From: Daniel Sanders Date: Tue, 21 Jan 2014 11:42:48 +0000 (+0000) Subject: [mips][sched] Split IIFcmp into II_C_CC_[SD] X-Git-Url: http://plrg.eecs.uci.edu/git/?p=oota-llvm.git;a=commitdiff_plain;h=65d38c3fcd1468f9129284a770103d4ec30363b3 [mips][sched] Split IIFcmp into II_C_CC_[SD] No functional change since the InstrItinData's have been duplicated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199728 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/Mips/MicroMipsInstrFPU.td b/lib/Target/Mips/MicroMipsInstrFPU.td index 8ff3b86ea76..65d345dc3da 100644 --- a/lib/Target/Mips/MicroMipsInstrFPU.td +++ b/lib/Target/Mips/MicroMipsInstrFPU.td @@ -32,9 +32,9 @@ def LUXC1_MM : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, IIFLoad>, def SUXC1_MM : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, IIFStore>, SWXC1_FM_MM<0x188>; -def FCMP_S32_MM : MMRel, CEQS_FT<"s", FGR32, IIFcmp, MipsFPCmp>, +def FCMP_S32_MM : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, CEQS_FM_MM<0>; -def FCMP_D32_MM : MMRel, CEQS_FT<"d", AFGR64, IIFcmp, MipsFPCmp>, +def FCMP_D32_MM : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM_MM<1>; def BC1F_MM : MMRel, BC1F_FT<"bc1f", brtarget_mm, IIBranch, MIPS_BRANCH_F>, diff --git a/lib/Target/Mips/MipsInstrFPU.td b/lib/Target/Mips/MipsInstrFPU.td index 12df06e5fdd..68a26c32a59 100644 --- a/lib/Target/Mips/MipsInstrFPU.td +++ b/lib/Target/Mips/MipsInstrFPU.td @@ -213,35 +213,38 @@ class CEQS_FT : +class C_COND_FT : InstSE<(outs), (ins RC:$fs, RC:$ft), - !strconcat("c.", CondStr, ".", Typestr, "\t$fs, $ft"), [], IIFcmp, + !strconcat("c.", CondStr, ".", Typestr, "\t$fs, $ft"), [], itin, FrmFR>; -multiclass C_COND_M fmt> { - def C_F_#NAME : C_COND_FT<"f", TypeStr, RC>, C_COND_FM; - def C_UN_#NAME : C_COND_FT<"un", TypeStr, RC>, C_COND_FM; - def C_EQ_#NAME : C_COND_FT<"eq", TypeStr, RC>, C_COND_FM; - def C_UEQ_#NAME : C_COND_FT<"ueq", TypeStr, RC>, C_COND_FM; - def C_OLT_#NAME : C_COND_FT<"olt", TypeStr, RC>, C_COND_FM; - def C_ULT_#NAME : C_COND_FT<"ult", TypeStr, RC>, C_COND_FM; - def C_OLE_#NAME : C_COND_FT<"ole", TypeStr, RC>, C_COND_FM; - def C_ULE_#NAME : C_COND_FT<"ule", TypeStr, RC>, C_COND_FM; - def C_SF_#NAME : C_COND_FT<"sf", TypeStr, RC>, C_COND_FM; - def C_NGLE_#NAME : C_COND_FT<"ngle", TypeStr, RC>, C_COND_FM; - def C_SEQ_#NAME : C_COND_FT<"seq", TypeStr, RC>, C_COND_FM; - def C_NGL_#NAME : C_COND_FT<"ngl", TypeStr, RC>, C_COND_FM; - def C_LT_#NAME : C_COND_FT<"lt", TypeStr, RC>, C_COND_FM; - def C_NGE_#NAME : C_COND_FT<"nge", TypeStr, RC>, C_COND_FM; - def C_LE_#NAME : C_COND_FT<"le", TypeStr, RC>, C_COND_FM; - def C_NGT_#NAME : C_COND_FT<"ngt", TypeStr, RC>, C_COND_FM; -} - -defm S : C_COND_M<"s", FGR32Opnd, 16>; -defm D32 : C_COND_M<"d", AFGR64Opnd, 17>, - Requires<[NotFP64bit, HasStdEnc]>; +multiclass C_COND_M fmt, + InstrItinClass itin> { + def C_F_#NAME : C_COND_FT<"f", TypeStr, RC, itin>, C_COND_FM; + def C_UN_#NAME : C_COND_FT<"un", TypeStr, RC, itin>, C_COND_FM; + def C_EQ_#NAME : C_COND_FT<"eq", TypeStr, RC, itin>, C_COND_FM; + def C_UEQ_#NAME : C_COND_FT<"ueq", TypeStr, RC, itin>, C_COND_FM; + def C_OLT_#NAME : C_COND_FT<"olt", TypeStr, RC, itin>, C_COND_FM; + def C_ULT_#NAME : C_COND_FT<"ult", TypeStr, RC, itin>, C_COND_FM; + def C_OLE_#NAME : C_COND_FT<"ole", TypeStr, RC, itin>, C_COND_FM; + def C_ULE_#NAME : C_COND_FT<"ule", TypeStr, RC, itin>, C_COND_FM; + def C_SF_#NAME : C_COND_FT<"sf", TypeStr, RC, itin>, C_COND_FM; + def C_NGLE_#NAME : C_COND_FT<"ngle", TypeStr, RC, itin>, C_COND_FM; + def C_SEQ_#NAME : C_COND_FT<"seq", TypeStr, RC, itin>, C_COND_FM; + def C_NGL_#NAME : C_COND_FT<"ngl", TypeStr, RC, itin>, C_COND_FM; + def C_LT_#NAME : C_COND_FT<"lt", TypeStr, RC, itin>, C_COND_FM; + def C_NGE_#NAME : C_COND_FT<"nge", TypeStr, RC, itin>, C_COND_FM; + def C_LE_#NAME : C_COND_FT<"le", TypeStr, RC, itin>, C_COND_FM; + def C_NGT_#NAME : C_COND_FT<"ngt", TypeStr, RC, itin>, C_COND_FM; +} + +defm S : C_COND_M<"s", FGR32Opnd, 16, II_C_CC_S>; +defm D32 : C_COND_M<"d", AFGR64Opnd, 17, II_C_CC_D>, + Requires<[NotFP64bit, HasStdEnc]>; let DecoderNamespace = "Mips64" in -defm D64 : C_COND_M<"d", FGR64Opnd, 17>, Requires<[IsFP64bit, HasStdEnc]>; +defm D64 : C_COND_M<"d", FGR64Opnd, 17, II_C_CC_D>, + Requires<[IsFP64bit, HasStdEnc]>; //===----------------------------------------------------------------------===// // Floating Point Instructions @@ -508,11 +511,11 @@ def MIPS_FCOND_LE : PatLeaf<(i32 14)>; def MIPS_FCOND_NGT : PatLeaf<(i32 15)>; /// Floating Point Compare -def FCMP_S32 : MMRel, CEQS_FT<"s", FGR32, IIFcmp, MipsFPCmp>, CEQS_FM<16>; -def FCMP_D32 : MMRel, CEQS_FT<"d", AFGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>, +def FCMP_S32 : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, CEQS_FM<16>; +def FCMP_D32 : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>, Requires<[NotFP64bit, HasStdEnc]>; let DecoderNamespace = "Mips64" in -def FCMP_D64 : CEQS_FT<"d", FGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>, +def FCMP_D64 : CEQS_FT<"d", FGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>, Requires<[IsFP64bit, HasStdEnc]>; //===----------------------------------------------------------------------===// diff --git a/lib/Target/Mips/MipsSchedule.td b/lib/Target/Mips/MipsSchedule.td index 8ff405d9b4f..d31db0706c8 100644 --- a/lib/Target/Mips/MipsSchedule.td +++ b/lib/Target/Mips/MipsSchedule.td @@ -20,7 +20,6 @@ def IIAlu : InstrItinClass; def IILoad : InstrItinClass; def IIStore : InstrItinClass; def IIBranch : InstrItinClass; -def IIFcmp : InstrItinClass; def IIFadd : InstrItinClass; def IIFmulSingle : InstrItinClass; def IIFmulDouble : InstrItinClass; @@ -46,6 +45,8 @@ def II_CLO : InstrItinClass; def II_CLZ : InstrItinClass; def II_CTC1 : InstrItinClass; def II_CVT : InstrItinClass; +def II_C_CC_D : InstrItinClass; // Any c..d instruction +def II_C_CC_S : InstrItinClass; // Any c..s instruction def II_DADDIU : InstrItinClass; def II_DADDU : InstrItinClass; def II_DDIV : InstrItinClass; @@ -197,7 +198,8 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [ InstrItinData]>, InstrItinData]>, InstrItinData]>, - InstrItinData]>, + InstrItinData]>, + InstrItinData]>, InstrItinData]>, InstrItinData]>, InstrItinData]>,