From: Craig Topper <craig.topper@gmail.com>
Date: Wed, 14 Oct 2015 05:37:38 +0000 (+0000)
Subject: [X86] Add XSAVE feature flags to their various processors.
X-Git-Url: http://plrg.eecs.uci.edu/git/?p=oota-llvm.git;a=commitdiff_plain;h=32e9bbaf96e02beea4be6177d3ea800f06a150bd

[X86] Add XSAVE feature flags to their various processors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250268 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86.td b/lib/Target/X86/X86.td
index 3379a4254c5..90d84ed8063 100644
--- a/lib/Target/X86/X86.td
+++ b/lib/Target/X86/X86.td
@@ -347,7 +347,9 @@ class SandyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
   FeatureSlowUAMem32,
   FeaturePOPCNT,
   FeatureAES,
-  FeaturePCLMUL
+  FeaturePCLMUL,
+  FeatureXSAVE,
+  FeatureXSAVEOPT
 ]>;
 def : SandyBridgeProc<"sandybridge">;
 def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
@@ -361,6 +363,8 @@ class IvyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
   FeaturePOPCNT,
   FeatureAES,
   FeaturePCLMUL,
+  FeatureXSAVE,
+  FeatureXSAVEOPT,
   FeatureRDRAND,
   FeatureF16C,
   FeatureFSGSBase
@@ -377,6 +381,8 @@ class HaswellProc<string Name> : ProcessorModel<Name, HaswellModel, [
   FeatureAES,
   FeaturePCLMUL,
   FeatureRDRAND,
+  FeatureXSAVE,
+  FeatureXSAVEOPT,
   FeatureF16C,
   FeatureFSGSBase,
   FeatureMOVBE,
@@ -399,6 +405,8 @@ class BroadwellProc<string Name> : ProcessorModel<Name, HaswellModel, [
   FeaturePOPCNT,
   FeatureAES,
   FeaturePCLMUL,
+  FeatureXSAVE,
+  FeatureXSAVEOPT,
   FeatureRDRAND,
   FeatureF16C,
   FeatureFSGSBase,
@@ -454,6 +462,8 @@ class SkylakeProc<string Name> : ProcessorModel<Name, HaswellModel, [
   FeaturePOPCNT,
   FeatureAES,
   FeaturePCLMUL,
+  FeatureXSAVE,
+  FeatureXSAVEOPT,
   FeatureRDRAND,
   FeatureF16C,
   FeatureFSGSBase,
@@ -467,7 +477,9 @@ class SkylakeProc<string Name> : ProcessorModel<Name, HaswellModel, [
   FeatureADX,
   FeatureRDSEED,
   FeatureSlowIncDec,
-  FeatureMPX
+  FeatureMPX,
+  FeatureXSAVEC,
+  FeatureXSAVES
 ]>;
 def : SkylakeProc<"skylake">;
 def : SkylakeProc<"skx">; // Legacy alias.
@@ -527,6 +539,7 @@ def : Proc<"btver1", [
   FeaturePRFCHW,
   FeatureLZCNT,
   FeaturePOPCNT,
+  FeatureXSAVE,
   FeatureSlowSHLD
 ]>;
 
@@ -544,6 +557,8 @@ def : ProcessorModel<"btver2", BtVer2Model, [
   FeatureMOVBE,
   FeatureLZCNT,
   FeaturePOPCNT,
+  FeatureXSAVE,
+  FeatureXSAVEOPT,
   FeatureSlowSHLD
 ]>;
 
@@ -560,6 +575,7 @@ def : Proc<"bdver1", [
   FeatureSSE4A,
   FeatureLZCNT,
   FeaturePOPCNT,
+  FeatureXSAVE,
   FeatureSlowSHLD
 ]>;
 // Piledriver
@@ -576,6 +592,7 @@ def : Proc<"bdver2", [
   FeatureF16C,
   FeatureLZCNT,
   FeaturePOPCNT,
+  FeatureXSAVE,
   FeatureBMI,
   FeatureTBM,
   FeatureFMA,
@@ -596,9 +613,11 @@ def : Proc<"bdver3", [
   FeatureF16C,
   FeatureLZCNT,
   FeaturePOPCNT,
+  FeatureXSAVE,
   FeatureBMI,
   FeatureTBM,
   FeatureFMA,
+  FeatureXSAVEOPT,
   FeatureSlowSHLD,
   FeatureFSGSBase
 ]>;
@@ -616,11 +635,12 @@ def : Proc<"bdver4", [
   FeatureF16C,
   FeatureLZCNT,
   FeaturePOPCNT,
+  FeatureXSAVE,
   FeatureBMI,
   FeatureBMI2,
   FeatureTBM,
   FeatureFMA,
-  FeatureSSE4A,
+  FeatureXSAVEOPT,
   FeatureFSGSBase
 ]>;