From: Eric Christopher Date: Fri, 18 Jul 2014 23:25:04 +0000 (+0000) Subject: In preparation for replacing the whole subtarget on the target machine, X-Git-Url: http://plrg.eecs.uci.edu/git/?p=oota-llvm.git;a=commitdiff_plain;h=286fbd19f3f781ec885cca1b8ad8a8ead0459652 In preparation for replacing the whole subtarget on the target machine, have target lowering take the subtarget explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213426 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/Mips/Mips16ISelLowering.cpp b/lib/Target/Mips/Mips16ISelLowering.cpp index d4cfaf4b996..587925df946 100644 --- a/lib/Target/Mips/Mips16ISelLowering.cpp +++ b/lib/Target/Mips/Mips16ISelLowering.cpp @@ -118,8 +118,9 @@ static const Mips16IntrinsicHelperType Mips16IntrinsicHelper[] = { {"truncf", "__mips16_call_stub_sf_1"}, }; -Mips16TargetLowering::Mips16TargetLowering(MipsTargetMachine &TM) - : MipsTargetLowering(TM) { +Mips16TargetLowering::Mips16TargetLowering(MipsTargetMachine &TM, + const MipsSubtarget &STI) + : MipsTargetLowering(TM, STI) { // Set up the register classes addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass); @@ -150,8 +151,9 @@ Mips16TargetLowering::Mips16TargetLowering(MipsTargetMachine &TM) } const MipsTargetLowering * -llvm::createMips16TargetLowering(MipsTargetMachine &TM) { - return new Mips16TargetLowering(TM); +llvm::createMips16TargetLowering(MipsTargetMachine &TM, + const MipsSubtarget &STI) { + return new Mips16TargetLowering(TM, STI); } bool diff --git a/lib/Target/Mips/Mips16ISelLowering.h b/lib/Target/Mips/Mips16ISelLowering.h index 2a5eec5b40d..e7e4d7f651d 100644 --- a/lib/Target/Mips/Mips16ISelLowering.h +++ b/lib/Target/Mips/Mips16ISelLowering.h @@ -19,7 +19,8 @@ namespace llvm { class Mips16TargetLowering : public MipsTargetLowering { public: - explicit Mips16TargetLowering(MipsTargetMachine &TM); + explicit Mips16TargetLowering(MipsTargetMachine &TM, + const MipsSubtarget &STI); bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AddrSpace, bool *Fast) const override; diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index 9eb93012ab3..12b339188b1 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -208,9 +208,9 @@ const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { } } -MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM) - : TargetLowering(TM, new MipsTargetObjectFile()), - Subtarget(TM.getSubtarget()) { +MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM, + const MipsSubtarget &STI) + : TargetLowering(TM, new MipsTargetObjectFile()), Subtarget(STI) { // Mips does not have i1 type, so use i32 for // setcc operations results (slt, sgt, ...). setBooleanContents(ZeroOrOneBooleanContent); @@ -403,11 +403,12 @@ MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM) isMicroMips = Subtarget.inMicroMipsMode(); } -const MipsTargetLowering *MipsTargetLowering::create(MipsTargetMachine &TM) { - if (TM.getSubtargetImpl()->inMips16Mode()) - return llvm::createMips16TargetLowering(TM); +const MipsTargetLowering *MipsTargetLowering::create(MipsTargetMachine &TM, + const MipsSubtarget &STI) { + if (STI.inMips16Mode()) + return llvm::createMips16TargetLowering(TM, STI); - return llvm::createMipsSETargetLowering(TM); + return llvm::createMipsSETargetLowering(TM, STI); } // Create a fast isel object. diff --git a/lib/Target/Mips/MipsISelLowering.h b/lib/Target/Mips/MipsISelLowering.h index 1a23e0d109c..10e4e0b4864 100644 --- a/lib/Target/Mips/MipsISelLowering.h +++ b/lib/Target/Mips/MipsISelLowering.h @@ -214,9 +214,11 @@ namespace llvm { class MipsTargetLowering : public TargetLowering { bool isMicroMips; public: - explicit MipsTargetLowering(MipsTargetMachine &TM); + explicit MipsTargetLowering(MipsTargetMachine &TM, + const MipsSubtarget &STI); - static const MipsTargetLowering *create(MipsTargetMachine &TM); + static const MipsTargetLowering *create(MipsTargetMachine &TM, + const MipsSubtarget &STI); /// createFastISel - This method returns a target specific FastISel object, /// or null if the target does not support "fast" ISel. @@ -611,8 +613,10 @@ namespace llvm { }; /// Create MipsTargetLowering objects. - const MipsTargetLowering *createMips16TargetLowering(MipsTargetMachine &TM); - const MipsTargetLowering *createMipsSETargetLowering(MipsTargetMachine &TM); + const MipsTargetLowering * + createMips16TargetLowering(MipsTargetMachine &TM, const MipsSubtarget &STI); + const MipsTargetLowering * + createMipsSETargetLowering(MipsTargetMachine &TM, const MipsSubtarget &STI); namespace Mips { FastISel *createFastISel(FunctionLoweringInfo &funcInfo, diff --git a/lib/Target/Mips/MipsSEISelLowering.cpp b/lib/Target/Mips/MipsSEISelLowering.cpp index 3ef3908df79..8173615cdcb 100644 --- a/lib/Target/Mips/MipsSEISelLowering.cpp +++ b/lib/Target/Mips/MipsSEISelLowering.cpp @@ -34,8 +34,9 @@ static cl::opt NoDPLoadStore("mno-ldc1-sdc1", cl::init(false), "stores to their single precision " "counterparts")); -MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM) - : MipsTargetLowering(TM) { +MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM, + const MipsSubtarget &STI) + : MipsTargetLowering(TM, STI) { // Set up the register classes addRegisterClass(MVT::i32, &Mips::GPR32RegClass); @@ -226,8 +227,9 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM) } const MipsTargetLowering * -llvm::createMipsSETargetLowering(MipsTargetMachine &TM) { - return new MipsSETargetLowering(TM); +llvm::createMipsSETargetLowering(MipsTargetMachine &TM, + const MipsSubtarget &STI) { + return new MipsSETargetLowering(TM, STI); } const TargetRegisterClass * diff --git a/lib/Target/Mips/MipsSEISelLowering.h b/lib/Target/Mips/MipsSEISelLowering.h index 13ef6fce887..00d86834be0 100644 --- a/lib/Target/Mips/MipsSEISelLowering.h +++ b/lib/Target/Mips/MipsSEISelLowering.h @@ -20,7 +20,8 @@ namespace llvm { class MipsSETargetLowering : public MipsTargetLowering { public: - explicit MipsSETargetLowering(MipsTargetMachine &TM); + explicit MipsSETargetLowering(MipsTargetMachine &TM, + const MipsSubtarget &STI); /// \brief Enable MSA support for the given integer type and Register /// class. diff --git a/lib/Target/Mips/MipsSubtarget.cpp b/lib/Target/Mips/MipsSubtarget.cpp index 71332eb9eea..f801dcd9e94 100644 --- a/lib/Target/Mips/MipsSubtarget.cpp +++ b/lib/Target/Mips/MipsSubtarget.cpp @@ -117,7 +117,7 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS, TM))), TSInfo(DL), JITInfo(), InstrInfo(MipsInstrInfo::create(*this)), FrameLowering(MipsFrameLowering::create(*TM, *this)), - TLInfo(MipsTargetLowering::create(*TM)) { + TLInfo(MipsTargetLowering::create(*TM, *this)) { PreviousInMips16Mode = InMips16Mode; @@ -256,7 +256,7 @@ void MipsSubtarget::setHelperClassesMips16() { if (!InstrInfo16) { InstrInfo.reset(MipsInstrInfo::create(*this)); FrameLowering.reset(MipsFrameLowering::create(*TM, *this)); - TLInfo.reset(MipsTargetLowering::create(*TM)); + TLInfo.reset(MipsTargetLowering::create(*TM, *this)); } else { InstrInfo16.swap(InstrInfo); FrameLowering16.swap(FrameLowering); @@ -274,7 +274,7 @@ void MipsSubtarget::setHelperClassesMipsSE() { if (!InstrInfoSE) { InstrInfo.reset(MipsInstrInfo::create(*this)); FrameLowering.reset(MipsFrameLowering::create(*TM, *this)); - TLInfo.reset(MipsTargetLowering::create(*TM)); + TLInfo.reset(MipsTargetLowering::create(*TM, *this)); } else { InstrInfoSE.swap(InstrInfo); FrameLoweringSE.swap(FrameLowering);