From: Quentin Colombet <qcolombet@apple.com>
Date: Mon, 14 Dec 2015 23:12:40 +0000 (+0000)
Subject: [X86] Add relaxtion logic for ADC instructions.
X-Git-Url: http://plrg.eecs.uci.edu/git/?p=oota-llvm.git;a=commitdiff_plain;h=265bc7dab126aadfb12f7ea40f25ae0bf85cff33

[X86] Add relaxtion logic for ADC instructions.

Prior to this patch, we would wrongly stick to the variant with imm8 encoding
even when the relocation could not fit that size.

rdar://problem/23785506


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255570 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp b/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
index 914ccdfb49a..4136943a117 100644
--- a/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
+++ b/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
@@ -204,6 +204,14 @@ static unsigned getRelaxedOpcodeArith(unsigned Op) {
   case X86::ADD64ri8: return X86::ADD64ri32;
   case X86::ADD64mi8: return X86::ADD64mi32;
 
+   // ADC
+  case X86::ADC16ri8: return X86::ADC16ri;
+  case X86::ADC16mi8: return X86::ADC16mi;
+  case X86::ADC32ri8: return X86::ADC32ri;
+  case X86::ADC32mi8: return X86::ADC32mi;
+  case X86::ADC64ri8: return X86::ADC64ri32;
+  case X86::ADC64mi8: return X86::ADC64mi32;
+
     // SUB
   case X86::SUB16ri8: return X86::SUB16ri;
   case X86::SUB16mi8: return X86::SUB16mi;
diff --git a/test/MC/ELF/relax-arith.s b/test/MC/ELF/relax-arith.s
index 15e44ebff7e..0e0d0a52d79 100644
--- a/test/MC/ELF/relax-arith.s
+++ b/test/MC/ELF/relax-arith.s
@@ -123,3 +123,19 @@ bar:
         .section push,"x"
         pushw $foo
         push  $foo
+
+// CHECK:      Disassembly of section adc:
+// CHECK-NEXT: adc:
+// CHECK-NEXT:   0: 66 81 d3 00 00                       adcw $0, %bx
+// CHECK-NEXT:   5: 66 81 14 25 00 00 00 00 00 00        adcw $0, 0
+// CHECK-NEXT:   f: 81 d3 00 00 00 00                    adcl $0, %ebx
+// CHECK-NEXT:  15: 81 14 25 00 00 00 00 00 00 00 00     adcl $0, 0
+// CHECK-NEXT:  20: 48 81 d3 00 00 00 00                 adcq $0, %rbx
+// CHECK-NEXT:  27: 48 81 14 25 00 00 00 00 00 00 00 00  adcq $0, 0
+        .section adc,"x"
+        adc  $foo, %bx
+        adcw $foo, bar
+        adc  $foo, %ebx
+        adcl $foo, bar
+        adc  $foo, %rbx
+        adcq $foo, bar