From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Thu, 24 Dec 2015 05:14:55 +0000 (+0000)
Subject: AMDGPU: Fix getRegisterBitWidth for vectors
X-Git-Url: http://plrg.eecs.uci.edu/git/?p=oota-llvm.git;a=commitdiff_plain;h=1e79dfc2eeffa4cb5b44ba73dbcccdacd4779e9b

AMDGPU: Fix getRegisterBitWidth for vectors

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256362 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp b/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
index c20a66e4481..54a003d6a9c 100644
--- a/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+++ b/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
@@ -74,7 +74,9 @@ unsigned AMDGPUTTIImpl::getNumberOfRegisters(bool Vec) {
   return 4 * 128; // XXX - 4 channels. Should these count as vector instead?
 }
 
-unsigned AMDGPUTTIImpl::getRegisterBitWidth(bool) { return 32; }
+unsigned AMDGPUTTIImpl::getRegisterBitWidth(bool Vector) {
+  return Vector ? 0 : 32;
+}
 
 unsigned AMDGPUTTIImpl::getMaxInterleaveFactor(unsigned VF) {
   // Semi-arbitrary large amount.