From: Daniel Sanders <daniel.sanders@imgtec.com>
Date: Wed, 9 Jul 2014 10:47:26 +0000 (+0000)
Subject: [mips][mips64r6] Correct select patterns that have the condition or true/false values... 
X-Git-Url: http://plrg.eecs.uci.edu/git/?p=oota-llvm.git;a=commitdiff_plain;h=1285b3130b103711fb6e65beeb5d4bcd1a26b433

[mips][mips64r6] Correct select patterns that have the condition or true/false values backwards

Summary: This bug caused SingleSource/Regression/C/uint64_to_float and SingleSource/UnitTests/2002-05-02-CastTest3 to fail (among others).

Differential Revision: http://reviews.llvm.org/D4388


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212608 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/Mips/Mips32r6InstrInfo.td b/lib/Target/Mips/Mips32r6InstrInfo.td
index bf60685e637..d06e5ca2258 100644
--- a/lib/Target/Mips/Mips32r6InstrInfo.td
+++ b/lib/Target/Mips/Mips32r6InstrInfo.td
@@ -786,14 +786,14 @@ def : MipsPat<(select i32:$cond, i32:$t, i32:$f),
               (OR (SELNEZ i32:$t, i32:$cond), (SELEQZ i32:$f, i32:$cond))>,
               ISA_MIPS32R6;
 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i32:$t, i32:$f),
-              (OR (SELNEZ i32:$t, i32:$cond), (SELEQZ i32:$f, i32:$cond))>,
+              (OR (SELEQZ i32:$t, i32:$cond), (SELNEZ i32:$f, i32:$cond))>,
               ISA_MIPS32R6;
 def : MipsPat<(select (i32 (setne i32:$cond, immz)), i32:$t, i32:$f),
-              (OR (SELNEZ i32:$f, i32:$cond), (SELEQZ i32:$t, i32:$cond))>,
+              (OR (SELNEZ i32:$t, i32:$cond), (SELEQZ i32:$f, i32:$cond))>,
               ISA_MIPS32R6;
 def : MipsPat<(select (i32 (seteq i32:$cond, immZExt16:$imm)), i32:$t, i32:$f),
-              (OR (SELNEZ i32:$t, (XORi i32:$cond, immZExt16:$imm)),
-                  (SELEQZ i32:$f, (XORi i32:$cond, immZExt16:$imm)))>,
+              (OR (SELEQZ i32:$t, (XORi i32:$cond, immZExt16:$imm)),
+                  (SELNEZ i32:$f, (XORi i32:$cond, immZExt16:$imm)))>,
               ISA_MIPS32R6;
 def : MipsPat<(select (i32 (setne i32:$cond, immZExt16:$imm)), i32:$t, i32:$f),
               (OR (SELNEZ i32:$f, (XORi i32:$cond, immZExt16:$imm)),
@@ -801,13 +801,13 @@ def : MipsPat<(select (i32 (setne i32:$cond, immZExt16:$imm)), i32:$t, i32:$f),
               ISA_MIPS32R6;
 def : MipsPat<(select (i32 (setgt i32:$cond, immSExt16Plus1:$imm)), i32:$t,
                       i32:$f),
-              (OR (SELNEZ i32:$t, (SLTi i32:$cond, (Plus1 imm:$imm))),
-                  (SELEQZ i32:$f, (SLTi i32:$cond, (Plus1 imm:$imm))))>,
+              (OR (SELEQZ i32:$t, (SLTi i32:$cond, (Plus1 imm:$imm))),
+                  (SELNEZ i32:$f, (SLTi i32:$cond, (Plus1 imm:$imm))))>,
               ISA_MIPS32R6;
 def : MipsPat<(select (i32 (setugt i32:$cond, immSExt16Plus1:$imm)),
                       i32:$t, i32:$f),
-              (OR (SELNEZ i32:$t, (SLTiu i32:$cond, (Plus1 imm:$imm))),
-                  (SELEQZ i32:$f, (SLTiu i32:$cond, (Plus1 imm:$imm))))>,
+              (OR (SELEQZ i32:$t, (SLTiu i32:$cond, (Plus1 imm:$imm))),
+                  (SELNEZ i32:$f, (SLTiu i32:$cond, (Plus1 imm:$imm))))>,
               ISA_MIPS32R6;
 
 def : MipsPat<(select i32:$cond, i32:$t, immz),
diff --git a/lib/Target/Mips/Mips64r6InstrInfo.td b/lib/Target/Mips/Mips64r6InstrInfo.td
index 5452175f258..63cf60b44cd 100644
--- a/lib/Target/Mips/Mips64r6InstrInfo.td
+++ b/lib/Target/Mips/Mips64r6InstrInfo.td
@@ -125,36 +125,36 @@ def : MipsPat<(select i64:$cond, i64:$t, i64:$f),
                     (SELEQZ64 i64:$f, i64:$cond))>,
               ISA_MIPS64R6;
 def : MipsPat<(select (i32 (seteq i64:$cond, immz)), i64:$t, i64:$f),
-              (OR64 (SELNEZ64 i64:$t, i64:$cond),
-                    (SELEQZ64 i64:$f, i64:$cond))>,
+              (OR64 (SELEQZ64 i64:$t, i64:$cond),
+                    (SELNEZ64 i64:$f, i64:$cond))>,
               ISA_MIPS64R6;
 def : MipsPat<(select (i32 (setne i64:$cond, immz)), i64:$t, i64:$f),
-              (OR64 (SELNEZ64 i64:$f, i64:$cond),
-                    (SELEQZ64 i64:$t, i64:$cond))>,
+              (OR64 (SELNEZ64 i64:$t, i64:$cond),
+                    (SELEQZ64 i64:$f, i64:$cond))>,
               ISA_MIPS64R6;
 def : MipsPat<(select (i32 (seteq i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f),
-              (OR64 (SELNEZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)),
-                    (SELEQZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)))>,
+              (OR64 (SELEQZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)),
+                    (SELNEZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)))>,
               ISA_MIPS64R6;
 def : MipsPat<(select (i32 (setne i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f),
-              (OR64 (SELNEZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)),
-                    (SELEQZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)))>,
+              (OR64 (SELNEZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)),
+                    (SELEQZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)))>,
               ISA_MIPS64R6;
 def : MipsPat<
   (select (i32 (setgt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f),
-  (OR64 (SELNEZ64 i64:$t,
+  (OR64 (SELEQZ64 i64:$t,
                   (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),
                                  sub_32)),
-        (SELEQZ64 i64:$f,
+        (SELNEZ64 i64:$f,
                   (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),
                                  sub_32)))>,
   ISA_MIPS64R6;
 def : MipsPat<
   (select (i32 (setugt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f),
-  (OR64 (SELNEZ64 i64:$t,
+  (OR64 (SELEQZ64 i64:$t,
                   (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
                                  sub_32)),
-        (SELEQZ64 i64:$f,
+        (SELNEZ64 i64:$f,
                   (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
                                  sub_32)))>,
   ISA_MIPS64R6;
@@ -177,17 +177,17 @@ def : MipsPat<(select i32:$cond, i64:$t, i64:$f),
                     (SELEQZ64 i64:$f, (SLL64_32 i32:$cond)))>,
               ISA_MIPS64R6;
 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i64:$t, i64:$f),
-              (OR64 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond)),
-                    (SELEQZ64 i64:$f, (SLL64_32 i32:$cond)))>,
+              (OR64 (SELEQZ64 i64:$t, (SLL64_32 i32:$cond)),
+                    (SELNEZ64 i64:$f, (SLL64_32 i32:$cond)))>,
               ISA_MIPS64R6;
 def : MipsPat<(select (i32 (setne i32:$cond, immz)), i64:$t, i64:$f),
-              (OR64 (SELNEZ64 i64:$f, (SLL64_32 i32:$cond)),
-                    (SELEQZ64 i64:$t, (SLL64_32 i32:$cond)))>,
+              (OR64 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond)),
+                    (SELEQZ64 i64:$f, (SLL64_32 i32:$cond)))>,
               ISA_MIPS64R6;
 def : MipsPat<(select (i32 (seteq i32:$cond, immZExt16:$imm)), i64:$t, i64:$f),
-              (OR64 (SELNEZ64 i64:$t, (SLL64_32 (XORi i32:$cond,
+              (OR64 (SELEQZ64 i64:$t, (SLL64_32 (XORi i32:$cond,
                                                       immZExt16:$imm))),
-                    (SELEQZ64 i64:$f, (SLL64_32 (XORi i32:$cond,
+                    (SELNEZ64 i64:$f, (SLL64_32 (XORi i32:$cond,
                                                       immZExt16:$imm))))>,
               ISA_MIPS64R6;
 def : MipsPat<(select (i32 (setne i32:$cond, immZExt16:$imm)), i64:$t, i64:$f),
diff --git a/test/CodeGen/Mips/cmov.ll b/test/CodeGen/Mips/cmov.ll
index 61f398314de..999bdb4d493 100644
--- a/test/CodeGen/Mips/cmov.ll
+++ b/test/CodeGen/Mips/cmov.ll
@@ -18,9 +18,9 @@
 
 ; 32-CMP-DAG:   lw $[[R0:[0-9]+]], %got(i3)
 ; 32-CMP-DAG:   addiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got(i1)
-; 32-CMP-DAG:   seleqz $[[T0:[0-9]+]], $[[R1]], $4
-; 32-CMP-DAG:   selnez $[[T1:[0-9]+]], $[[R0]], $4
-; 32-CMP-DAG:   or $[[T2:[0-9]+]], $[[T1]], $[[T0]]
+; 32-CMP-DAG:   selnez $[[T0:[0-9]+]], $[[R1]], $4
+; 32-CMP-DAG:   seleqz $[[T1:[0-9]+]], $[[R0]], $4
+; 32-CMP-DAG:   or $[[T2:[0-9]+]], $[[T0]], $[[T1]]
 ; 32-CMP-DAG:   lw $2, 0($[[T2]])
 
 ; 64-CMOV-DAG:  ldr $[[R0:[0-9]+]]
@@ -33,9 +33,9 @@
 ;        (setcc's result is i32 so bits 32-63 are undefined). It's not really
 ;        needed.
 ; 64-CMP-DAG:   sll $[[CC:[0-9]+]], $4, 0
-; 64-CMP-DAG:   seleqz $[[T0:[0-9]+]], $[[R1]], $[[CC]]
-; 64-CMP-DAG:   selnez $[[T1:[0-9]+]], $[[R0]], $[[CC]]
-; 64-CMP-DAG:   or $[[T2:[0-9]+]], $[[T1]], $[[T0]]
+; 64-CMP-DAG:   selnez $[[T0:[0-9]+]], $[[R1]], $[[CC]]
+; 64-CMP-DAG:   seleqz $[[T1:[0-9]+]], $[[R0]], $[[CC]]
+; 64-CMP-DAG:   or $[[T2:[0-9]+]], $[[T0]], $[[T1]]
 ; 64-CMP-DAG:   ld $2, 0($[[T2]])
 
 define i32* @cmov1(i32 %s) nounwind readonly {
@@ -58,9 +58,9 @@ entry:
 
 ; 32-CMP-DAG:   addiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got(d)
 ; 32-CMP-DAG:   addiu $[[R0:[0-9]+]], ${{[0-9]+}}, %got(c)
-; 32-CMP-DAG:   seleqz $[[T0:[0-9]+]], $[[R0]], $4
-; 32-CMP-DAG:   selnez $[[T1:[0-9]+]], $[[R1]], $4
-; 32-CMP-DAG:   or $[[T2:[0-9]+]], $[[T1]], $[[T0]]
+; 32-CMP-DAG:   selnez $[[T0:[0-9]+]], $[[R0]], $4
+; 32-CMP-DAG:   seleqz $[[T1:[0-9]+]], $[[R1]], $4
+; 32-CMP-DAG:   or $[[T2:[0-9]+]], $[[T0]], $[[T1]]
 ; 32-CMP-DAG:   lw $2, 0($[[T2]])
 
 ; 64-CMOV:      daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got_disp(d)
@@ -73,9 +73,9 @@ entry:
 ;        (setcc's result is i32 so bits 32-63 are undefined). It's not really
 ;        needed.
 ; 64-CMP-DAG:   sll $[[CC:[0-9]+]], $4, 0
-; 64-CMP-DAG:   seleqz $[[T0:[0-9]+]], $[[R0]], $[[CC]]
-; 64-CMP-DAG:   selnez $[[T1:[0-9]+]], $[[R1]], $[[CC]]
-; 64-CMP-DAG:   or $[[T2:[0-9]+]], $[[T1]], $[[T0]]
+; 64-CMP-DAG:   selnez $[[T0:[0-9]+]], $[[R0]], $[[CC]]
+; 64-CMP-DAG:   seleqz $[[T1:[0-9]+]], $[[R1]], $[[CC]]
+; 64-CMP-DAG:   or $[[T2:[0-9]+]], $[[T0]], $[[T1]]
 ; 64-CMP-DAG:   lw $2, 0($[[T2]])
 
 define i32 @cmov2(i32 %s) nounwind readonly {
@@ -97,16 +97,16 @@ entry:
 ; 32-CMOV:      movz ${{[26]}}, $5, $[[R0]]
 
 ; 32-CMP-DAG:   xori $[[CC:[0-9]+]], $4, 234
-; 32-CMP-DAG:   selnez $[[T0:[0-9]+]], $5, $[[CC]]
-; 32-CMP-DAG:   seleqz $[[T1:[0-9]+]], $6, $[[CC]]
+; 32-CMP-DAG:   seleqz $[[T0:[0-9]+]], $5, $[[CC]]
+; 32-CMP-DAG:   selnez $[[T1:[0-9]+]], $6, $[[CC]]
 ; 32-CMP-DAG:   or $2, $[[T0]], $[[T1]]
 
 ; 64-CMOV:      xori $[[R0:[0-9]+]], $4, 234
 ; 64-CMOV:      movz ${{[26]}}, $5, $[[R0]]
 
 ; 64-CMP-DAG:   xori $[[CC:[0-9]+]], $4, 234
-; 64-CMP-DAG:   selnez $[[T0:[0-9]+]], $5, $[[CC]]
-; 64-CMP-DAG:   seleqz $[[T1:[0-9]+]], $6, $[[CC]]
+; 64-CMP-DAG:   seleqz $[[T0:[0-9]+]], $5, $[[CC]]
+; 64-CMP-DAG:   selnez $[[T1:[0-9]+]], $6, $[[CC]]
 ; 64-CMP-DAG:   or $2, $[[T0]], $[[T1]]
 
 define i32 @cmov3(i32 %a, i32 %b, i32 %c) nounwind readnone {
@@ -131,10 +131,10 @@ entry:
 ; 32-CMP-DAG:  xori $[[R0:[0-9]+]], $4, 234
 ; 32-CMP-DAG:  lw $[[R1:[0-9]+]], 16($sp)
 ; 32-CMP-DAG:  lw $[[R2:[0-9]+]], 20($sp)
-; 32-CMP-DAG:  selnez $[[T0:[0-9]+]], $6, $[[R0]]
-; 32-CMP-DAG:  selnez $[[T1:[0-9]+]], $7, $[[R0]]
-; 32-CMP-DAG:  seleqz $[[T2:[0-9]+]], $[[R1]], $[[R0]]
-; 32-CMP-DAG:  seleqz $[[T3:[0-9]+]], $[[R2]], $[[R0]]
+; 32-CMP-DAG:  seleqz $[[T0:[0-9]+]], $6, $[[R0]]
+; 32-CMP-DAG:  seleqz $[[T1:[0-9]+]], $7, $[[R0]]
+; 32-CMP-DAG:  selnez $[[T2:[0-9]+]], $[[R1]], $[[R0]]
+; 32-CMP-DAG:  selnez $[[T3:[0-9]+]], $[[R2]], $[[R0]]
 ; 32-CMP-DAG:  or $2, $[[T0]], $[[T2]]
 ; 32-CMP-DAG:  or $3, $[[T1]], $[[T3]]
 
@@ -142,8 +142,8 @@ entry:
 ; 64-CMOV: movz ${{[26]}}, $5, $[[R0]]
 
 ; 64-CMP-DAG:  xori $[[R0:[0-9]+]], $4, 234
-; 64-CMP-DAG:  selnez $[[T0:[0-9]+]], $5, $[[R0]]
-; 64-CMP-DAG:  seleqz $[[T1:[0-9]+]], $6, $[[R0]]
+; 64-CMP-DAG:  seleqz $[[T0:[0-9]+]], $5, $[[R0]]
+; 64-CMP-DAG:  selnez $[[T1:[0-9]+]], $6, $[[R0]]
 ; 64-CMP-DAG:  or $2, $[[T0]], $[[T1]]
 
 define i64 @cmov4(i32 %a, i64 %b, i64 %c) nounwind readnone {
@@ -172,8 +172,8 @@ entry:
 ; 32-CMP-DAG:  addiu $[[I5:[0-9]+]], $zero, 5
 ; 32-CMP-DAG:  slti $[[R0:[0-9]+]], $4, 32767
 ; FIXME: We can do better than this by using selccz to choose between +0 and +2
-; 32-CMP-DAG:  selnez $[[T0:[0-9]+]], $[[I3]], $[[R0]]
-; 32-CMP-DAG:  seleqz $[[T1:[0-9]+]], $[[I5]], $[[R0]]
+; 32-CMP-DAG:  seleqz $[[T0:[0-9]+]], $[[I3]], $[[R0]]
+; 32-CMP-DAG:  selnez $[[T1:[0-9]+]], $[[I5]], $[[R0]]
 ; 32-CMP-DAG:  or $2, $[[T0]], $[[T1]]
 
 ; 64-CMOV-DAG: addiu $[[I3:[0-9]+]], $zero, 3
@@ -185,8 +185,8 @@ entry:
 ; 64-CMP-DAG:  addiu $[[I5:[0-9]+]], $zero, 5
 ; 64-CMP-DAG:  slti $[[R0:[0-9]+]], $4, 32767
 ; FIXME: We can do better than this by using selccz to choose between +0 and +2
-; 64-CMP-DAG:  selnez $[[T0:[0-9]+]], $[[I3]], $[[R0]]
-; 64-CMP-DAG:  seleqz $[[T1:[0-9]+]], $[[I5]], $[[R0]]
+; 64-CMP-DAG:  seleqz $[[T0:[0-9]+]], $[[I3]], $[[R0]]
+; 64-CMP-DAG:  selnez $[[T1:[0-9]+]], $[[I5]], $[[R0]]
 ; 64-CMP-DAG:  or $2, $[[T0]], $[[T1]]
 
 define i32 @slti0(i32 %a) {
@@ -246,8 +246,8 @@ entry:
 ; 32-CMP-DAG:  addiu $[[I5:[0-9]+]], $zero, 5
 ; 32-CMP-DAG:  slti $[[R0:[0-9]+]], $4, -32768
 ; FIXME: We can do better than this by using selccz to choose between +0 and +2
-; 32-CMP-DAG:  selnez $[[T0:[0-9]+]], $[[I3]], $[[R0]]
-; 32-CMP-DAG:  seleqz $[[T1:[0-9]+]], $[[I5]], $[[R0]]
+; 32-CMP-DAG:  seleqz $[[T0:[0-9]+]], $[[I3]], $[[R0]]
+; 32-CMP-DAG:  selnez $[[T1:[0-9]+]], $[[I5]], $[[R0]]
 ; 32-CMP-DAG:  or $2, $[[T0]], $[[T1]]
 
 ; 64-CMOV-DAG: addiu $[[I3:[0-9]+]], $zero, 3
@@ -259,8 +259,8 @@ entry:
 ; 64-CMP-DAG:  addiu $[[I5:[0-9]+]], $zero, 5
 ; 64-CMP-DAG:  slti $[[R0:[0-9]+]], $4, -32768
 ; FIXME: We can do better than this by using selccz to choose between +0 and +2
-; 64-CMP-DAG:  selnez $[[T0:[0-9]+]], $[[I3]], $[[R0]]
-; 64-CMP-DAG:  seleqz $[[T1:[0-9]+]], $[[I5]], $[[R0]]
+; 64-CMP-DAG:  seleqz $[[T0:[0-9]+]], $[[I3]], $[[R0]]
+; 64-CMP-DAG:  selnez $[[T1:[0-9]+]], $[[I5]], $[[R0]]
 ; 64-CMP-DAG:  or $2, $[[T0]], $[[T1]]
 
 define i32 @slti2(i32 %a) {
@@ -329,8 +329,8 @@ entry:
 ; 32-CMP-DAG:   slt $[[CC0:[0-9]+]], $zero, $4
 ; 32-CMP-DAG:   addiu $[[I32766:[0-9]+]], $zero, 32766
 ; 32-CMP-DAG:   sltu $[[CC1:[0-9]+]], $[[I32766]], $5
-; 32-CMP-DAG:   seleqz $[[CC2:[0-9]+]], $[[CC0]], $4
-; 32-CMP-DAG:   selnez $[[CC3:[0-9]+]], $[[CC1]], $4
+; 32-CMP-DAG:   selnez $[[CC2:[0-9]+]], $[[CC0]], $4
+; 32-CMP-DAG:   seleqz $[[CC3:[0-9]+]], $[[CC1]], $4
 ; 32-CMP:       or $[[CC:[0-9]+]], $[[CC3]], $[[CC2]]
 ; 32-CMP-DAG:   addiu $[[I5:[0-9]+]], $zero, 5
 ; 32-CMP-DAG:   addiu $[[I4:[0-9]+]], $zero, 4
@@ -349,8 +349,8 @@ entry:
 ; 64-CMP-DAG:  slti $[[R0:[0-9]+]], $4, 32767
 ; FIXME: We can do better than this by adding/subtracting the result of slti
 ;        to/from one of the constants.
-; 64-CMP-DAG:  selnez $[[T0:[0-9]+]], $[[I5]], $[[R0]]
-; 64-CMP-DAG:  seleqz $[[T1:[0-9]+]], $[[I4]], $[[R0]]
+; 64-CMP-DAG:  seleqz $[[T0:[0-9]+]], $[[I5]], $[[R0]]
+; 64-CMP-DAG:  selnez $[[T1:[0-9]+]], $[[I4]], $[[R0]]
 ; 64-CMP-DAG:  or $2, $[[T0]], $[[T1]]
 
 define i64 @slti64_0(i64 %a) {
@@ -374,8 +374,8 @@ entry:
 ; 32-CMP-DAG:   slt $[[CC0:[0-9]+]], $zero, $4
 ; 32-CMP-DAG:   addiu $[[I32766:[0-9]+]], $zero, 32767
 ; 32-CMP-DAG:   sltu $[[CC1:[0-9]+]], $[[I32766]], $5
-; 32-CMP-DAG:   seleqz $[[CC2:[0-9]+]], $[[CC0]], $4
-; 32-CMP-DAG:   selnez $[[CC3:[0-9]+]], $[[CC1]], $4
+; 32-CMP-DAG:   selnez $[[CC2:[0-9]+]], $[[CC0]], $4
+; 32-CMP-DAG:   seleqz $[[CC3:[0-9]+]], $[[CC1]], $4
 ; 32-CMP:       or $[[CC:[0-9]+]], $[[CC3]], $[[CC2]]
 ; 32-CMP-DAG:   addiu $[[I5:[0-9]+]], $zero, 5
 ; 32-CMP-DAG:   addiu $[[I4:[0-9]+]], $zero, 4
@@ -423,8 +423,8 @@ entry:
 ; 64-CMP-DAG:  slti $[[R0:[0-9]+]], $4, -32768
 ; FIXME: We can do better than this by adding/subtracting the result of slti
 ;        to/from one of the constants.
-; 64-CMP-DAG:  selnez $[[T0:[0-9]+]], $[[I3]], $[[R0]]
-; 64-CMP-DAG:  seleqz $[[T1:[0-9]+]], $[[I4]], $[[R0]]
+; 64-CMP-DAG:  seleqz $[[T0:[0-9]+]], $[[I3]], $[[R0]]
+; 64-CMP-DAG:  selnez $[[T1:[0-9]+]], $[[I4]], $[[R0]]
 ; 64-CMP-DAG:  or $2, $[[T0]], $[[T1]]
 
 define i64 @slti64_2(i64 %a) {
@@ -476,8 +476,8 @@ entry:
 ; 32-CMP-DAG:  addiu $[[I5:[0-9]+]], $zero, 5
 ; 32-CMP-DAG:  sltiu $[[R0:[0-9]+]], $4, 32767
 ; FIXME: We can do better than this by using selccz to choose between +0 and +2
-; 32-CMP-DAG:  selnez $[[T0:[0-9]+]], $[[I3]], $[[R0]]
-; 32-CMP-DAG:  seleqz $[[T1:[0-9]+]], $[[I5]], $[[R0]]
+; 32-CMP-DAG:  seleqz $[[T0:[0-9]+]], $[[I3]], $[[R0]]
+; 32-CMP-DAG:  selnez $[[T1:[0-9]+]], $[[I5]], $[[R0]]
 ; 32-CMP-DAG:  or $2, $[[T0]], $[[T1]]
 
 ; 64-CMOV-DAG: addiu $[[I3:[0-9]+]], $zero, 3
@@ -489,8 +489,8 @@ entry:
 ; 64-CMP-DAG:  addiu $[[I5:[0-9]+]], $zero, 5
 ; 64-CMP-DAG:  sltiu $[[R0:[0-9]+]], $4, 32767
 ; FIXME: We can do better than this by using selccz to choose between +0 and +2
-; 64-CMP-DAG:  selnez $[[T0:[0-9]+]], $[[I3]], $[[R0]]
-; 64-CMP-DAG:  seleqz $[[T1:[0-9]+]], $[[I5]], $[[R0]]
+; 64-CMP-DAG:  seleqz $[[T0:[0-9]+]], $[[I3]], $[[R0]]
+; 64-CMP-DAG:  selnez $[[T1:[0-9]+]], $[[I5]], $[[R0]]
 ; 64-CMP-DAG:  or $2, $[[T0]], $[[T1]]
 
 define i32 @sltiu0(i32 %a) {
@@ -550,8 +550,8 @@ entry:
 ; 32-CMP-DAG:  addiu $[[I5:[0-9]+]], $zero, 5
 ; 32-CMP-DAG:  sltiu $[[R0:[0-9]+]], $4, -32768
 ; FIXME: We can do better than this by using selccz to choose between +0 and +2
-; 32-CMP-DAG:  selnez $[[T0:[0-9]+]], $[[I3]], $[[R0]]
-; 32-CMP-DAG:  seleqz $[[T1:[0-9]+]], $[[I5]], $[[R0]]
+; 32-CMP-DAG:  seleqz $[[T0:[0-9]+]], $[[I3]], $[[R0]]
+; 32-CMP-DAG:  selnez $[[T1:[0-9]+]], $[[I5]], $[[R0]]
 ; 32-CMP-DAG:  or $2, $[[T0]], $[[T1]]
 
 ; 64-CMOV-DAG: addiu $[[I3:[0-9]+]], $zero, 3
@@ -563,8 +563,8 @@ entry:
 ; 64-CMP-DAG:  addiu $[[I5:[0-9]+]], $zero, 5
 ; 64-CMP-DAG:  sltiu $[[R0:[0-9]+]], $4, -32768
 ; FIXME: We can do better than this by using selccz to choose between +0 and +2
-; 64-CMP-DAG:  selnez $[[T0:[0-9]+]], $[[I3]], $[[R0]]
-; 64-CMP-DAG:  seleqz $[[T1:[0-9]+]], $[[I5]], $[[R0]]
+; 64-CMP-DAG:  seleqz $[[T0:[0-9]+]], $[[I3]], $[[R0]]
+; 64-CMP-DAG:  selnez $[[T1:[0-9]+]], $[[I5]], $[[R0]]
 ; 64-CMP-DAG:  or $2, $[[T0]], $[[T1]]
 
 define i32 @sltiu2(i32 %a) {
diff --git a/test/CodeGen/Mips/countleading.ll b/test/CodeGen/Mips/countleading.ll
index 81fb2b44942..6e63cff123c 100644
--- a/test/CodeGen/Mips/countleading.ll
+++ b/test/CodeGen/Mips/countleading.ll
@@ -52,9 +52,9 @@ entry:
 ; MIPS32-GT-R1-DAG: clz $[[R1:[0-9]+]], $5
 ; MIPS32-GT-R1-DAG: addiu $[[R2:2+]], $[[R0]], 32
 ; MIPS32-R1-R2-DAG: movn $[[R2]], $[[R1]], $5
-; MIPS32-R6-DAG:    selnez $[[R5:[0-9]+]], $[[R2]], $5
-; MIPS32-R6-DAG:    seleqz $[[R6:[0-9]+]], $[[R1]], $5
-; MIPS32-R6-DAG:    or $2, $[[R5]], $[[R6]]
+; MIPS32-R6-DAG:    seleqz $[[R5:[0-9]+]], $[[R2]], $5
+; MIPS32-R6-DAG:    selnez $[[R6:[0-9]+]], $[[R1]], $5
+; MIPS32-R6-DAG:    or $2, $[[R6]], $[[R5]]
 ; MIPS32-GT-R1-DAG: addiu $3, $zero, 0
 
 ; MIPS64-GT-R1:  dclz $2, $4
diff --git a/test/CodeGen/Mips/mips64-f128.ll b/test/CodeGen/Mips/mips64-f128.ll
index d523f253bf3..7f7d515d690 100644
--- a/test/CodeGen/Mips/mips64-f128.ll
+++ b/test/CodeGen/Mips/mips64-f128.ll
@@ -628,12 +628,12 @@ entry:
 ;        (setcc's result is i32 so bits 32-63 are undefined). It's not really
 ;        needed.
 ; CMP_CC_FMT-DAG: sll $[[CC:[0-9]+]], $4, 0
-; CMP_CC_FMT-DAG: selnez $[[EQ1:[0-9]+]], $8, $[[CC]]
-; CMP_CC_FMT-DAG: seleqz $[[NE1:[0-9]+]], $6, $[[CC]]
-; CMP_CC_FMT-DAG: or $2, $[[EQ1]], $[[NE1]]
-; CMP_CC_FMT-DAG: selnez $[[EQ2:[0-9]+]], $9, $[[CC]]
-; CMP_CC_FMT-DAG: seleqz $[[NE2:[0-9]+]], $7, $[[CC]]
-; CMP_CC_FMT-DAG: or $4, $[[EQ2]], $[[NE2]]
+; CMP_CC_FMT-DAG: seleqz $[[EQ1:[0-9]+]], $8, $[[CC]]
+; CMP_CC_FMT-DAG: selnez $[[NE1:[0-9]+]], $6, $[[CC]]
+; CMP_CC_FMT-DAG: or $2, $[[NE1]], $[[EQ1]]
+; CMP_CC_FMT-DAG: seleqz $[[EQ2:[0-9]+]], $9, $[[CC]]
+; CMP_CC_FMT-DAG: selnez $[[NE2:[0-9]+]], $7, $[[CC]]
+; CMP_CC_FMT-DAG: or $4, $[[NE2]], $[[EQ2]]
 
 define fp128 @select_LD(i32 %a, i64, fp128 %b, fp128 %c) {
 entry:
diff --git a/test/CodeGen/Mips/select.ll b/test/CodeGen/Mips/select.ll
index d4a75bc42ff..91471a2ce6b 100644
--- a/test/CodeGen/Mips/select.ll
+++ b/test/CodeGen/Mips/select.ll
@@ -18,9 +18,9 @@ entry:
 ; 32R2:          movn $5, $6, $4
 ; 32R2:          move $2, $5
 
-; 32R6-DAG:      selnez $[[T0:[0-9]+]], $5, $4
-; 32R6-DAG:      seleqz $[[T1:[0-9]+]], $6, $4
-; 32R6:          or $2, $[[T0]], $[[T1]]
+; 32R6-DAG:      seleqz $[[T0:[0-9]+]], $5, $4
+; 32R6-DAG:      selnez $[[T1:[0-9]+]], $6, $4
+; 32R6:          or $2, $[[T1]], $[[T0]]
 
 ; 64:            movn $5, $6, $4
 ; 64:            move $2, $5
@@ -28,9 +28,9 @@ entry:
 ; 64R2:          movn $5, $6, $4
 ; 64R2:          move $2, $5
 
-; 64R6-DAG:      selnez $[[T0:[0-9]+]], $5, $4
-; 64R6-DAG:      seleqz $[[T1:[0-9]+]], $6, $4
-; 64R6:          or $2, $[[T0]], $[[T1]]
+; 64R6-DAG:      seleqz $[[T0:[0-9]+]], $5, $4
+; 64R6-DAG:      selnez $[[T1:[0-9]+]], $6, $4
+; 64R6:          or $2, $[[T1]], $[[T0]]
 
   %tobool = icmp ne i32 %s, 0
   %cond = select i1 %tobool, i32 %f1, i32 %f0
@@ -56,13 +56,13 @@ entry:
 ; 32R2:          move $3, $7
 
 ; 32R6-DAG:      lw $[[F1:[0-9]+]], 16($sp)
-; 32R6-DAG:      selnez $[[T0:[0-9]+]], $6, $4
-; 32R6-DAG:      seleqz $[[T1:[0-9]+]], $[[F1]], $4
-; 32R6:          or $2, $[[T0]], $[[T1]]
+; 32R6-DAG:      seleqz $[[T0:[0-9]+]], $6, $4
+; 32R6-DAG:      selnez $[[T1:[0-9]+]], $[[F1]], $4
+; 32R6:          or $2, $[[T1]], $[[T0]]
 ; 32R6-DAG:      lw $[[F1H:[0-9]+]], 20($sp)
-; 32R6-DAG:      selnez $[[T0:[0-9]+]], $7, $4
-; 32R6-DAG:      seleqz $[[T1:[0-9]+]], $[[F1H]], $4
-; 32R6:          or $3, $[[T0]], $[[T1]]
+; 32R6-DAG:      seleqz $[[T0:[0-9]+]], $7, $4
+; 32R6-DAG:      selnez $[[T1:[0-9]+]], $[[F1H]], $4
+; 32R6:          or $3, $[[T1]], $[[T0]]
 
 ; 64:            movn $5, $6, $4
 ; 64:            move $2, $5
@@ -74,9 +74,9 @@ entry:
 ;        (setcc's result is i32 so bits 32-63 are undefined). It's not really
 ;        needed.
 ; 64R6-DAG:      sll $[[CC:[0-9]+]], $4, 0
-; 64R6-DAG:      selnez $[[T0:[0-9]+]], $5, $[[CC]]
-; 64R6-DAG:      seleqz $[[T1:[0-9]+]], $6, $[[CC]]
-; 64R6:          or $2, $[[T0]], $[[T1]]
+; 64R6-DAG:      seleqz $[[T0:[0-9]+]], $5, $[[CC]]
+; 64R6-DAG:      selnez $[[T1:[0-9]+]], $6, $[[CC]]
+; 64R6:          or $2, $[[T1]], $[[T0]]
 
   %tobool = icmp ne i32 %s, 0
   %cond = select i1 %tobool, i64 %f1, i64 %f0
@@ -105,13 +105,13 @@ entry:
 
 ; 32R6-DAG:      lw $[[F1:[0-9]+]], 16($sp)
 ; 32R6-DAG:      or $[[T2:[0-9]+]], $4, $5
-; 32R6-DAG:      selnez $[[T0:[0-9]+]], $6, $[[T2]]
-; 32R6-DAG:      seleqz $[[T1:[0-9]+]], $[[F1]], $[[T2]]
-; 32R6:          or $2, $[[T0]], $[[T1]]
+; 32R6-DAG:      seleqz $[[T0:[0-9]+]], $6, $[[T2]]
+; 32R6-DAG:      selnez $[[T1:[0-9]+]], $[[F1]], $[[T2]]
+; 32R6:          or $2, $[[T1]], $[[T0]]
 ; 32R6-DAG:      lw $[[F1H:[0-9]+]], 20($sp)
-; 32R6-DAG:      selnez $[[T0:[0-9]+]], $7, $[[T2]]
-; 32R6-DAG:      seleqz $[[T1:[0-9]+]], $[[F1H]], $[[T2]]
-; 32R6:          or $3, $[[T0]], $[[T1]]
+; 32R6-DAG:      seleqz $[[T0:[0-9]+]], $7, $[[T2]]
+; 32R6-DAG:      selnez $[[T1:[0-9]+]], $[[F1H]], $[[T2]]
+; 32R6:          or $3, $[[T1]], $[[T0]]
 
 ; 64:            movn $5, $6, $4
 ; 64:            move $2, $5
@@ -119,9 +119,9 @@ entry:
 ; 64R2:          movn $5, $6, $4
 ; 64R2:          move $2, $5
 
-; 64R6-DAG:      selnez $[[T0:[0-9]+]], $5, $4
-; 64R6-DAG:      seleqz $[[T1:[0-9]+]], $6, $4
-; 64R6:          or $2, $[[T0]], $[[T1]]
+; 64R6-DAG:      seleqz $[[T0:[0-9]+]], $5, $4
+; 64R6-DAG:      selnez $[[T1:[0-9]+]], $6, $4
+; 64R6:          or $2, $[[T1]], $[[T0]]
 
   %tobool = icmp ne i64 %s, 0
   %cond = select i1 %tobool, i64 %f1, i64 %f0