From: Tim Northover <tnorthover@apple.com>
Date: Tue, 7 Apr 2015 22:49:47 +0000 (+0000)
Subject: AArch64: disallow "fmov sD, #-0.0" during assembly.
X-Git-Url: http://plrg.eecs.uci.edu/git/?p=oota-llvm.git;a=commitdiff_plain;h=112102c7fe7be6d3f322a07e0da00284284398c6;hp=112102c7fe7be6d3f322a07e0da00284284398c6

AArch64: disallow "fmov sD, #-0.0" during assembly.

We weren't checking the sign of the floating point immediate before translating
it to "fmov sD, wzr". Similarly for D-regs.

Technically "movi vD.2s, #0x80, lsl #24" would work most of the time, but it's
not a blessed alias (and I don't think it should be since people expect writing
sD to zero out the high lanes, and there's no dD equivalent). So an error it is.

rdar://20455398

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234372 91177308-0d34-0410-b5e6-96231b3b80d8
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