From: Evan Cheng Date: Tue, 13 Feb 2007 01:30:55 +0000 (+0000) Subject: Allow any MachineBasicBlock (not just the entry block) to have live-in physical X-Git-Url: http://plrg.eecs.uci.edu/git/?p=oota-llvm.git;a=commitdiff_plain;h=0c9f92e1ff64ee56724eae444a0442b02f83d0a8 Allow any MachineBasicBlock (not just the entry block) to have live-in physical registers. Make sure liveinterval analysis is correctly creating live ranges for them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34217 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp index 68d19488375..83852ca8b9c 100644 --- a/lib/CodeGen/LiveIntervalAnalysis.cpp +++ b/lib/CodeGen/LiveIntervalAnalysis.cpp @@ -88,28 +88,6 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) { allocatableRegs_ = mri_->getAllocatableSet(fn); r2rMap_.grow(mf_->getSSARegMap()->getLastVirtReg()); - // If this function has any live ins, insert a dummy instruction at the - // beginning of the function that we will pretend "defines" the values. This - // is to make the interval analysis simpler by providing a number. - if (fn.livein_begin() != fn.livein_end()) { - unsigned FirstLiveIn = fn.livein_begin()->first; - - // Find a reg class that contains this live in. - const TargetRegisterClass *RC = 0; - for (MRegisterInfo::regclass_iterator RCI = mri_->regclass_begin(), - E = mri_->regclass_end(); RCI != E; ++RCI) - if ((*RCI)->contains(FirstLiveIn)) { - RC = *RCI; - break; - } - - MachineInstr *OldFirstMI = fn.begin()->begin(); - mri_->copyRegToReg(*fn.begin(), fn.begin()->begin(), - FirstLiveIn, FirstLiveIn, RC); - assert(OldFirstMI != fn.begin()->begin() && - "copyRetToReg didn't insert anything!"); - } - // Number MachineInstrs and MachineBasicBlocks. // Initialize MBB indexes to a sentinal. MBB2IdxMap.resize(mf_->getNumBlockIDs(), ~0U); @@ -119,6 +97,28 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) { MBB != E; ++MBB) { // Set the MBB2IdxMap entry for this MBB. MBB2IdxMap[MBB->getNumber()] = MIIndex; + + // If this BB has any live ins, insert a dummy instruction at the + // beginning of the function that we will pretend "defines" the values. This + // is to make the interval analysis simpler by providing a number. + if (MBB->livein_begin() != MBB->livein_end()) { + unsigned FirstLiveIn = *MBB->livein_begin(); + + // Find a reg class that contains this live in. + const TargetRegisterClass *RC = 0; + for (MRegisterInfo::regclass_iterator RCI = mri_->regclass_begin(), + RCE = mri_->regclass_end(); RCI != RCE; ++RCI) + if ((*RCI)->contains(FirstLiveIn)) { + RC = *RCI; + break; + } + + MachineInstr *OldFirstMI = MBB->begin(); + mri_->copyRegToReg(*MBB, MBB->begin(), + FirstLiveIn, FirstLiveIn, RC); + assert(OldFirstMI != MBB->begin() && + "copyRetToReg didn't insert anything!"); + } for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E; ++I) { @@ -129,19 +129,6 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) { } } - // Note intervals due to live-in values. - if (fn.livein_begin() != fn.livein_end()) { - MachineBasicBlock *Entry = fn.begin(); - for (MachineFunction::livein_iterator I = fn.livein_begin(), - E = fn.livein_end(); I != E; ++I) { - handlePhysicalRegisterDef(Entry, Entry->begin(), 0, - getOrCreateInterval(I->first), 0); - for (const unsigned* AS = mri_->getAliasSet(I->first); *AS; ++AS) - handlePhysicalRegisterDef(Entry, Entry->begin(), 0, - getOrCreateInterval(*AS), 0); - } - } - computeIntervals(); numIntervals += getNumIntervals(); @@ -691,8 +678,6 @@ void LiveIntervals::computeIntervals() { DOUT << "********** COMPUTING LIVE INTERVALS **********\n" << "********** Function: " << ((Value*)mf_->getFunction())->getName() << '\n'; - bool IgnoreFirstInstr = mf_->livein_begin() != mf_->livein_end(); - // Track the index of the current machine instr. unsigned MIIndex = 0; for (MachineFunction::iterator MBBI = mf_->begin(), E = mf_->end(); @@ -701,9 +686,18 @@ void LiveIntervals::computeIntervals() { DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n"; MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end(); - if (IgnoreFirstInstr) { + + if (MBB->livein_begin() != MBB->livein_end()) { + // Process live-ins to this BB first. + for (MachineBasicBlock::livein_iterator LI = MBB->livein_begin(), + LE = MBB->livein_end(); LI != LE; ++LI) { + handlePhysicalRegisterDef(MBB, MBB->begin(), MIIndex, + getOrCreateInterval(*LI), 0); + for (const unsigned* AS = mri_->getAliasSet(*LI); *AS; ++AS) + handlePhysicalRegisterDef(MBB, MBB->begin(), MIIndex, + getOrCreateInterval(*AS), 0); + } ++MI; - IgnoreFirstInstr = false; MIIndex += InstrSlots::NUM; } diff --git a/lib/CodeGen/LiveVariables.cpp b/lib/CodeGen/LiveVariables.cpp index e0713c87c99..c0da92c658c 100644 --- a/lib/CodeGen/LiveVariables.cpp +++ b/lib/CodeGen/LiveVariables.cpp @@ -254,14 +254,6 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &MF) { /// Get some space for a respectable number of registers... VirtRegInfo.resize(64); - // Mark live-in registers as live-in. - for (MachineFunction::livein_iterator I = MF.livein_begin(), - E = MF.livein_end(); I != E; ++I) { - assert(MRegisterInfo::isPhysicalRegister(I->first) && - "Cannot have a live-in virtual register!"); - HandlePhysRegDef(I->first, 0); - } - analyzePHINodes(MF); // Calculate live variable information in depth first order on the CFG of the @@ -275,6 +267,14 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &MF) { E = df_ext_end(Entry, Visited); DFI != E; ++DFI) { MachineBasicBlock *MBB = *DFI; + // Mark live-in registers as live-in. + for (MachineBasicBlock::livein_iterator II = MBB->livein_begin(), + EE = MBB->livein_end(); II != EE; ++II) { + assert(MRegisterInfo::isPhysicalRegister(*II) && + "Cannot have a live-in virtual register!"); + HandlePhysRegDef(*II, 0); + } + // Loop over all of the instructions, processing them. for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E; ++I) {