#include <iterator>
#include <memory>
#include <utility> // for std::pair
+#include <cassert>
namespace llvm {
}
};
+/// A functor like C++14's std::less<void> in its absence.
+struct less {
+ template <typename A, typename B> bool operator()(A &&a, B &&b) const {
+ return std::forward<A>(a) < std::forward<B>(b);
+ }
+};
+
+/// A functor like C++14's std::equal<void> in its absence.
+struct equal {
+ template <typename A, typename B> bool operator()(A &&a, B &&b) const {
+ return std::forward<A>(a) == std::forward<B>(b);
+ }
+};
+
+/// Binary functor that adapts to any other binary functor after dereferencing
+/// operands.
+template <typename T> struct deref {
+ T func;
+ // Could be further improved to cope with non-derivable functors and
+ // non-binary functors (should be a variadic template member function
+ // operator()).
+ template <typename A, typename B>
+ auto operator()(A &lhs, B &rhs) const -> decltype(func(*lhs, *rhs)) {
+ assert(lhs);
+ assert(rhs);
+ return func(*lhs, *rhs);
+ }
+};
+
} // End llvm namespace
#endif
//===----------------------------------------------------------------------===//
static void sortAndUniqueRegisters(CodeGenRegister::Vec &M) {
- std::sort(M.begin(), M.end(), CodeGenRegister::Less());
- M.erase(std::unique(M.begin(), M.end(), CodeGenRegister::Equal()), M.end());
+ std::sort(M.begin(), M.end(), deref<llvm::less>());
+ M.erase(std::unique(M.begin(), M.end(), deref<llvm::equal>()), M.end());
}
CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
bool CodeGenRegisterClass::contains(const CodeGenRegister *Reg) const {
return std::binary_search(Members.begin(), Members.end(), Reg,
- CodeGenRegister::Less());
+ deref<llvm::less>());
}
namespace llvm {
static bool testSubClass(const CodeGenRegisterClass *A,
const CodeGenRegisterClass *B) {
return A->SpillAlignment && B->SpillAlignment % A->SpillAlignment == 0 &&
- A->SpillSize <= B->SpillSize &&
- std::includes(A->getMembers().begin(), A->getMembers().end(),
- B->getMembers().begin(), B->getMembers().end(),
- CodeGenRegister::Less());
+ A->SpillSize <= B->SpillSize &&
+ std::includes(A->getMembers().begin(), A->getMembers().end(),
+ B->getMembers().begin(), B->getMembers().end(),
+ deref<llvm::less>());
}
/// Sorting predicate for register classes. This provides a topological
const CodeGenRegister::Vec &Memb1 = RC1->getMembers();
const CodeGenRegister::Vec &Memb2 = RC2->getMembers();
CodeGenRegister::Vec Intersection;
- std::set_intersection(Memb1.begin(), Memb1.end(),
- Memb2.begin(), Memb2.end(),
- std::inserter(Intersection, Intersection.begin()),
- CodeGenRegister::Less());
+ std::set_intersection(
+ Memb1.begin(), Memb1.end(), Memb2.begin(), Memb2.end(),
+ std::inserter(Intersection, Intersection.begin()), deref<llvm::less>());
// Skip disjoint class pairs.
if (Intersection.empty())
void CodeGenRegBank::inferSubClassWithSubReg(CodeGenRegisterClass *RC) {
// Map SubRegIndex to set of registers in RC supporting that SubRegIndex.
typedef std::map<const CodeGenSubRegIndex *, CodeGenRegister::Vec,
- CodeGenSubRegIndex::Less> SubReg2SetMap;
+ deref<llvm::less>> SubReg2SetMap;
// Compute the set of registers supporting each SubRegIndex.
SubReg2SetMap SRSets;
const std::string &getNamespace() const { return Namespace; }
std::string getQualifiedName() const;
- // Order CodeGenSubRegIndex pointers by EnumValue.
- struct Less {
- bool operator()(const CodeGenSubRegIndex *A,
- const CodeGenSubRegIndex *B) const {
- assert(A && B);
- return A->EnumValue < B->EnumValue;
- }
- };
-
// Map of composite subreg indices.
- typedef std::map<CodeGenSubRegIndex*, CodeGenSubRegIndex*, Less> CompMap;
+ typedef std::map<CodeGenSubRegIndex *, CodeGenSubRegIndex *,
+ deref<llvm::less>> CompMap;
// Returns the subreg index that results from composing this with Idx.
// Returns NULL if this and Idx don't compose.
CompMap Composed;
};
+ inline bool operator<(const CodeGenSubRegIndex &A,
+ const CodeGenSubRegIndex &B) {
+ return A.EnumValue < B.EnumValue;
+ }
+
/// CodeGenRegister - Represents a register definition.
struct CodeGenRegister {
Record *TheDef;
bool CoveredBySubRegs;
// Map SubRegIndex -> Register.
- typedef std::map<CodeGenSubRegIndex*, CodeGenRegister*,
- CodeGenSubRegIndex::Less> SubRegMap;
+ typedef std::map<CodeGenSubRegIndex *, CodeGenRegister *, deref<llvm::less>>
+ SubRegMap;
CodeGenRegister(Record *R, unsigned Enum);
// Get the sum of this register's register unit weights.
unsigned getWeight(const CodeGenRegBank &RegBank) const;
- // Order CodeGenRegister pointers by EnumValue.
- struct Less {
- bool operator()(const CodeGenRegister *A,
- const CodeGenRegister *B) const {
- assert(A && B);
- return A->EnumValue < B->EnumValue;
- }
- };
-
- struct Equal {
- bool operator()(const CodeGenRegister *A,
- const CodeGenRegister *B) const {
- assert(A && B);
- return A->EnumValue == B->EnumValue;
- }
- };
-
// Canonically ordered set.
typedef std::vector<const CodeGenRegister*> Vec;
RegUnitLaneMaskList RegUnitLaneMasks;
};
+ inline bool operator<(const CodeGenRegister &A, const CodeGenRegister &B) {
+ return A.EnumValue < B.EnumValue;
+ }
+
+ inline bool operator==(const CodeGenRegister &A, const CodeGenRegister &B) {
+ return A.EnumValue == B.EnumValue;
+ }
class CodeGenRegisterClass {
CodeGenRegister::Vec Members;
// Keep track of sub-register names as well. These are not differentially
// encoded.
typedef SmallVector<const CodeGenSubRegIndex*, 4> SubRegIdxVec;
- SequenceToOffsetTable<SubRegIdxVec, CodeGenSubRegIndex::Less> SubRegIdxSeqs;
+ SequenceToOffsetTable<SubRegIdxVec, deref<llvm::less>> SubRegIdxSeqs;
SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size());
SequenceToOffsetTable<std::string> RegStrings;
// Compress the sub-reg index lists.
typedef std::vector<const CodeGenSubRegIndex*> IdxList;
SmallVector<IdxList, 8> SuperRegIdxLists(RegisterClasses.size());
- SequenceToOffsetTable<IdxList, CodeGenSubRegIndex::Less> SuperRegIdxSeqs;
+ SequenceToOffsetTable<IdxList, deref<llvm::less>> SuperRegIdxSeqs;
BitVector MaskBV(RegisterClasses.size());
for (const auto &RC : RegisterClasses) {