[TableGen] Correct Namespace lookup with AltNames in AsmWriterEmitter

AsmWriterEmitter will generate a getRegisterName function with an alternate
register name index as its second argument if the target makes use of them. The
enum of these values is generated in RegisterInfoEmitter. The getRegisterName
generator would assume the namespace could always be found by reading index 1
of the list of AltNameIndices, but this will fail if this list is sorted such
that the NoRegAltName is at index 1. Because this list is sorted by record name
(in CodeGenTarget::ReadRegAltNameIndices), you only run in to problems if your
MyTargetRegisterInfo.td defines a single RegAltNameIndex that sorts lexically
before NoRegAltName.

For example, if a target has something like

  def AnAltNameIndex : RegAltNameIndex

and defines RegAltNameIndices for some registers then, prior to this change,
AsmWriterEmitter would generate references to

  ::AnAltNameIndex and ::NoRegAltName

Patch by Alex Bradbury!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255344 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/utils/TableGen/AsmWriterEmitter.cpp b/utils/TableGen/AsmWriterEmitter.cpp
index a954998d36e97106c39cacbc1ff2dbf22a61c02e..cc74f9ebceced78dc3c901482325b7b5a53dddb9 100644 (file)
--- a/utils/TableGen/AsmWriterEmitter.cpp
+++ b/utils/TableGen/AsmWriterEmitter.cpp
@@ -586,6 +586,8 @@ void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) {
   const auto &Registers = Target.getRegBank().getRegisters();
   std::vector<Record*> AltNameIndices = Target.getRegAltNameIndices();
   bool hasAltNames = AltNameIndices.size() > 1;
   const auto &Registers = Target.getRegBank().getRegisters();
   std::vector<Record*> AltNameIndices = Target.getRegAltNameIndices();
   bool hasAltNames = AltNameIndices.size() > 1;

+  std::string Namespace =
+      Registers.front().TheDef->getValueAsString("Namespace");

 
   O <<
   "\n\n/// getRegisterName - This method is automatically generated by tblgen\n"
 
   O <<
   "\n\n/// getRegisterName - This method is automatically generated by tblgen\n"


@@ -610,9 +612,9 @@ void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) {
     O << "  switch(AltIdx) {\n"
       << "  default: llvm_unreachable(\"Invalid register alt name index!\");\n";
     for (unsigned i = 0, e = AltNameIndices.size(); i < e; ++i) {
     O << "  switch(AltIdx) {\n"
       << "  default: llvm_unreachable(\"Invalid register alt name index!\");\n";
     for (unsigned i = 0, e = AltNameIndices.size(); i < e; ++i) {

-      std::string Namespace = AltNameIndices[1]->getValueAsString("Namespace");

       std::string AltName(AltNameIndices[i]->getName());
       std::string AltName(AltNameIndices[i]->getName());

-      O << "  case " << Namespace << "::" << AltName << ":\n"
+      std::string Prefix = !Namespace.empty() ? Namespace + "::" : "";
+      O << "  case " << Prefix << AltName << ":\n"

         << "    assert(*(AsmStrs" << AltName << "+RegAsmOffset"
         << AltName << "[RegNo-1]) &&\n"
         << "           \"Invalid alt name index for register!\");\n"
         << "    assert(*(AsmStrs" << AltName << "+RegAsmOffset"
         << AltName << "[RegNo-1]) &&\n"
         << "           \"Invalid alt name index for register!\");\n"