let AddedComplexity = 20 in {
def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
(VMOVDI2PDIZrm addr:$src)>;
+ def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
+ (VMOV64toPQIZrr GR64:$src)>;
+ def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
+ (VMOVDI2PDIZrr GR32:$src)>;
def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
(VMOVDI2PDIZrm addr:$src)>;
def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
(VMOVZPQILo2PQIZrr VR128X:$src)>;
}
+
// Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
(v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
%res = insertelement <2 x double>zeroinitializer, double %y, i32 0
ret <2 x double>%res
}
+
+; CHECK-LABEL: @test13
+; CHECK: vmovqz %rdi
+; CHECK: ret
+define <2 x i64> @test13(i64 %x) {
+ %res = insertelement <2 x i64>zeroinitializer, i64 %x, i32 0
+ ret <2 x i64>%res
+}
+
+; CHECK-LABEL: @test14
+; CHECK: vmovdz %edi
+; CHECK: ret
+define <4 x i32> @test14(i32 %x) {
+ %res = insertelement <4 x i32>zeroinitializer, i32 %x, i32 0
+ ret <4 x i32>%res
+}