// ----------------------------------------------------------------
// FPClass
+//handle fpclass instruction mask = op(reg_scalar,imm)
+// op(mem_scalar,imm)
+multiclass avx512_scalar_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
+ X86VectorVTInfo _, Predicate prd> {
+ let Predicates = [prd] in {
+ def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),//_.KRC:$dst),
+ (ins _.RC:$src1, i32u8imm:$src2),
+ OpcodeStr##_.Suffix#"\t{$src2, $src1, $dst | $dst, $src1, $src2}",
+ [(set _.KRC:$dst,(OpNode (_.VT _.RC:$src1),
+ (i32 imm:$src2)))], NoItinerary>;
+ def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
+ (ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
+ OpcodeStr##_.Suffix#
+ "\t{$src2, $src1, $dst {${mask}} | $dst {${mask}}, $src1, $src2}",
+ [(set _.KRC:$dst,(or _.KRCWM:$mask,
+ (OpNode (_.VT _.RC:$src1),
+ (i32 imm:$src2))))], NoItinerary>, EVEX_K;
+ let mayLoad = 1, AddedComplexity = 20 in {
+ def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
+ (ins _.MemOp:$src1, i32u8imm:$src2),
+ OpcodeStr##_.Suffix##
+ "\t{$src2, $src1, $dst | $dst, $src1, $src2}",
+ [(set _.KRC:$dst,
+ (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
+ (i32 imm:$src2)))], NoItinerary>;
+ def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
+ (ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
+ OpcodeStr##_.Suffix##
+ "\t{$src2, $src1, $dst {${mask}} | $dst {${mask}}, $src1, $src2}",
+ [(set _.KRC:$dst,(or _.KRCWM:$mask,
+ (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
+ (i32 imm:$src2))))], NoItinerary>, EVEX_K;
+ }
+ }
+}
+
//handle fpclass instruction mask = fpclass(reg_vec, reg_vec, imm)
// fpclass(reg_vec, mem_vec, imm)
// fpclass(reg_vec, broadcast(eltVt), imm)
}
multiclass avx512_fp_fpclass_all<string OpcodeStr, bits<8> opcVec,
- SDNode OpNode, Predicate prd>{
+ bits<8> opcScalar, SDNode VecOpNode, SDNode ScalarOpNode, Predicate prd>{
defm PS : avx512_vector_fpclass_all<OpcodeStr, avx512vl_f32_info, opcVec,
- OpNode, prd, "{l}">, EVEX_CD8<32, CD8VF>;
+ VecOpNode, prd, "{l}">, EVEX_CD8<32, CD8VF>;
defm PD : avx512_vector_fpclass_all<OpcodeStr, avx512vl_f64_info, opcVec,
- OpNode, prd, "{q}">,EVEX_CD8<64, CD8VF> , VEX_W;
+ VecOpNode, prd, "{q}">,EVEX_CD8<64, CD8VF> , VEX_W;
+ defm SS : avx512_scalar_fpclass<opcScalar, OpcodeStr, ScalarOpNode,
+ f32x_info, prd>, EVEX_CD8<32, CD8VT1>;
+ defm SD : avx512_scalar_fpclass<opcScalar, OpcodeStr, ScalarOpNode,
+ f64x_info, prd>, EVEX_CD8<64, CD8VT1>, VEX_W;
}
-defm VFPCLASS : avx512_fp_fpclass_all<"vfpclass", 0x66, X86Vfpclass, HasDQI>,
- AVX512AIi8Base,EVEX;
+defm VFPCLASS : avx512_fp_fpclass_all<"vfpclass", 0x66, 0x67, X86Vfpclass,
+ X86Vfpclasss, HasDQI>, AVX512AIi8Base,EVEX;
//-----------------------------------------------------------------
// Mask register copy, including
// CHECK: vcvtuqq2ps -1032(%rdx){1to8}, %ymm25
// CHECK: encoding: [0x62,0x61,0xff,0x58,0x7a,0x8a,0xf8,0xfb,0xff,0xff]
vcvtuqq2ps -1032(%rdx){1to8}, %ymm25
+
+// CHECK: vfpclasssd $171, %xmm28, %k4
+// CHECK: encoding: [0x62,0x93,0xfd,0x08,0x67,0xe4,0xab]
+ vfpclasssd $0xab, %xmm28, %k4
+
+// CHECK: vfpclasssd $171, %xmm28, %k4 {%k3}
+// CHECK: encoding: [0x62,0x93,0xfd,0x0b,0x67,0xe4,0xab]
+ vfpclasssd $0xab, %xmm28, %k4 {%k3}
+
+// CHECK: vfpclasssd $123, %xmm28, %k4
+// CHECK: encoding: [0x62,0x93,0xfd,0x08,0x67,0xe4,0x7b]
+ vfpclasssd $0x7b, %xmm28, %k4
+
+// CHECK: vfpclasssd $123, (%rcx), %k4
+// CHECK: encoding: [0x62,0xf3,0xfd,0x08,0x67,0x21,0x7b]
+ vfpclasssd $0x7b,(%rcx), %k4
+
+// CHECK: vfpclasssd $123, 291(%rax,%r14,8), %k4
+// CHECK: encoding: [0x62,0xb3,0xfd,0x08,0x67,0xa4,0xf0,0x23,0x01,0x00,0x00,0x7b]
+ vfpclasssd $0x7b,291(%rax,%r14,8), %k4
+
+// CHECK: vfpclasssd $123, 1016(%rdx), %k4
+// CHECK: encoding: [0x62,0xf3,0xfd,0x08,0x67,0x62,0x7f,0x7b]
+ vfpclasssd $0x7b,1016(%rdx), %k4
+
+// CHECK: vfpclasssd $123, 1024(%rdx), %k4
+// CHECK: encoding: [0x62,0xf3,0xfd,0x08,0x67,0xa2,0x00,0x04,0x00,0x00,0x7b]
+ vfpclasssd $0x7b,1024(%rdx), %k4
+
+// CHECK: vfpclasssd $123, -1024(%rdx), %k4
+// CHECK: encoding: [0x62,0xf3,0xfd,0x08,0x67,0x62,0x80,0x7b]
+ vfpclasssd $0x7b,-1024(%rdx), %k4
+
+// CHECK: vfpclasssd $123, -1032(%rdx), %k4
+// CHECK: encoding: [0x62,0xf3,0xfd,0x08,0x67,0xa2,0xf8,0xfb,0xff,0xff,0x7b]
+ vfpclasssd $0x7b,-1032(%rdx), %k4
+
+// CHECK: vfpclassss $171, %xmm26, %k5
+// CHECK: encoding: [0x62,0x93,0x7d,0x08,0x67,0xea,0xab]
+ vfpclassss $0xab, %xmm26, %k5
+
+// CHECK: vfpclassss $171, %xmm26, %k5 {%k4}
+// CHECK: encoding: [0x62,0x93,0x7d,0x0c,0x67,0xea,0xab]
+ vfpclassss $0xab, %xmm26, %k5 {%k4}
+
+// CHECK: vfpclassss $123, %xmm26, %k5
+// CHECK: encoding: [0x62,0x93,0x7d,0x08,0x67,0xea,0x7b]
+ vfpclassss $0x7b, %xmm26, %k5
+
+// CHECK: vfpclassss $123, (%rcx), %k5
+// CHECK: encoding: [0x62,0xf3,0x7d,0x08,0x67,0x29,0x7b]
+ vfpclassss $0x7b,(%rcx), %k5
+
+// CHECK: vfpclassss $123, 291(%rax,%r14,8), %k5
+// CHECK: encoding: [0x62,0xb3,0x7d,0x08,0x67,0xac,0xf0,0x23,0x01,0x00,0x00,0x7b]
+ vfpclassss $0x7b,291(%rax,%r14,8), %k5
+
+// CHECK: vfpclassss $123, 508(%rdx), %k5
+// CHECK: encoding: [0x62,0xf3,0x7d,0x08,0x67,0x6a,0x7f,0x7b]
+ vfpclassss $0x7b,508(%rdx), %k5
+
+// CHECK: vfpclassss $123, 512(%rdx), %k5
+// CHECK: encoding: [0x62,0xf3,0x7d,0x08,0x67,0xaa,0x00,0x02,0x00,0x00,0x7b]
+ vfpclassss $0x7b,512(%rdx), %k5
+
+// CHECK: vfpclassss $123, -512(%rdx), %k5
+// CHECK: encoding: [0x62,0xf3,0x7d,0x08,0x67,0x6a,0x80,0x7b]
+ vfpclassss $0x7b,-512(%rdx), %k5
+
+// CHECK: vfpclassss $123, -516(%rdx), %k5
+// CHECK: encoding: [0x62,0xf3,0x7d,0x08,0x67,0xaa,0xfc,0xfd,0xff,0xff,0x7b]
+ vfpclassss $0x7b,-516(%rdx), %k5
+
+// CHECK: vfpclasssd $171, %xmm20, %k3
+// CHECK: encoding: [0x62,0xb3,0xfd,0x08,0x67,0xdc,0xab]
+ vfpclasssd $0xab, %xmm20, %k3
+
+// CHECK: vfpclasssd $171, %xmm20, %k3 {%k6}
+// CHECK: encoding: [0x62,0xb3,0xfd,0x0e,0x67,0xdc,0xab]
+ vfpclasssd $0xab, %xmm20, %k3 {%k6}
+
+// CHECK: vfpclasssd $123, %xmm20, %k3
+// CHECK: encoding: [0x62,0xb3,0xfd,0x08,0x67,0xdc,0x7b]
+ vfpclasssd $0x7b, %xmm20, %k3
+
+// CHECK: vfpclasssd $123, (%rcx), %k3
+// CHECK: encoding: [0x62,0xf3,0xfd,0x08,0x67,0x19,0x7b]
+ vfpclasssd $0x7b,(%rcx), %k3
+
+// CHECK: vfpclasssd $123, 4660(%rax,%r14,8), %k3
+// CHECK: encoding: [0x62,0xb3,0xfd,0x08,0x67,0x9c,0xf0,0x34,0x12,0x00,0x00,0x7b]
+ vfpclasssd $0x7b,4660(%rax,%r14,8), %k3
+
+// CHECK: vfpclasssd $123, 1016(%rdx), %k3
+// CHECK: encoding: [0x62,0xf3,0xfd,0x08,0x67,0x5a,0x7f,0x7b]
+ vfpclasssd $0x7b,1016(%rdx), %k3
+
+// CHECK: vfpclasssd $123, 1024(%rdx), %k3
+// CHECK: encoding: [0x62,0xf3,0xfd,0x08,0x67,0x9a,0x00,0x04,0x00,0x00,0x7b]
+ vfpclasssd $0x7b,1024(%rdx), %k3
+
+// CHECK: vfpclasssd $123, -1024(%rdx), %k3
+// CHECK: encoding: [0x62,0xf3,0xfd,0x08,0x67,0x5a,0x80,0x7b]
+ vfpclasssd $0x7b,-1024(%rdx), %k3
+
+// CHECK: vfpclasssd $123, -1032(%rdx), %k3
+// CHECK: encoding: [0x62,0xf3,0xfd,0x08,0x67,0x9a,0xf8,0xfb,0xff,0xff,0x7b]
+ vfpclasssd $0x7b,-1032(%rdx), %k3
+
+// CHECK: vfpclassss $171, %xmm28, %k4
+// CHECK: encoding: [0x62,0x93,0x7d,0x08,0x67,0xe4,0xab]
+ vfpclassss $0xab, %xmm28, %k4
+
+// CHECK: vfpclassss $171, %xmm28, %k4 {%k6}
+// CHECK: encoding: [0x62,0x93,0x7d,0x0e,0x67,0xe4,0xab]
+ vfpclassss $0xab, %xmm28, %k4 {%k6}
+
+// CHECK: vfpclassss $123, %xmm28, %k4
+// CHECK: encoding: [0x62,0x93,0x7d,0x08,0x67,0xe4,0x7b]
+ vfpclassss $0x7b, %xmm28, %k4
+
+// CHECK: vfpclassss $123, (%rcx), %k4
+// CHECK: encoding: [0x62,0xf3,0x7d,0x08,0x67,0x21,0x7b]
+ vfpclassss $0x7b,(%rcx), %k4
+
+// CHECK: vfpclassss $123, 4660(%rax,%r14,8), %k4
+// CHECK: encoding: [0x62,0xb3,0x7d,0x08,0x67,0xa4,0xf0,0x34,0x12,0x00,0x00,0x7b]
+ vfpclassss $0x7b,4660(%rax,%r14,8), %k4
+
+// CHECK: vfpclassss $123, 508(%rdx), %k4
+// CHECK: encoding: [0x62,0xf3,0x7d,0x08,0x67,0x62,0x7f,0x7b]
+ vfpclassss $0x7b,508(%rdx), %k4
+
+// CHECK: vfpclassss $123, 512(%rdx), %k4
+// CHECK: encoding: [0x62,0xf3,0x7d,0x08,0x67,0xa2,0x00,0x02,0x00,0x00,0x7b]
+ vfpclassss $0x7b,512(%rdx), %k4
+
+// CHECK: vfpclassss $123, -512(%rdx), %k4
+// CHECK: encoding: [0x62,0xf3,0x7d,0x08,0x67,0x62,0x80,0x7b]
+ vfpclassss $0x7b,-512(%rdx), %k4
+
+// CHECK: vfpclassss $123, -516(%rdx), %k4
+// CHECK: encoding: [0x62,0xf3,0x7d,0x08,0x67,0xa2,0xfc,0xfd,0xff,0xff,0x7b]
+ vfpclassss $0x7b,-516(%rdx), %k4