case scCouldNotCompute:
return ((SC*)this)->visitCouldNotCompute((const SCEVCouldNotCompute*)S);
default:
- LLVM_UNREACHABLE("Unknown SCEV type!");
+ llvm_unreachable("Unknown SCEV type!");
}
}
RetVal visitCouldNotCompute(const SCEVCouldNotCompute *S) {
- LLVM_UNREACHABLE("Invalid use of SCEVCouldNotCompute!");
+ llvm_unreachable("Invalid use of SCEVCouldNotCompute!");
return RetVal();
}
};
virtual void destroyConstant();
virtual void replaceUsesOfWithOnConstant(Value *From, Value *To, Use *U) {
- LLVM_UNREACHABLE("This should never be called because MDNodes have no ops");
+ llvm_unreachable("This should never be called because MDNodes have no ops");
}
/// Methods for support type inquiry through isa, cast, and dyn_cast:
void llvm_report_error(const std::string &reason) NORETURN;
/// This function calls abort(), and prints the optional message to stderr.
- /// Call this instead of assert(0), so that compiler knows the path is not
- /// reachable even for NDEBUG builds.
- /// Use the LLVM_UNREACHABLE macro instead that adds location info.
- void llvm_unreachable(const char *msg=0, const char *file=0,
- unsigned line=0) NORETURN;
+ /// Use the llvm_unreachable macro (that adds location info), instead of
+ /// calling this function directly.
+ void llvm_unreachable_internal(const char *msg=0, const char *file=0,
+ unsigned line=0) NORETURN;
}
-/// Macro that calls llvm_unreachable with location info and message in
-/// debug mode. In NDEBUG mode it calls llvm_unreachable with no message.
+/// Prints the message and location info to stderr in !NDEBUG builds.
+/// In NDEBUG mode it only prints "UNREACHABLE executed".
+/// Use this instead of assert(0), so that the compiler knows this path
+/// is not reachable even for NDEBUG builds.
#ifndef NDEBUG
-#define LLVM_UNREACHABLE(msg) llvm_unreachable(msg, __FILE__, __LINE__)
+#define llvm_unreachable(msg) llvm_unreachable_internal(msg, __FILE__, __LINE__)
#else
-#define LLVM_UNREACHABLE(msg) llvm_unreachable()
+#define llvm_unreachable(msg) llvm_unreachable_internal()
#endif
#endif
//
RetTy visit(Instruction &I) {
switch (I.getOpcode()) {
- default: LLVM_UNREACHABLE("Unknown instruction type encountered!");
+ default: llvm_unreachable("Unknown instruction type encountered!");
// Build the switch statement using the Instruction.def file...
#define HANDLE_INST(NUM, OPCODE, CLASS) \
case Instruction::OPCODE: return \
if (findOption(P->getPassArgument()) != getNumOptions()) {
cerr << "Two passes with the same argument (-"
<< P->getPassArgument() << ") attempted to be registered!\n";
- LLVM_UNREACHABLE(0);
+ llvm_unreachable(0);
}
addLiteralOption(P->getPassArgument(), P, P->getPassName());
}
/// point.
virtual void insertNoop(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const {
- LLVM_UNREACHABLE("Target didn't implement insertNoop!");
+ llvm_unreachable("Target didn't implement insertNoop!");
}
/// isPredicated - Returns true if the instruction is already predicated.
const char *AliasString;
switch (R) {
- default: LLVM_UNREACHABLE("Unknown alias type!");
+ default: llvm_unreachable("Unknown alias type!");
case NoAlias: No++; AliasString = "No alias"; break;
case MayAlias: May++; AliasString = "May alias"; break;
case MustAlias: Must++; AliasString = "Must alias"; break;
const char *MRString;
switch (R) {
- default: LLVM_UNREACHABLE("Unknown mod/ref type!");
+ default: llvm_unreachable("Unknown mod/ref type!");
case NoModRef: NoMR++; MRString = "NoModRef"; break;
case Ref: JustRef++; MRString = "JustRef"; break;
case Mod: JustMod++; MRString = "JustMod"; break;
case Refs : OS << "Ref "; break;
case Mods : OS << "Mod "; break;
case ModRef : OS << "Mod/Ref "; break;
- default: LLVM_UNREACHABLE("Bad value for AccessTy!");
+ default: llvm_unreachable("Bad value for AccessTy!");
}
if (isVolatile()) OS << "[volatile] ";
if (Forward)
virtual void getArgumentAccesses(Function *F, CallSite CS,
std::vector<PointerAccessInfo> &Info) {
- LLVM_UNREACHABLE("This method may not be called on this function!");
+ llvm_unreachable("This method may not be called on this function!");
}
virtual void getMustAliases(Value *P, std::vector<Value*> &RetVals) { }
return 0;
case Instruction::ICmp:
case Instruction::FCmp:
- LLVM_UNREACHABLE("This function is invalid for compares: no predicate specified");
+ llvm_unreachable("This function is invalid for compares: no predicate specified");
case Instruction::PtrToInt:
// If the input is a inttoptr, eliminate the pair. This requires knowing
// the width of a pointer, so it can't be done in ConstantExpr::getCast.
return Context->getConstantFP(APFloat((float)V));
if (Ty == Type::DoubleTy)
return Context->getConstantFP(APFloat(V));
- LLVM_UNREACHABLE("Can only constant fold float/double");
+ llvm_unreachable("Can only constant fold float/double");
return 0; // dummy return to suppress warning
}
return Context->getConstantFP(APFloat((float)V));
if (Ty == Type::DoubleTy)
return Context->getConstantFP(APFloat(V));
- LLVM_UNREACHABLE("Can only constant fold float/double");
+ llvm_unreachable("Can only constant fold float/double");
return 0; // dummy return to suppress warning
}
#ifndef NDEBUG
V->dump();
#endif
- LLVM_UNREACHABLE("Value does not have a node in the points-to graph!");
+ llvm_unreachable("Value does not have a node in the points-to graph!");
}
return I->second;
}
return getNodeForConstantPointer(CE->getOperand(0));
default:
cerr << "Constant Expr not yet handled: " << *CE << "\n";
- llvm_unreachable();
+ llvm_unreachable(0);
}
} else {
- LLVM_UNREACHABLE("Unknown constant pointer!");
+ llvm_unreachable("Unknown constant pointer!");
}
return 0;
}
return getNodeForConstantPointerTarget(CE->getOperand(0));
default:
cerr << "Constant Expr not yet handled: " << *CE << "\n";
- llvm_unreachable();
+ llvm_unreachable(0);
}
} else {
- LLVM_UNREACHABLE("Unknown constant pointer!");
+ llvm_unreachable("Unknown constant pointer!");
}
return 0;
}
default:
// Is this something we aren't handling yet?
cerr << "Unknown instruction: " << I;
- llvm_unreachable();
+ llvm_unreachable(0);
}
}
}
void Andersens::visitVAArg(VAArgInst &I) {
- LLVM_UNREACHABLE("vaarg not handled yet!");
+ llvm_unreachable("vaarg not handled yet!");
}
/// AddConstraintsForCall - Add constraints for a call with actual arguments
void visitInstruction(Instruction &I) {
cerr << "Instruction Count does not know about " << I;
- llvm_unreachable();
+ llvm_unreachable(0);
}
public:
static char ID; // Pass identification, replacement for typeid
return i->getPointerOperand();
if (StoreInst *i = dyn_cast<StoreInst>(I))
return i->getPointerOperand();
- LLVM_UNREACHABLE("Value is no load or store instruction!");
+ llvm_unreachable("Value is no load or store instruction!");
// Never reached.
return 0;
}
SCEV(FoldingSetNodeID(), scCouldNotCompute) {}
bool SCEVCouldNotCompute::isLoopInvariant(const Loop *L) const {
- LLVM_UNREACHABLE("Attempt to use a SCEVCouldNotCompute object!");
+ llvm_unreachable("Attempt to use a SCEVCouldNotCompute object!");
return false;
}
const Type *SCEVCouldNotCompute::getType() const {
- LLVM_UNREACHABLE("Attempt to use a SCEVCouldNotCompute object!");
+ llvm_unreachable("Attempt to use a SCEVCouldNotCompute object!");
return 0;
}
bool SCEVCouldNotCompute::hasComputableLoopEvolution(const Loop *L) const {
- LLVM_UNREACHABLE("Attempt to use a SCEVCouldNotCompute object!");
+ llvm_unreachable("Attempt to use a SCEVCouldNotCompute object!");
return false;
}
else if (isa<SCEVUMaxExpr>(this))
return SE.getUMaxExpr(NewOps);
else
- LLVM_UNREACHABLE("Unknown commutative expr!");
+ llvm_unreachable("Unknown commutative expr!");
}
}
return this;
return operator()(LC->getOperand(), RC->getOperand());
}
- LLVM_UNREACHABLE("Unknown SCEV kind!");
+ llvm_unreachable("Unknown SCEV kind!");
return false;
}
};
if (Idx >= ATy->getNumElements()) return 0; // Bogus program
Init = Context->getNullValue(ATy->getElementType());
} else {
- LLVM_UNREACHABLE("Unknown constant aggregate type!");
+ llvm_unreachable("Unknown constant aggregate type!");
}
return 0;
} else {
return getSMaxExpr(NewOps);
if (isa<SCEVUMaxExpr>(Comm))
return getUMaxExpr(NewOps);
- LLVM_UNREACHABLE("Unknown commutative SCEV type!");
+ llvm_unreachable("Unknown commutative SCEV type!");
}
}
// If we got here, all operands are loop invariant.
return getTruncateExpr(Op, Cast->getType());
}
- LLVM_UNREACHABLE("Unknown SCEV type!");
+ llvm_unreachable("Unknown SCEV type!");
return 0;
}
uint64_t Pair[2];
switch (Kind) {
- default: LLVM_UNREACHABLE("Unknown kind!");
+ default: llvm_unreachable("Unknown kind!");
case 'K':
// F80HexFPConstant - x87 long double in hexadecimal format (10 bytes)
FP80HexToIntPair(TokStart+3, CurPtr, Pair);
return Error(ID.Loc, "functions are not values, refer to them as pointers");
switch (ID.Kind) {
- default: LLVM_UNREACHABLE("Unknown ValID!");
+ default: llvm_unreachable("Unknown ValID!");
case ValID::t_LocalID:
case ValID::t_LocalName:
return Error(ID.Loc, "invalid use of function-local name");
bool Valid;
switch (OperandType) {
- default: LLVM_UNREACHABLE("Unknown operand type!");
+ default: llvm_unreachable("Unknown operand type!");
case 0: // int or FP.
Valid = LHS->getType()->isIntOrIntVector() ||
LHS->getType()->isFPOrFPVector();
static unsigned GetEncodedCastOpcode(unsigned Opcode) {
switch (Opcode) {
- default: LLVM_UNREACHABLE("Unknown cast instruction!");
+ default: llvm_unreachable("Unknown cast instruction!");
case Instruction::Trunc : return bitc::CAST_TRUNC;
case Instruction::ZExt : return bitc::CAST_ZEXT;
case Instruction::SExt : return bitc::CAST_SEXT;
static unsigned GetEncodedBinaryOpcode(unsigned Opcode) {
switch (Opcode) {
- default: LLVM_UNREACHABLE("Unknown binary instruction!");
+ default: llvm_unreachable("Unknown binary instruction!");
case Instruction::Add:
case Instruction::FAdd: return bitc::BINOP_ADD;
case Instruction::Sub:
unsigned Code = 0;
switch (T->getTypeID()) {
- default: LLVM_UNREACHABLE("Unknown type!");
+ default: llvm_unreachable("Unknown type!");
case Type::VoidTyID: Code = bitc::TYPE_CODE_VOID; break;
case Type::FloatTyID: Code = bitc::TYPE_CODE_FLOAT; break;
case Type::DoubleTyID: Code = bitc::TYPE_CODE_DOUBLE; break;
static unsigned getEncodedLinkage(const GlobalValue *GV) {
switch (GV->getLinkage()) {
- default: LLVM_UNREACHABLE("Invalid linkage!");
+ default: llvm_unreachable("Invalid linkage!");
case GlobalValue::GhostLinkage: // Map ghost linkage onto external.
case GlobalValue::ExternalLinkage: return 0;
case GlobalValue::WeakAnyLinkage: return 1;
static unsigned getEncodedVisibility(const GlobalValue *GV) {
switch (GV->getVisibility()) {
- default: LLVM_UNREACHABLE("Invalid visibility!");
+ default: llvm_unreachable("Invalid visibility!");
case GlobalValue::DefaultVisibility: return 0;
case GlobalValue::HiddenVisibility: return 1;
case GlobalValue::ProtectedVisibility: return 2;
}
}
} else {
- LLVM_UNREACHABLE("Unknown constant!");
+ llvm_unreachable("Unknown constant!");
}
Stream.EmitRecord(Code, Record, AbbrevToUse);
Record.clear();
Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 8));
if (Stream.EmitBlockInfoAbbrev(bitc::VALUE_SYMTAB_BLOCK_ID,
Abbv) != VST_ENTRY_8_ABBREV)
- LLVM_UNREACHABLE("Unexpected abbrev ordering!");
+ llvm_unreachable("Unexpected abbrev ordering!");
}
{ // 7-bit fixed width VST_ENTRY strings.
Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 7));
if (Stream.EmitBlockInfoAbbrev(bitc::VALUE_SYMTAB_BLOCK_ID,
Abbv) != VST_ENTRY_7_ABBREV)
- LLVM_UNREACHABLE("Unexpected abbrev ordering!");
+ llvm_unreachable("Unexpected abbrev ordering!");
}
{ // 6-bit char6 VST_ENTRY strings.
BitCodeAbbrev *Abbv = new BitCodeAbbrev();
Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Char6));
if (Stream.EmitBlockInfoAbbrev(bitc::VALUE_SYMTAB_BLOCK_ID,
Abbv) != VST_ENTRY_6_ABBREV)
- LLVM_UNREACHABLE("Unexpected abbrev ordering!");
+ llvm_unreachable("Unexpected abbrev ordering!");
}
{ // 6-bit char6 VST_BBENTRY strings.
BitCodeAbbrev *Abbv = new BitCodeAbbrev();
Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Char6));
if (Stream.EmitBlockInfoAbbrev(bitc::VALUE_SYMTAB_BLOCK_ID,
Abbv) != VST_BBENTRY_6_ABBREV)
- LLVM_UNREACHABLE("Unexpected abbrev ordering!");
+ llvm_unreachable("Unexpected abbrev ordering!");
}
Log2_32_Ceil(VE.getTypes().size()+1)));
if (Stream.EmitBlockInfoAbbrev(bitc::CONSTANTS_BLOCK_ID,
Abbv) != CONSTANTS_SETTYPE_ABBREV)
- LLVM_UNREACHABLE("Unexpected abbrev ordering!");
+ llvm_unreachable("Unexpected abbrev ordering!");
}
{ // INTEGER abbrev for CONSTANTS_BLOCK.
Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 8));
if (Stream.EmitBlockInfoAbbrev(bitc::CONSTANTS_BLOCK_ID,
Abbv) != CONSTANTS_INTEGER_ABBREV)
- LLVM_UNREACHABLE("Unexpected abbrev ordering!");
+ llvm_unreachable("Unexpected abbrev ordering!");
}
{ // CE_CAST abbrev for CONSTANTS_BLOCK.
if (Stream.EmitBlockInfoAbbrev(bitc::CONSTANTS_BLOCK_ID,
Abbv) != CONSTANTS_CE_CAST_Abbrev)
- LLVM_UNREACHABLE("Unexpected abbrev ordering!");
+ llvm_unreachable("Unexpected abbrev ordering!");
}
{ // NULL abbrev for CONSTANTS_BLOCK.
BitCodeAbbrev *Abbv = new BitCodeAbbrev();
Abbv->Add(BitCodeAbbrevOp(bitc::CST_CODE_NULL));
if (Stream.EmitBlockInfoAbbrev(bitc::CONSTANTS_BLOCK_ID,
Abbv) != CONSTANTS_NULL_Abbrev)
- LLVM_UNREACHABLE("Unexpected abbrev ordering!");
+ llvm_unreachable("Unexpected abbrev ordering!");
}
// FIXME: This should only use space for first class types!
Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 1)); // volatile
if (Stream.EmitBlockInfoAbbrev(bitc::FUNCTION_BLOCK_ID,
Abbv) != FUNCTION_INST_LOAD_ABBREV)
- LLVM_UNREACHABLE("Unexpected abbrev ordering!");
+ llvm_unreachable("Unexpected abbrev ordering!");
}
{ // INST_BINOP abbrev for FUNCTION_BLOCK.
BitCodeAbbrev *Abbv = new BitCodeAbbrev();
Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 4)); // opc
if (Stream.EmitBlockInfoAbbrev(bitc::FUNCTION_BLOCK_ID,
Abbv) != FUNCTION_INST_BINOP_ABBREV)
- LLVM_UNREACHABLE("Unexpected abbrev ordering!");
+ llvm_unreachable("Unexpected abbrev ordering!");
}
{ // INST_CAST abbrev for FUNCTION_BLOCK.
BitCodeAbbrev *Abbv = new BitCodeAbbrev();
Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 4)); // opc
if (Stream.EmitBlockInfoAbbrev(bitc::FUNCTION_BLOCK_ID,
Abbv) != FUNCTION_INST_CAST_ABBREV)
- LLVM_UNREACHABLE("Unexpected abbrev ordering!");
+ llvm_unreachable("Unexpected abbrev ordering!");
}
{ // INST_RET abbrev for FUNCTION_BLOCK.
Abbv->Add(BitCodeAbbrevOp(bitc::FUNC_CODE_INST_RET));
if (Stream.EmitBlockInfoAbbrev(bitc::FUNCTION_BLOCK_ID,
Abbv) != FUNCTION_INST_RET_VOID_ABBREV)
- LLVM_UNREACHABLE("Unexpected abbrev ordering!");
+ llvm_unreachable("Unexpected abbrev ordering!");
}
{ // INST_RET abbrev for FUNCTION_BLOCK.
BitCodeAbbrev *Abbv = new BitCodeAbbrev();
Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // ValID
if (Stream.EmitBlockInfoAbbrev(bitc::FUNCTION_BLOCK_ID,
Abbv) != FUNCTION_INST_RET_VAL_ABBREV)
- LLVM_UNREACHABLE("Unexpected abbrev ordering!");
+ llvm_unreachable("Unexpected abbrev ordering!");
}
{ // INST_UNREACHABLE abbrev for FUNCTION_BLOCK.
BitCodeAbbrev *Abbv = new BitCodeAbbrev();
Abbv->Add(BitCodeAbbrevOp(bitc::FUNC_CODE_INST_UNREACHABLE));
if (Stream.EmitBlockInfoAbbrev(bitc::FUNCTION_BLOCK_ID,
Abbv) != FUNCTION_INST_UNREACHABLE_ABBREV)
- LLVM_UNREACHABLE("Unexpected abbrev ordering!");
+ llvm_unreachable("Unexpected abbrev ordering!");
}
Stream.ExitBlock();
else if (I->hasWeakLinkage())
O << TAI->getWeakRefDirective() << Name << '\n';
else if (!I->hasLocalLinkage())
- LLVM_UNREACHABLE("Invalid alias linkage");
+ llvm_unreachable("Invalid alias linkage");
printVisibility(Name, I->getVisibility());
case Instruction::SIToFP:
case Instruction::FPToUI:
case Instruction::FPToSI:
- LLVM_UNREACHABLE("FIXME: Don't yet support this kind of constant cast expr");
+ llvm_unreachable("FIXME: Don't yet support this kind of constant cast expr");
break;
case Instruction::BitCast:
return EmitConstantValueOnly(CE->getOperand(0));
O << ')';
break;
default:
- LLVM_UNREACHABLE("Unsupported operator!");
+ llvm_unreachable("Unsupported operator!");
}
} else {
- LLVM_UNREACHABLE("Unknown constant value!");
+ llvm_unreachable("Unknown constant value!");
}
}
O << '\n';
}
return;
- } else LLVM_UNREACHABLE("Floating point constant type not handled");
+ } else llvm_unreachable("Floating point constant type not handled");
}
void AsmPrinter::EmitGlobalConstantLargeInt(const ConstantInt *CI,
void AsmPrinter::EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
// Target doesn't support this yet!
- LLVM_UNREACHABLE("Target does not support EmitMachineConstantPoolValue");
+ llvm_unreachable("Target does not support EmitMachineConstantPoolValue");
}
/// PrintSpecial - Print information related to the specified machine instr
"Target cannot handle 64-bit constant exprs!");
O << TAI->getData64bitsDirective(AddrSpace);
} else {
- LLVM_UNREACHABLE("Target cannot handle given data directive width!");
+ llvm_unreachable("Target cannot handle given data directive width!");
}
break;
}
}
cerr << "no GCMetadataPrinter registered for GC: " << Name << "\n";
- llvm_unreachable();
+ llvm_unreachable(0);
}
/// EmitComments - Pretty-print comments for instructions
case dwarf::DW_FORM_data8: Asm->EmitInt64(Integer); break;
case dwarf::DW_FORM_udata: Asm->EmitULEB128Bytes(Integer); break;
case dwarf::DW_FORM_sdata: Asm->EmitSLEB128Bytes(Integer); break;
- default: LLVM_UNREACHABLE("DIE Value form not supported yet");
+ default: llvm_unreachable("DIE Value form not supported yet");
}
}
case dwarf::DW_FORM_data8: return sizeof(int64_t);
case dwarf::DW_FORM_udata: return TargetAsmInfo::getULEB128Size(Integer);
case dwarf::DW_FORM_sdata: return TargetAsmInfo::getSLEB128Size(Integer);
- default: LLVM_UNREACHABLE("DIE Value form not supported yet"); break;
+ default: llvm_unreachable("DIE Value form not supported yet"); break;
}
return 0;
}
case dwarf::DW_FORM_block2: Asm->EmitInt16(Size); break;
case dwarf::DW_FORM_block4: Asm->EmitInt32(Size); break;
case dwarf::DW_FORM_block: Asm->EmitULEB128Bytes(Size); break;
- default: LLVM_UNREACHABLE("Improper form for block"); break;
+ default: llvm_unreachable("Improper form for block"); break;
}
const SmallVector<DIEAbbrevData, 8> &AbbrevData = Abbrev.getData();
case dwarf::DW_FORM_block2: return Size + sizeof(int16_t);
case dwarf::DW_FORM_block4: return Size + sizeof(int32_t);
case dwarf::DW_FORM_block: return Size + TargetAsmInfo::getULEB128Size(Size);
- default: LLVM_UNREACHABLE("Improper form for block"); break;
+ default: llvm_unreachable("Improper form for block"); break;
}
return 0;
}
Asm->EmitULEB128Bytes(Offset);
Asm->EOL("Offset");
} else {
- LLVM_UNREACHABLE("Machine move not supported yet.");
+ llvm_unreachable("Machine move not supported yet.");
}
} else if (Src.isReg() &&
Src.getReg() == MachineLocation::VirtualFP) {
Asm->EmitULEB128Bytes(RI->getDwarfRegNum(Dst.getReg(), isEH));
Asm->EOL("Register");
} else {
- LLVM_UNREACHABLE("Machine move not supported yet.");
+ llvm_unreachable("Machine move not supported yet.");
}
} else {
unsigned Reg = RI->getDwarfRegNum(Src.getReg(), isEH);
// _GLIBCXX_DEBUG checks strict weak ordering, which involves comparing
// an object with itself.
#ifndef _GLIBCXX_DEBUG
- LLVM_UNREACHABLE("Predecessor appears twice");
+ llvm_unreachable("Predecessor appears twice");
#endif
return false;
}
MR.setResultPointer((void*)Addr);
MR.setConstantVal(JumpTableSectionIdx);
} else {
- LLVM_UNREACHABLE("Unhandled relocation type");
+ llvm_unreachable("Unhandled relocation type");
}
ES->addRelocation(MR);
}
unsigned ELFWriter::getGlobalELFVisibility(const GlobalValue *GV) {
switch (GV->getVisibility()) {
default:
- LLVM_UNREACHABLE("unknown visibility type");
+ llvm_unreachable("unknown visibility type");
case GlobalValue::DefaultVisibility:
return ELFSym::STV_DEFAULT;
case GlobalValue::HiddenVisibility:
else if (CFP->getType() == Type::FloatTy)
GblS.emitWord32(Val);
else if (CFP->getType() == Type::X86_FP80Ty) {
- LLVM_UNREACHABLE("X86_FP80Ty global emission not implemented");
+ llvm_unreachable("X86_FP80Ty global emission not implemented");
} else if (CFP->getType() == Type::PPC_FP128Ty)
- LLVM_UNREACHABLE("PPC_FP128Ty global emission not implemented");
+ llvm_unreachable("PPC_FP128Ty global emission not implemented");
return;
} else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
if (Size == 4)
else if (Size == 8)
GblS.emitWord64(CI->getZExtValue());
else
- LLVM_UNREACHABLE("LargeInt global emission not implemented");
+ llvm_unreachable("LargeInt global emission not implemented");
return;
} else if (const ConstantVector *CP = dyn_cast<ConstantVector>(CV)) {
const VectorType *PTy = CP->getType();
EmitGlobalConstant(CP->getOperand(I), GblS);
return;
}
- LLVM_UNREACHABLE("unknown global constant");
+ llvm_unreachable("unknown global constant");
}
}
cerr << "unsupported GC: " << Name << "\n";
- llvm_unreachable();
+ llvm_unreachable(0);
}
GCFunctionInfo &GCModuleInfo::getFunctionInfo(const Function &F) {
static const char *DescKind(GC::PointKind Kind) {
switch (Kind) {
- default: LLVM_UNREACHABLE("Unknown GC point kind");
+ default: llvm_unreachable("Unknown GC point kind");
case GC::Loop: return "loop";
case GC::Return: return "return";
case GC::PreCall: return "pre-call";
bool GCStrategy::performCustomLowering(Function &F) {
cerr << "gc " << getName() << " must override performCustomLowering.\n";
- llvm_unreachable();
+ llvm_unreachable(0);
return 0;
}
#ifndef NDEBUG
cerr << "Unable to predicate " << *I << "!\n";
#endif
- llvm_unreachable();
+ llvm_unreachable(0);
}
}
#ifndef NDEBUG
cerr << "Unable to predicate " << *I << "!\n";
#endif
- llvm_unreachable();
+ llvm_unreachable(0);
}
}
IRBuilder<> Builder(IP->getParent(), IP);
switch(BitSize) {
- default: LLVM_UNREACHABLE("Unhandled type size of value to byteswap!");
+ default: llvm_unreachable("Unhandled type size of value to byteswap!");
case 16: {
Value *Tmp1 = Builder.CreateShl(V, ConstantInt::get(V->getType(), 8),
"bswap.2");
const char *Dname,
const char *LDname) {
switch (CI->getOperand(1)->getType()->getTypeID()) {
- default: LLVM_UNREACHABLE("Invalid type in intrinsic");
+ default: llvm_unreachable("Invalid type in intrinsic");
case Type::FloatTyID:
ReplaceCallWith(Fname, CI, CI->op_begin() + 1, CI->op_end(),
Type::FloatTy);
unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
if (tii_->isMoveInstr(*VNI->copy, SrcReg, DstReg, SrcSubReg, DstSubReg))
return SrcReg;
- LLVM_UNREACHABLE("Unrecognized copy instruction!");
+ llvm_unreachable("Unrecognized copy instruction!");
return 0;
}
// FIXME: This should be a set or something that uniques
MOW.PendingGlobals.push_back(MR.getGlobalValue());
} else {
- LLVM_UNREACHABLE("Unhandled relocation type");
+ llvm_unreachable("Unhandled relocation type");
}
MOS->addRelocation(MR);
}
case Instruction::Add:
default:
cerr << "ConstantExpr not handled as global var init: " << *CE << "\n";
- llvm_unreachable();
+ llvm_unreachable(0);
}
} else if (PC->getType()->isSingleValueType()) {
unsigned char *ptr = (unsigned char *)PA;
ptr[6] = val >> 48;
ptr[7] = val >> 56;
} else {
- LLVM_UNREACHABLE("Not implemented: bit widths > 64");
+ llvm_unreachable("Not implemented: bit widths > 64");
}
break;
}
ScatteredOffset));
ScatteredOffset = 0;
} else
- LLVM_UNREACHABLE("Unknown constant pointer type!");
+ llvm_unreachable("Unknown constant pointer type!");
break;
default:
std::string msg;
PA+SL->getElementOffset(i)));
} else {
cerr << "Bad Type: " << *PC->getType() << "\n";
- LLVM_UNREACHABLE("Unknown constant type to initialize memory with!");
+ llvm_unreachable("Unknown constant type to initialize memory with!");
}
}
}
switch (GV->getLinkage()) {
default:
- LLVM_UNREACHABLE("Unexpected linkage type!");
+ llvm_unreachable("Unexpected linkage type!");
break;
case GlobalValue::WeakAnyLinkage:
case GlobalValue::WeakODRLinkage:
return false;
switch (getType()) {
- default: LLVM_UNREACHABLE("Unrecognized operand type");
+ default: llvm_unreachable("Unrecognized operand type");
case MachineOperand::MO_Register:
return getReg() == Other.getReg() && isDef() == Other.isDef() &&
getSubReg() == Other.getSubReg();
OS << '>';
break;
default:
- LLVM_UNREACHABLE("Unrecognized operand type");
+ llvm_unreachable("Unrecognized operand type");
}
if (unsigned TF = getTargetFlags())
}
// This should never happen
- LLVM_UNREACHABLE("Personality function should be set!");
+ llvm_unreachable("Personality function should be set!");
return 0;
}
cerr << "*** Scheduling failed! ***\n";
SuccSU->dump(this);
cerr << " has been released too many times!\n";
- llvm_unreachable();
+ llvm_unreachable(0);
}
#endif
this == getConstantPool() ||
this == getJumpTable())
return true;
- LLVM_UNREACHABLE("Unknown PseudoSourceValue!");
+ llvm_unreachable("Unknown PseudoSourceValue!");
return false;
}
}
}
if (Error)
- llvm_unreachable();
+ llvm_unreachable(0);
#endif
regUse_.clear();
regUseBackUp_.clear();
ISD::ArgFlagsTy ArgFlags =
cast<ARG_FLAGSSDNode>(TheArgs->getOperand(3+i))->getArgFlags();
if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) {
- std::string msg;
- raw_string_ostream Msg(msg);
- Msg << "Formal argument #" << i << " has unhandled type "
+#ifndef NDEBUG
+ cerr << "Formal argument #" << i << " has unhandled type "
<< ArgVT.getMVTString();
- llvm_report_error(Msg.str());
+#endif
+ llvm_unreachable(0);
}
}
}
MVT VT = TheRet->getOperand(i*2+1).getValueType();
ISD::ArgFlagsTy ArgFlags =
cast<ARG_FLAGSSDNode>(TheRet->getOperand(i*2+2))->getArgFlags();
- if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)){
- std::string msg;
- raw_string_ostream Msg(msg);
- Msg << "Return operand #" << i << " has unhandled type "
+ if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) {
+#ifndef NDEBUG
+ cerr << "Return operand #" << i << " has unhandled type "
<< VT.getMVTString();
- llvm_report_error(Msg.str());
+#endif
+ llvm_unreachable(0);
}
}
}
MVT ArgVT = TheCall->getArg(i).getValueType();
ISD::ArgFlagsTy ArgFlags = TheCall->getArgFlags(i);
if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) {
- std::string msg;
- raw_string_ostream Msg(msg);
- Msg << "Call operand #" << i << " has unhandled type "
+#ifndef NDEBUG
+ cerr << "Call operand #" << i << " has unhandled type "
<< ArgVT.getMVTString();
- llvm_report_error(Msg.str());
+#endif
+ llvm_unreachable(0);
}
}
}
MVT ArgVT = ArgVTs[i];
ISD::ArgFlagsTy ArgFlags = Flags[i];
if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) {
- std::string msg;
- raw_string_ostream Msg(msg);
- Msg << "Call operand #" << i << " has unhandled type "
+#ifndef NDEBUG
+ cerr << "Call operand #" << i << " has unhandled type "
<< ArgVT.getMVTString();
- llvm_report_error(Msg.str());
+#endif
+ llvm_unreachable(0);
}
}
}
if (TheCall->isInreg())
Flags.setInReg();
if (Fn(i, VT, VT, CCValAssign::Full, Flags, *this)) {
- std::string msg;
- raw_string_ostream Msg(msg);
- Msg << "Call result #" << i << " has unhandled type "
+#ifndef NDEBUG
+ cerr << "Call result #" << i << " has unhandled type "
<< VT.getMVTString();
- llvm_report_error(Msg.str());
+#endif
+ llvm_unreachable(0);
}
}
}
/// produce a single value.
void CCState::AnalyzeCallResult(MVT VT, CCAssignFn Fn) {
if (Fn(0, VT, VT, CCValAssign::Full, ISD::ArgFlagsTy(), *this)) {
- std::string msg;
- raw_string_ostream Msg(msg);
- Msg << "Call result has unhandled type "
+#ifndef NDEBUG
+ cerr << "Call result has unhandled type "
<< VT.getMVTString();
- llvm_report_error(Msg.str());
+#endif
+ llvm_unreachable(0);
}
}
assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
switch (Op.getOpcode()) {
- default: LLVM_UNREACHABLE("Unknown code");
+ default: llvm_unreachable("Unknown code");
case ISD::ConstantFP: {
APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
V.changeSign();
if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) {
switch (N0.getOpcode()) {
default:
- LLVM_UNREACHABLE("Unhandled SetCC Equivalent!");
+ llvm_unreachable("Unhandled SetCC Equivalent!");
case ISD::SETCC:
return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC);
case ISD::SELECT_CC:
if (Value.getOpcode() != ISD::TargetConstantFP) {
SDValue Tmp;
switch (CFP->getValueType(0).getSimpleVT()) {
- default: LLVM_UNREACHABLE("Unknown FP type");
+ default: llvm_unreachable("Unknown FP type");
case MVT::f80: // We don't do this for these yet.
case MVT::f128:
case MVT::ppcf128:
SrcValue = ST->getSrcValue();
SrcValueOffset = ST->getSrcValueOffset();
} else {
- LLVM_UNREACHABLE("FindAliasInfo expected a memory operand");
+ llvm_unreachable("FindAliasInfo expected a memory operand");
}
return false;
#ifndef NDEBUG
cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
#endif
- LLVM_UNREACHABLE("Do not know how to legalize this operator!");
+ llvm_unreachable("Do not know how to legalize this operator!");
case ISD::CALL:
// The only option for this is to custom lower it.
Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
return Tmp2;
case ISD::BUILD_VECTOR:
switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
- default: LLVM_UNREACHABLE("This action is not supported yet!");
+ default: llvm_unreachable("This action is not supported yet!");
case TargetLowering::Custom:
Tmp3 = TLI.LowerOperation(Result, DAG);
if (Tmp3.getNode()) {
Tmp4 = Result.getValue(1);
switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
- default: LLVM_UNREACHABLE("This action is not supported yet!");
+ default: llvm_unreachable("This action is not supported yet!");
case TargetLowering::Legal:
// If this is an unaligned load and the target doesn't support it,
// expand it.
Tmp2 = LegalizeOp(Ch);
} else {
switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
- default: LLVM_UNREACHABLE("This action is not supported yet!");
+ default: llvm_unreachable("This action is not supported yet!");
case TargetLowering::Custom:
isCustom = true;
// FALLTHROUGH
MVT VT = Tmp3.getValueType();
switch (TLI.getOperationAction(ISD::STORE, VT)) {
- default: LLVM_UNREACHABLE("This action is not supported yet!");
+ default: llvm_unreachable("This action is not supported yet!");
case TargetLowering::Legal:
// If this is an unaligned store and the target doesn't support it,
// expand it.
ST->getOffset());
switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
- default: LLVM_UNREACHABLE("This action is not supported yet!");
+ default: llvm_unreachable("This action is not supported yet!");
case TargetLowering::Legal:
// If this is an unaligned store and the target doesn't support it,
// expand it.
MVT OpVT = LHS.getValueType();
ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
switch (TLI.getCondCodeAction(CCCode, OpVT)) {
- default: LLVM_UNREACHABLE("Unknown condition code action!");
+ default: llvm_unreachable("Unknown condition code action!");
case TargetLowering::Legal:
// Nothing to do.
break;
ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
unsigned Opc = 0;
switch (CCCode) {
- default: LLVM_UNREACHABLE("Don't know how to expand this condition!");
+ default: llvm_unreachable("Don't know how to expand this condition!");
case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
RTLIB::Libcall Call_PPCF128) {
RTLIB::Libcall LC;
switch (Node->getValueType(0).getSimpleVT()) {
- default: LLVM_UNREACHABLE("Unexpected request for libcall!");
+ default: llvm_unreachable("Unexpected request for libcall!");
case MVT::f32: LC = Call_F32; break;
case MVT::f64: LC = Call_F64; break;
case MVT::f80: LC = Call_F80; break;
RTLIB::Libcall Call_I128) {
RTLIB::Libcall LC;
switch (Node->getValueType(0).getSimpleVT()) {
- default: LLVM_UNREACHABLE("Unexpected request for libcall!");
+ default: llvm_unreachable("Unexpected request for libcall!");
case MVT::i16: LC = Call_I16; break;
case MVT::i32: LC = Call_I32; break;
case MVT::i64: LC = Call_I64; break;
// offset depending on the data type.
uint64_t FF;
switch (Op0.getValueType().getSimpleVT()) {
- default: LLVM_UNREACHABLE("Unsupported integer type!");
+ default: llvm_unreachable("Unsupported integer type!");
case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
MVT SHVT = TLI.getShiftAmountTy();
SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
switch (VT.getSimpleVT()) {
- default: LLVM_UNREACHABLE("Unhandled Expand type in BSWAP!");
+ default: llvm_unreachable("Unhandled Expand type in BSWAP!");
case MVT::i16:
Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
DebugLoc dl) {
switch (Opc) {
- default: LLVM_UNREACHABLE("Cannot expand this yet!");
+ default: llvm_unreachable("Cannot expand this yet!");
case ISD::CTPOP: {
static const uint64_t mask[6] = {
0x5555555555555555ULL, 0x3333333333333333ULL,
else if (VT.isFloatingPoint())
Results.push_back(DAG.getConstantFP(0, VT));
else
- LLVM_UNREACHABLE("Unknown value type!");
+ llvm_unreachable("Unknown value type!");
break;
}
case ISD::TRAP: {
// type in some cases cases.
// Also, we can fall back to a division in some cases, but that's a big
// performance hit in the general case.
- LLVM_UNREACHABLE("Don't know how to expand this operation yet!");
+ llvm_unreachable("Don't know how to expand this operation yet!");
}
if (isSigned) {
Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, TLI.getShiftAmountTy());
break;
}
if (NewInTy.isInteger())
- LLVM_UNREACHABLE("Cannot promote Legal Integer SETCC yet");
+ llvm_unreachable("Cannot promote Legal Integer SETCC yet");
else {
Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp1);
Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp2);
cerr << "SoftenFloatResult #" << ResNo << ": ";
N->dump(&DAG); cerr << "\n";
#endif
- LLVM_UNREACHABLE("Do not know how to soften the result of this operator!");
+ llvm_unreachable("Do not know how to soften the result of this operator!");
case ISD::BIT_CONVERT: R = SoftenFloatRes_BIT_CONVERT(N); break;
case ISD::BUILD_PAIR: R = SoftenFloatRes_BUILD_PAIR(N); break;
cerr << "SoftenFloatOperand Op #" << OpNo << ": ";
N->dump(&DAG); cerr << "\n";
#endif
- LLVM_UNREACHABLE("Do not know how to soften this operator's operand!");
+ llvm_unreachable("Do not know how to soften this operator's operand!");
case ISD::BIT_CONVERT: Res = SoftenFloatOp_BIT_CONVERT(N); break;
case ISD::BR_CC: Res = SoftenFloatOp_BR_CC(N); break;
cerr << "ExpandFloatResult #" << ResNo << ": ";
N->dump(&DAG); cerr << "\n";
#endif
- LLVM_UNREACHABLE("Do not know how to expand the result of this operator!");
+ llvm_unreachable("Do not know how to expand the result of this operator!");
case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
cerr << "ExpandFloatOperand Op #" << OpNo << ": ";
N->dump(&DAG); cerr << "\n";
#endif
- LLVM_UNREACHABLE("Do not know how to expand this operator's operand!");
+ llvm_unreachable("Do not know how to expand this operator's operand!");
case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break;
case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
cerr << "PromoteIntegerResult #" << ResNo << ": ";
N->dump(&DAG); cerr << "\n";
#endif
- LLVM_UNREACHABLE("Do not know how to promote this operator!");
+ llvm_unreachable("Do not know how to promote this operator!");
case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
case ISD::BIT_CONVERT: Res = PromoteIntRes_BIT_CONVERT(N); break;
SDValue Res;
switch (getTypeAction(N->getOperand(0).getValueType())) {
- default: LLVM_UNREACHABLE("Unknown type action!");
+ default: llvm_unreachable("Unknown type action!");
case Legal:
case ExpandInteger:
Res = N->getOperand(0);
cerr << "PromoteIntegerOperand Op #" << OpNo << ": ";
N->dump(&DAG); cerr << "\n";
#endif
- LLVM_UNREACHABLE("Do not know how to promote this operator's operand!");
+ llvm_unreachable("Do not know how to promote this operator's operand!");
case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
case ISD::BIT_CONVERT: Res = PromoteIntOp_BIT_CONVERT(N); break;
// insert sign extends for ALL conditions, but zero extend is cheaper on
// many machines (an AND instead of two shifts), so prefer it.
switch (CCCode) {
- default: LLVM_UNREACHABLE("Unknown integer comparison!");
+ default: llvm_unreachable("Unknown integer comparison!");
case ISD::SETEQ:
case ISD::SETNE:
case ISD::SETUGE:
cerr << "ExpandIntegerResult #" << ResNo << ": ";
N->dump(&DAG); cerr << "\n";
#endif
- LLVM_UNREACHABLE("Do not know how to expand the result of this operator!");
+ llvm_unreachable("Do not know how to expand the result of this operator!");
case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
DAG.getConstant(~HighBitMask, ShTy));
switch (N->getOpcode()) {
- default: LLVM_UNREACHABLE("Unknown shift");
+ default: llvm_unreachable("Unknown shift");
case ISD::SHL:
Lo = DAG.getConstant(0, NVT); // Low part is zero.
Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
Amt);
unsigned Op1, Op2;
switch (N->getOpcode()) {
- default: LLVM_UNREACHABLE("Unknown shift");
+ default: llvm_unreachable("Unknown shift");
case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
case ISD::SRL:
case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
SDValue Lo1, Hi1, Lo2, Hi2;
switch (N->getOpcode()) {
- default: LLVM_UNREACHABLE("Unknown shift");
+ default: llvm_unreachable("Unknown shift");
case ISD::SHL:
// ShAmt < NVTBits
Lo1 = DAG.getConstant(0, NVT); // Low part is zero.
}
if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
- LLVM_UNREACHABLE("Unsupported shift!");
+ llvm_unreachable("Unsupported shift!");
}
void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
cerr << "ExpandIntegerOperand Op #" << OpNo << ": ";
N->dump(&DAG); cerr << "\n";
#endif
- LLVM_UNREACHABLE("Do not know how to expand this operator's operand!");
+ llvm_unreachable("Do not know how to expand this operator's operand!");
case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break;
case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
// FIXME: This generated code sucks.
ISD::CondCode LowCC;
switch (CCCode) {
- default: LLVM_UNREACHABLE("Unknown integer setcc!");
+ default: llvm_unreachable("Unknown integer setcc!");
case ISD::SETLT:
case ISD::SETULT: LowCC = ISD::SETULT; break;
case ISD::SETGT:
if (Mapped & 128)
cerr << " WidenedVectors";
cerr << "\n";
- llvm_unreachable();
+ llvm_unreachable(0);
}
}
}
if (Failed) {
I->dump(&DAG); cerr << "\n";
- llvm_unreachable();
+ llvm_unreachable(0);
}
}
#endif
cerr << "ScalarizeVectorResult #" << ResNo << ": ";
N->dump(&DAG); cerr << "\n";
#endif
- LLVM_UNREACHABLE("Do not know how to scalarize the result of this operator!");
+ llvm_unreachable("Do not know how to scalarize the result of this operator!");
case ISD::BIT_CONVERT: R = ScalarizeVecRes_BIT_CONVERT(N); break;
case ISD::BUILD_VECTOR: R = N->getOperand(0); break;
cerr << "ScalarizeVectorOperand Op #" << OpNo << ": ";
N->dump(&DAG); cerr << "\n";
#endif
- LLVM_UNREACHABLE("Do not know how to scalarize this operator's operand!");
+ llvm_unreachable("Do not know how to scalarize this operator's operand!");
case ISD::BIT_CONVERT:
Res = ScalarizeVecOp_BIT_CONVERT(N);
break;
cerr << "SplitVectorResult #" << ResNo << ": ";
N->dump(&DAG); cerr << "\n";
#endif
- LLVM_UNREACHABLE("Do not know how to split the result of this operator!");
+ llvm_unreachable("Do not know how to split the result of this operator!");
case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
SDValue VLo, VHi;
MVT InVT = N->getOperand(0).getValueType();
switch (getTypeAction(InVT)) {
- default: LLVM_UNREACHABLE("Unexpected type action!");
+ default: llvm_unreachable("Unexpected type action!");
case Legal: {
MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
LoVT.getVectorNumElements());
// Split the input.
MVT InVT = N->getOperand(0).getValueType();
switch (getTypeAction(InVT)) {
- default: LLVM_UNREACHABLE("Unexpected type action!");
+ default: llvm_unreachable("Unexpected type action!");
case Legal: {
MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
LoVT.getVectorNumElements());
cerr << "SplitVectorOperand Op #" << OpNo << ": ";
N->dump(&DAG); cerr << "\n";
#endif
- LLVM_UNREACHABLE("Do not know how to split this operator's operand!");
+ llvm_unreachable("Do not know how to split this operator's operand!");
case ISD::BIT_CONVERT: Res = SplitVecOp_BIT_CONVERT(N); break;
case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
cerr << "WidenVectorResult #" << ResNo << ": ";
N->dump(&DAG); cerr << "\n";
#endif
- LLVM_UNREACHABLE("Do not know how to widen the result of this operator!");
+ llvm_unreachable("Do not know how to widen the result of this operator!");
case ISD::BIT_CONVERT: Res = WidenVecRes_BIT_CONVERT(N); break;
case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
cerr << "WidenVectorOperand op #" << ResNo << ": ";
N->dump(&DAG); cerr << "\n";
#endif
- LLVM_UNREACHABLE("Do not know how to widen this operator's operand!");
+ llvm_unreachable("Do not know how to widen this operator's operand!");
case ISD::BIT_CONVERT: Res = WidenVecOp_BIT_CONVERT(N); break;
case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
cerr << "*** Scheduling failed! ***\n";
PredSU->dump(this);
cerr << " has been released too many times!\n";
- llvm_unreachable();
+ llvm_unreachable(0);
}
#endif
}
if (!CurSU) {
- LLVM_UNREACHABLE("Unable to resolve live physical register dependencies!");
+ llvm_unreachable("Unable to resolve live physical register dependencies!");
}
}
cerr << "*** Scheduling failed! ***\n";
SuccSU->dump(this);
cerr << " has been released too many times!\n";
- llvm_unreachable();
+ llvm_unreachable(0);
}
#endif
cerr << "*** Scheduling failed! ***\n";
PredSU->dump(this);
cerr << " has been released too many times!\n";
- llvm_unreachable();
+ llvm_unreachable(0);
}
#endif
cerr << "*** Scheduling failed! ***\n";
SuccSU->dump(this);
cerr << " has been released too many times!\n";
- llvm_unreachable();
+ llvm_unreachable(0);
}
#endif
MI->addOperand(MachineOperand::CreateImm(SubIdx));
BB->insert(InsertPos, MI);
} else
- LLVM_UNREACHABLE("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
+ llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
SDValue Op(Node, 0);
bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
#ifndef NDEBUG
Node->dump(DAG);
#endif
- LLVM_UNREACHABLE("This target-independent node should have been selected!");
+ llvm_unreachable("This target-independent node should have been selected!");
break;
case ISD::EntryToken:
- LLVM_UNREACHABLE("EntryToken should have been excluded from the schedule!");
+ llvm_unreachable("EntryToken should have been excluded from the schedule!");
break;
case ISD::TokenFactor: // fall thru
break;
++i; // Skip the ID value.
switch (Flags & 7) {
- default: LLVM_UNREACHABLE("Bad flags!");
+ default: llvm_unreachable("Bad flags!");
case 2: // Def of register.
for (; NumVals; --NumVals, ++i) {
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
static const fltSemantics *MVTToAPFloatSemantics(MVT VT) {
switch (VT.getSimpleVT()) {
- default: LLVM_UNREACHABLE("Unknown FP format");
+ default: llvm_unreachable("Unknown FP format");
case MVT::f32: return &APFloat::IEEEsingle;
case MVT::f64: return &APFloat::IEEEdouble;
case MVT::f80: return &APFloat::x87DoubleExtended;
/// if the operation does not depend on the sign of the input (setne and seteq).
static int isSignedOp(ISD::CondCode Opcode) {
switch (Opcode) {
- default: LLVM_UNREACHABLE("Illegal integer setcc operation!");
+ default: llvm_unreachable("Illegal integer setcc operation!");
case ISD::SETEQ:
case ISD::SETNE: return 0;
case ISD::SETLT:
switch (N->getOpcode()) {
case ISD::TargetExternalSymbol:
case ISD::ExternalSymbol:
- LLVM_UNREACHABLE("Should only be used on nodes with operands");
+ llvm_unreachable("Should only be used on nodes with operands");
default: break; // Normal nodes don't need extra info.
case ISD::ARG_FLAGS:
ID.AddInteger(cast<ARG_FLAGSSDNode>(N)->getArgFlags().getRawBits());
bool Erased = false;
switch (N->getOpcode()) {
case ISD::EntryToken:
- LLVM_UNREACHABLE("EntryToken should not be in CSEMaps!");
+ llvm_unreachable("EntryToken should not be in CSEMaps!");
return false;
case ISD::HANDLENODE: return false; // noop.
case ISD::CONDCODE:
!N->isMachineOpcode() && !doNotCSE(N)) {
N->dump(this);
cerr << "\n";
- LLVM_UNREACHABLE("Node is not in map!");
+ llvm_unreachable("Node is not in map!");
}
#endif
return Erased;
const APInt &C1 = N1C->getAPIntValue();
switch (Cond) {
- default: LLVM_UNREACHABLE("Unknown integer setcc!");
+ default: llvm_unreachable("Unknown integer setcc!");
case ISD::SETEQ: return getConstant(C1 == C2, VT);
case ISD::SETNE: return getConstant(C1 != C2, VT);
case ISD::SETULT: return getConstant(C1.ult(C2), VT);
case ISD::MERGE_VALUES:
case ISD::CONCAT_VECTORS:
return Operand; // Factor, merge or concat of one node? No need.
- case ISD::FP_ROUND: LLVM_UNREACHABLE("Invalid method to make FP_ROUND node");
+ case ISD::FP_ROUND: llvm_unreachable("Invalid method to make FP_ROUND node");
case ISD::FP_EXTEND:
assert(VT.isFloatingPoint() &&
Operand.getValueType().isFloatingPoint() && "Invalid FP cast!");
}
break;
case ISD::VECTOR_SHUFFLE:
- LLVM_UNREACHABLE("should use getVectorShuffle constructor!");
+ llvm_unreachable("should use getVectorShuffle constructor!");
break;
case ISD::BIT_CONVERT:
// Fold bit_convert nodes from a type to themselves.
SDVTList SelectionDAG::getVTList(const MVT *VTs, unsigned NumVTs) {
switch (NumVTs) {
- case 0: LLVM_UNREACHABLE("Cannot have nodes without results!");
+ case 0: llvm_unreachable("Cannot have nodes without results!");
case 1: return getVTList(VTs[0]);
case 2: return getVTList(VTs[0], VTs[1]);
case 3: return getVTList(VTs[0], VTs[1], VTs[2]);
case ISD::CONVERT_RNDSAT: {
switch (cast<CvtRndSatSDNode>(this)->getCvtCode()) {
- default: LLVM_UNREACHABLE("Unknown cvt code!");
+ default: llvm_unreachable("Unknown cvt code!");
case ISD::CVT_FF: return "cvt_ff";
case ISD::CVT_FS: return "cvt_fs";
case ISD::CVT_FU: return "cvt_fu";
case ISD::CONDCODE:
switch (cast<CondCodeSDNode>(this)->get()) {
- default: LLVM_UNREACHABLE("Unknown setcc condition!");
+ default: llvm_unreachable("Unknown setcc condition!");
case ISD::SETOEQ: return "setoeq";
case ISD::SETOGT: return "setogt";
case ISD::SETOGE: return "setoge";
if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
- LLVM_UNREACHABLE("Unknown mismatch!");
+ llvm_unreachable("Unknown mismatch!");
return SDValue();
}
ValueVT = MVT::getIntegerVT(NumParts * PartBits);
Val = DAG.getNode(ExtendKind, dl, ValueVT, Val);
} else {
- LLVM_UNREACHABLE("Unknown mismatch!");
+ llvm_unreachable("Unknown mismatch!");
}
} else if (PartBits == ValueVT.getSizeInBits()) {
// Different types of the same size.
ValueVT = MVT::getIntegerVT(NumParts * PartBits);
Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
} else {
- LLVM_UNREACHABLE("Unknown mismatch!");
+ llvm_unreachable("Unknown mismatch!");
}
}
// Note: this doesn't use InstVisitor, because it has to work with
// ConstantExpr's in addition to instructions.
switch (Opcode) {
- default: LLVM_UNREACHABLE("Unknown instruction type encountered!");
+ default: llvm_unreachable("Unknown instruction type encountered!");
// Build the switch statement using the Instruction.def file.
#define HANDLE_INST(NUM, OPCODE, CLASS) \
case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
default:
- LLVM_UNREACHABLE("Invalid FCmp predicate opcode!");
+ llvm_unreachable("Invalid FCmp predicate opcode!");
FOC = FPC = ISD::SETFALSE;
break;
}
case ICmpInst::ICMP_SGT: return ISD::SETGT;
case ICmpInst::ICMP_UGT: return ISD::SETUGT;
default:
- LLVM_UNREACHABLE("Invalid ICmp predicate opcode!");
+ llvm_unreachable("Invalid ICmp predicate opcode!");
return ISD::SETNE;
}
}
Condition = getFCmpCondCode(FC->getPredicate());
} else {
Condition = ISD::SETEQ; // silence warning.
- LLVM_UNREACHABLE("Unknown compare instruction");
+ llvm_unreachable("Unknown compare instruction");
}
CaseBlock CB(Condition, BOp->getOperand(0),
case Intrinsic::gcread:
case Intrinsic::gcwrite:
- LLVM_UNREACHABLE("GC failed to lower gcread/gcwrite intrinsics!");
+ llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
return 0;
case Intrinsic::flt_rounds: {
}
SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
- LLVM_UNREACHABLE("LowerOperation not implemented for this target!");
+ llvm_unreachable("LowerOperation not implemented for this target!");
return SDValue();
}
void visitVACopy(CallInst &I);
void visitUserOp1(Instruction &I) {
- LLVM_UNREACHABLE("UserOp1 should not exist at instruction selection time!");
+ llvm_unreachable("UserOp1 should not exist at instruction selection time!");
}
void visitUserOp2(Instruction &I) {
- LLVM_UNREACHABLE("UserOp2 should not exist at instruction selection time!");
+ llvm_unreachable("UserOp2 should not exist at instruction selection time!");
}
const char *implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op);
"'usesCustomDAGSchedInserter', it must implement "
"TargetLowering::EmitInstrWithCustomInserter!";
#endif
- llvm_unreachable();
+ llvm_unreachable(0);
return 0;
}
if (EnableFastISelAbort)
// The "fast" selector couldn't handle something and bailed.
// For the purpose of debugging, just abort.
- LLVM_UNREACHABLE("FastISel didn't select the entire block");
+ llvm_unreachable("FastISel didn't select the entire block");
}
break;
}
if (CFP->getValueAPF().isNaN()) {
// If an operand is known to be a nan, we can fold it.
switch (ISD::getUnorderedFlavor(Cond)) {
- default: LLVM_UNREACHABLE("Unknown flavor!");
+ default: llvm_unreachable("Unknown flavor!");
case 0: // Known false.
return DAG.getConstant(0, VT);
case 1: // Known true.
SDValue Temp;
if (N0.getValueType() == MVT::i1 && foldBooleans) {
switch (Cond) {
- default: LLVM_UNREACHABLE("Unknown integer setcc!");
+ default: llvm_unreachable("Unknown integer setcc!");
case ISD::SETEQ: // X == Y -> ~(X^Y)
Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
N0 = DAG.getNOT(dl, Temp, MVT::i1);
/// is.
static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
switch (CT) {
- default: LLVM_UNREACHABLE("Unknown constraint type!");
+ default: llvm_unreachable("Unknown constraint type!");
case TargetLowering::C_Other:
case TargetLowering::C_Unknown:
return 0;
DstSubIdx = CopyMI->getOperand(3).getImm();
SrcReg = CopyMI->getOperand(2).getReg();
} else if (!tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)){
- LLVM_UNREACHABLE("Unrecognized copy instruction!");
+ llvm_unreachable("Unrecognized copy instruction!");
}
// If they are already joined we continue.
*tri_->getSuperRegisters(LHS.reg))
// Imprecise sub-register information. Can't handle it.
return false;
- LLVM_UNREACHABLE("No copies from the RHS?");
+ llvm_unreachable("No copies from the RHS?");
} else {
LHSValNo = EliminatedLHSVals[0];
}
// Unfold current MI.
SmallVector<MachineInstr*, 4> NewMIs;
if (!TII->unfoldMemoryOperand(MF, &MI, VirtReg, false, false, NewMIs))
- LLVM_UNREACHABLE("Unable unfold the load / store folding instruction!");
+ llvm_unreachable("Unable unfold the load / store folding instruction!");
assert(NewMIs.size() == 1);
AssignPhysToVirtReg(NewMIs[0], VirtReg, PhysReg);
VRM.transferRestorePts(&MI, NewMIs[0]);
NextMII = next(NextMII);
NewMIs.clear();
if (!TII->unfoldMemoryOperand(MF, &NextMI, VirtReg, false, false, NewMIs))
- LLVM_UNREACHABLE("Unable unfold the load / store folding instruction!");
+ llvm_unreachable("Unable unfold the load / store folding instruction!");
assert(NewMIs.size() == 1);
AssignPhysToVirtReg(NewMIs[0], VirtReg, PhysReg);
VRM.transferRestorePts(&NextMI, NewMIs[0]);
assert(RC && "Unable to determine register class!");
int SS = VRM.getEmergencySpillSlot(RC);
if (UsedSS.count(SS))
- LLVM_UNREACHABLE("Need to spill more than one physical registers!");
+ llvm_unreachable("Need to spill more than one physical registers!");
UsedSS.insert(SS);
TII->storeRegToStackSlot(MBB, MII, PhysReg, true, SS, RC);
MachineInstr *StoreMI = prior(MII);
llvm::VirtRegRewriter* llvm::createVirtRegRewriter() {
switch (RewriterOpt) {
- default: LLVM_UNREACHABLE("Unreachable!");
+ default: llvm_unreachable("Unreachable!");
case local:
return new LocalRewriter();
case trivial:
const_cast<GlobalVariable *>(dyn_cast<GlobalVariable>(GV)))
EmitGlobalVariable(GVar);
else
- LLVM_UNREACHABLE("Global hasn't had an address allocated yet!");
+ llvm_unreachable("Global hasn't had an address allocated yet!");
return state.getGlobalAddressMap(locked)[GV];
}
GenericValue GV = getConstantValue(Op0);
const Type* DestTy = CE->getType();
switch (Op0->getType()->getTypeID()) {
- default: LLVM_UNREACHABLE("Invalid bitcast operand");
+ default: llvm_unreachable("Invalid bitcast operand");
case Type::IntegerTyID:
assert(DestTy->isFloatingPoint() && "invalid bitcast");
if (DestTy == Type::FloatTy)
GenericValue RHS = getConstantValue(CE->getOperand(1));
GenericValue GV;
switch (CE->getOperand(0)->getType()->getTypeID()) {
- default: LLVM_UNREACHABLE("Bad add type!");
+ default: llvm_unreachable("Bad add type!");
case Type::IntegerTyID:
switch (CE->getOpcode()) {
- default: LLVM_UNREACHABLE("Invalid integer opcode");
+ default: llvm_unreachable("Invalid integer opcode");
case Instruction::Add: GV.IntVal = LHS.IntVal + RHS.IntVal; break;
case Instruction::Sub: GV.IntVal = LHS.IntVal - RHS.IntVal; break;
case Instruction::Mul: GV.IntVal = LHS.IntVal * RHS.IntVal; break;
break;
case Type::FloatTyID:
switch (CE->getOpcode()) {
- default: LLVM_UNREACHABLE("Invalid float opcode");
+ default: llvm_unreachable("Invalid float opcode");
case Instruction::FAdd:
GV.FloatVal = LHS.FloatVal + RHS.FloatVal; break;
case Instruction::FSub:
break;
case Type::DoubleTyID:
switch (CE->getOpcode()) {
- default: LLVM_UNREACHABLE("Invalid double opcode");
+ default: llvm_unreachable("Invalid double opcode");
case Instruction::FAdd:
GV.DoubleVal = LHS.DoubleVal + RHS.DoubleVal; break;
case Instruction::FSub:
case Type::FP128TyID: {
APFloat apfLHS = APFloat(LHS.IntVal);
switch (CE->getOpcode()) {
- default: LLVM_UNREACHABLE("Invalid long double opcode");llvm_unreachable();
+ default: llvm_unreachable("Invalid long double opcode");llvm_unreachable(0);
case Instruction::FAdd:
apfLHS.add(APFloat(RHS.IntVal), APFloat::rmNearestTiesToEven);
GV.IntVal = apfLHS.bitcastToAPInt();
else if (const GlobalVariable* GV = dyn_cast<GlobalVariable>(C))
Result = PTOGV(getOrEmitGlobalVariable(const_cast<GlobalVariable*>(GV)));
else
- LLVM_UNREACHABLE("Unknown constant pointer type!");
+ llvm_unreachable("Unknown constant pointer type!");
break;
default:
std::string msg;
}
cerr << "Bad Type: " << *Init->getType() << "\n";
- LLVM_UNREACHABLE("Unknown constant type to initialize memory with!");
+ llvm_unreachable("Unknown constant type to initialize memory with!");
}
/// EmitGlobals - Emit all of the global variables to memory, storing their
GenVal->DoubleVal = N;
break;
default:
- LLVM_UNREACHABLE("LLVMGenericValueToFloat supports only float and double.");
+ llvm_unreachable("LLVMGenericValueToFloat supports only float and double.");
}
return wrap(GenVal);
}
case Type::DoubleTyID:
return unwrap(GenVal)->DoubleVal;
default:
- LLVM_UNREACHABLE("LLVMGenericValueToFloat supports only float and double.");
+ llvm_unreachable("LLVMGenericValueToFloat supports only float and double.");
break;
}
return 0; // Not reached
IMPLEMENT_BINARY_OPERATOR(+, Double);
default:
cerr << "Unhandled type for FAdd instruction: " << *Ty << "\n";
- llvm_unreachable();
+ llvm_unreachable(0);
}
}
IMPLEMENT_BINARY_OPERATOR(-, Double);
default:
cerr << "Unhandled type for FSub instruction: " << *Ty << "\n";
- llvm_unreachable();
+ llvm_unreachable(0);
}
}
IMPLEMENT_BINARY_OPERATOR(*, Double);
default:
cerr << "Unhandled type for FMul instruction: " << *Ty << "\n";
- llvm_unreachable();
+ llvm_unreachable(0);
}
}
IMPLEMENT_BINARY_OPERATOR(/, Double);
default:
cerr << "Unhandled type for FDiv instruction: " << *Ty << "\n";
- llvm_unreachable();
+ llvm_unreachable(0);
}
}
break;
default:
cerr << "Unhandled type for Rem instruction: " << *Ty << "\n";
- llvm_unreachable();
+ llvm_unreachable(0);
}
}
IMPLEMENT_POINTER_ICMP(==);
default:
cerr << "Unhandled type for ICMP_EQ predicate: " << *Ty << "\n";
- llvm_unreachable();
+ llvm_unreachable(0);
}
return Dest;
}
IMPLEMENT_POINTER_ICMP(!=);
default:
cerr << "Unhandled type for ICMP_NE predicate: " << *Ty << "\n";
- llvm_unreachable();
+ llvm_unreachable(0);
}
return Dest;
}
IMPLEMENT_POINTER_ICMP(<);
default:
cerr << "Unhandled type for ICMP_ULT predicate: " << *Ty << "\n";
- llvm_unreachable();
+ llvm_unreachable(0);
}
return Dest;
}
IMPLEMENT_POINTER_ICMP(<);
default:
cerr << "Unhandled type for ICMP_SLT predicate: " << *Ty << "\n";
- llvm_unreachable();
+ llvm_unreachable(0);
}
return Dest;
}
IMPLEMENT_POINTER_ICMP(>);
default:
cerr << "Unhandled type for ICMP_UGT predicate: " << *Ty << "\n";
- llvm_unreachable();
+ llvm_unreachable(0);
}
return Dest;
}
IMPLEMENT_POINTER_ICMP(>);
default:
cerr << "Unhandled type for ICMP_SGT predicate: " << *Ty << "\n";
- llvm_unreachable();
+ llvm_unreachable(0);
}
return Dest;
}
IMPLEMENT_POINTER_ICMP(<=);
default:
cerr << "Unhandled type for ICMP_ULE predicate: " << *Ty << "\n";
- llvm_unreachable();
+ llvm_unreachable(0);
}
return Dest;
}
IMPLEMENT_POINTER_ICMP(<=);
default:
cerr << "Unhandled type for ICMP_SLE predicate: " << *Ty << "\n";
- llvm_unreachable();
+ llvm_unreachable(0);
}
return Dest;
}
IMPLEMENT_POINTER_ICMP(>=);
default:
cerr << "Unhandled type for ICMP_UGE predicate: " << *Ty << "\n";
- llvm_unreachable();
+ llvm_unreachable(0);
}
return Dest;
}
IMPLEMENT_POINTER_ICMP(>=);
default:
cerr << "Unhandled type for ICMP_SGE predicate: " << *Ty << "\n";
- llvm_unreachable();
+ llvm_unreachable(0);
}
return Dest;
}
case ICmpInst::ICMP_SGE: R = executeICMP_SGE(Src1, Src2, Ty); break;
default:
cerr << "Don't know how to handle this ICmp predicate!\n-->" << I;
- llvm_unreachable();
+ llvm_unreachable(0);
}
SetValue(&I, R, SF);
IMPLEMENT_FCMP(==, Double);
default:
cerr << "Unhandled type for FCmp EQ instruction: " << *Ty << "\n";
- llvm_unreachable();
+ llvm_unreachable(0);
}
return Dest;
}
default:
cerr << "Unhandled type for FCmp NE instruction: " << *Ty << "\n";
- llvm_unreachable();
+ llvm_unreachable(0);
}
return Dest;
}
IMPLEMENT_FCMP(<=, Double);
default:
cerr << "Unhandled type for FCmp LE instruction: " << *Ty << "\n";
- llvm_unreachable();
+ llvm_unreachable(0);
}
return Dest;
}
IMPLEMENT_FCMP(>=, Double);
default:
cerr << "Unhandled type for FCmp GE instruction: " << *Ty << "\n";
- llvm_unreachable();
+ llvm_unreachable(0);
}
return Dest;
}
IMPLEMENT_FCMP(<, Double);
default:
cerr << "Unhandled type for FCmp LT instruction: " << *Ty << "\n";
- llvm_unreachable();
+ llvm_unreachable(0);
}
return Dest;
}
IMPLEMENT_FCMP(>, Double);
default:
cerr << "Unhandled type for FCmp GT instruction: " << *Ty << "\n";
- llvm_unreachable();
+ llvm_unreachable(0);
}
return Dest;
}
case FCmpInst::FCMP_OGE: R = executeFCMP_OGE(Src1, Src2, Ty); break;
default:
cerr << "Don't know how to handle this FCmp predicate!\n-->" << I;
- llvm_unreachable();
+ llvm_unreachable(0);
}
SetValue(&I, R, SF);
}
default:
cerr << "Unhandled Cmp predicate\n";
- llvm_unreachable();
+ llvm_unreachable(0);
}
}
case Instruction::Xor: R.IntVal = Src1.IntVal ^ Src2.IntVal; break;
default:
cerr << "Don't know how to handle this binary operator!\n-->" << I;
- llvm_unreachable();
+ llvm_unreachable(0);
}
SetValue(&I, R, SF);
} else if (SrcTy->isInteger()) {
Dest.IntVal = Src.IntVal;
} else
- LLVM_UNREACHABLE("Invalid BitCast");
+ llvm_unreachable("Invalid BitCast");
} else if (DstTy == Type::FloatTy) {
if (SrcTy->isInteger())
Dest.FloatVal = Src.IntVal.bitsToFloat();
else
Dest.DoubleVal = Src.DoubleVal;
} else
- LLVM_UNREACHABLE("Invalid Bitcast");
+ llvm_unreachable("Invalid Bitcast");
return Dest;
}
IMPLEMENT_VAARG(Double);
default:
cerr << "Unhandled dest type for vaarg instruction: " << *Ty << "\n";
- llvm_unreachable();
+ llvm_unreachable(0);
}
// Set the Value of this Instruction.
break;
default:
cerr << "Unhandled ConstantExpr: " << *CE << "\n";
- llvm_unreachable();
+ llvm_unreachable(0);
return GenericValue();
}
return Dest;
DOUT << " --> ";
const GenericValue &Val = SF.Values[&I];
switch (I.getType()->getTypeID()) {
- default: LLVM_UNREACHABLE("Invalid GenericValue Type");
+ default: llvm_unreachable("Invalid GenericValue Type");
case Type::VoidTyID: DOUT << "void"; break;
case Type::FloatTyID: DOUT << "float " << Val.FloatVal; break;
case Type::DoubleTyID: DOUT << "double " << Val.DoubleVal; break;
void visitStoreInst(StoreInst &I);
void visitGetElementPtrInst(GetElementPtrInst &I);
void visitPHINode(PHINode &PN) {
- LLVM_UNREACHABLE("PHI nodes already handled!");
+ llvm_unreachable("PHI nodes already handled!");
}
void visitTruncInst(TruncInst &I);
void visitZExtInst(ZExtInst &I);
void visitVAArgInst(VAArgInst &I);
void visitInstruction(Instruction &I) {
cerr << I;
- LLVM_UNREACHABLE("Instruction not interpretable yet!");
+ llvm_unreachable("Instruction not interpretable yet!");
}
GenericValue callExternalFunction(Function *F,
if (ArgValues.empty()) {
GenericValue rv;
switch (RetTy->getTypeID()) {
- default: LLVM_UNREACHABLE("Unknown return type for function call!");
+ default: llvm_unreachable("Unknown return type for function call!");
case Type::IntegerTyID: {
unsigned BitWidth = cast<IntegerType>(RetTy)->getBitWidth();
if (BitWidth == 1)
else if (BitWidth <= 64)
rv.IntVal = APInt(BitWidth, ((int64_t(*)())(intptr_t)FPtr)());
else
- LLVM_UNREACHABLE("Integer types > 64 bits not supported");
+ llvm_unreachable("Integer types > 64 bits not supported");
return rv;
}
case Type::VoidTyID:
case Type::X86_FP80TyID:
case Type::FP128TyID:
case Type::PPC_FP128TyID:
- LLVM_UNREACHABLE("long double not supported yet");
+ llvm_unreachable("long double not supported yet");
return rv;
case Type::PointerTyID:
return PTOGV(((void*(*)())(intptr_t)FPtr)());
const Type *ArgTy = FTy->getParamType(i);
const GenericValue &AV = ArgValues[i];
switch (ArgTy->getTypeID()) {
- default: LLVM_UNREACHABLE("Unknown argument type for function call!");
+ default: llvm_unreachable("Unknown argument type for function call!");
case Type::IntegerTyID:
C = ConstantInt::get(AV.IntVal);
break;
JCE->emitULEB128Bytes(Offset);
} else {
- LLVM_UNREACHABLE("Machine move no supported yet.");
+ llvm_unreachable("Machine move no supported yet.");
}
} else if (Src.isReg() &&
Src.getReg() == MachineLocation::VirtualFP) {
JCE->emitByte(dwarf::DW_CFA_def_cfa_register);
JCE->emitULEB128Bytes(RI->getDwarfRegNum(Dst.getReg(), true));
} else {
- LLVM_UNREACHABLE("Machine move no supported yet.");
+ llvm_unreachable("Machine move no supported yet.");
}
} else {
unsigned Reg = RI->getDwarfRegNum(Src.getReg(), true);
FinalSize += TargetAsmInfo::getULEB128Size(Offset);
} else {
- LLVM_UNREACHABLE("Machine move no supported yet.");
+ llvm_unreachable("Machine move no supported yet.");
}
} else if (Src.isReg() &&
Src.getReg() == MachineLocation::VirtualFP) {
unsigned RegNum = RI->getDwarfRegNum(Dst.getReg(), true);
FinalSize += TargetAsmInfo::getULEB128Size(RegNum);
} else {
- LLVM_UNREACHABLE("Machine move no supported yet.");
+ llvm_unreachable("Machine move no supported yet.");
}
} else {
unsigned Reg = RI->getDwarfRegNum(Src.getReg(), true);
std::string Magic;
Pathname.getMagicNumber(Magic, 64);
switch (sys::IdentifyFileType(Magic.c_str(), 64)) {
- default: LLVM_UNREACHABLE("Bad file type identification");
+ default: llvm_unreachable("Bad file type identification");
case sys::Unknown_FileType:
return warning("Supposed library '" + Lib + "' isn't a library.");
std::string Magic;
File.getMagicNumber(Magic, 64);
switch (sys::IdentifyFileType(Magic.c_str(), 64)) {
- default: LLVM_UNREACHABLE("Bad file type identification");
+ default: llvm_unreachable("Bad file type identification");
case sys::Unknown_FileType:
return warning("Ignoring file '" + File.toString() +
"' because does not contain bitcode.");
Result = CE->getWithOperands(Ops);
} else {
assert(!isa<GlobalValue>(CPV) && "Unmapped global?");
- LLVM_UNREACHABLE("Unknown type of derived type constant value!");
+ llvm_unreachable("Unknown type of derived type constant value!");
}
} else if (isa<InlineAsm>(In)) {
Result = const_cast<Value*>(In);
PrintMap(ValueMap);
cerr << "Couldn't remap value: " << (void*)In << " " << *In << "\n";
- LLVM_UNREACHABLE("Couldn't remap value!");
+ llvm_unreachable("Couldn't remap value!");
#endif
return 0;
}
// Nothing is required, mapped values will take the new global
// automatically.
} else if (DGVar->hasAppendingLinkage()) {
- LLVM_UNREACHABLE("Appending linkage unimplemented!");
+ llvm_unreachable("Appending linkage unimplemented!");
} else {
- LLVM_UNREACHABLE("Unknown linkage!");
+ llvm_unreachable("Unknown linkage!");
}
} else {
// Copy the initializer over now...
// Need target hooks to know how to print this.
switch (Size) {
default:
- LLVM_UNREACHABLE("Invalid size for machine code value!");
+ llvm_unreachable("Invalid size for machine code value!");
case 1: OS << ".byte"; break;
case 2: OS << ".short"; break;
case 4: OS << ".long"; break;
switch (ValueSize) {
default:
- LLVM_UNREACHABLE("Invalid size for machine code value!");
+ llvm_unreachable("Invalid size for machine code value!");
case 8:
- LLVM_UNREACHABLE("Unsupported alignment size!");
+ llvm_unreachable("Unsupported alignment size!");
case 1: OS << (IsPow2 ? ".p2align" : ".balign"); break;
case 2: OS << (IsPow2 ? ".p2alignw" : ".balignw"); break;
case 4: OS << (IsPow2 ? ".p2alignl" : ".balignl"); break;
switch (rounding_mode) {
default:
- llvm_unreachable();
+ llvm_unreachable(0);
case rmNearestTiesToAway:
return lost_fraction == lfExactlyHalf || lost_fraction == lfMoreThanHalf;
{
switch (convolve(category, rhs.category)) {
default:
- llvm_unreachable();
+ llvm_unreachable(0);
case convolve(fcNaN, fcZero):
case convolve(fcNaN, fcNormal):
{
switch (convolve(category, rhs.category)) {
default:
- llvm_unreachable();
+ llvm_unreachable(0);
case convolve(fcNaN, fcZero):
case convolve(fcNaN, fcNormal):
{
switch (convolve(category, rhs.category)) {
default:
- llvm_unreachable();
+ llvm_unreachable(0);
case convolve(fcNaN, fcZero):
case convolve(fcNaN, fcNormal):
{
switch (convolve(category, rhs.category)) {
default:
- llvm_unreachable();
+ llvm_unreachable(0);
case convolve(fcNaN, fcZero):
case convolve(fcNaN, fcNormal):
switch (convolve(category, rhs.category)) {
default:
- llvm_unreachable();
+ llvm_unreachable(0);
case convolve(fcNaN, fcZero):
case convolve(fcNaN, fcNormal):
else if (api.getBitWidth()==128 && !isIEEE)
return initFromPPCDoubleDoubleAPInt(api);
else
- llvm_unreachable();
+ llvm_unreachable(0);
}
APFloat::APFloat(const APInt& api, bool isIEEE)
else
return x_old + 1;
} else
- LLVM_UNREACHABLE("Error in APInt::sqrt computation");
+ llvm_unreachable("Error in APInt::sqrt computation");
return x_old + 1;
}
char cdigit = str[i];
if (radix == 16) {
if (!isxdigit(cdigit))
- LLVM_UNREACHABLE("Invalid hex digit in string");
+ llvm_unreachable("Invalid hex digit in string");
if (isdigit(cdigit))
digit = cdigit - '0';
else if (cdigit >= 'a')
else if (cdigit >= 'A')
digit = cdigit - 'A' + 10;
else
- LLVM_UNREACHABLE("huh? we shouldn't get here");
+ llvm_unreachable("huh? we shouldn't get here");
} else if (isdigit(cdigit)) {
digit = cdigit - '0';
assert((radix == 10 ||
(radix == 2 && (digit == 0 || digit == 1))) &&
"Invalid digit in string for given radix");
} else {
- LLVM_UNREACHABLE("Invalid character in digit string");
+ llvm_unreachable("Invalid character in digit string");
}
// Shift or multiply the value by the radix
cerr << ProgramName
<< ": Bad ValueMask flag! CommandLine usage error:"
<< Handler->getValueExpectedFlag() << "\n";
- llvm_unreachable();
+ llvm_unreachable(0);
}
// If this isn't a multi-arg option, just run the handler.
ValNo++;
break;
default:
- LLVM_UNREACHABLE("Internal error, unexpected NumOccurrences flag in "
+ llvm_unreachable("Internal error, unexpected NumOccurrences flag in "
"positional argument processing!");
}
}
case DW_TAG_lo_user: return "DW_TAG_lo_user";
case DW_TAG_hi_user: return "DW_TAG_hi_user";
}
- LLVM_UNREACHABLE("Unknown Dwarf Tag");
+ llvm_unreachable("Unknown Dwarf Tag");
return "";
}
case DW_CHILDREN_no: return "CHILDREN_no";
case DW_CHILDREN_yes: return "CHILDREN_yes";
}
- LLVM_UNREACHABLE("Unknown Dwarf ChildrenFlag");
+ llvm_unreachable("Unknown Dwarf ChildrenFlag");
return "";
}
case DW_AT_APPLE_major_runtime_vers: return "DW_AT_APPLE_major_runtime_vers";
case DW_AT_APPLE_runtime_class: return "DW_AT_APPLE_runtime_class";
}
- LLVM_UNREACHABLE("Unknown Dwarf Attribute");
+ llvm_unreachable("Unknown Dwarf Attribute");
return "";
}
case DW_FORM_ref_udata: return "FORM_ref_udata";
case DW_FORM_indirect: return "FORM_indirect";
}
- LLVM_UNREACHABLE("Unknown Dwarf Form Encoding");
+ llvm_unreachable("Unknown Dwarf Form Encoding");
return "";
}
case DW_OP_lo_user: return "OP_lo_user";
case DW_OP_hi_user: return "OP_hi_user";
}
- LLVM_UNREACHABLE("Unknown Dwarf Operation Encoding");
+ llvm_unreachable("Unknown Dwarf Operation Encoding");
return "";
}
case DW_ATE_lo_user: return "ATE_lo_user";
case DW_ATE_hi_user: return "ATE_hi_user";
}
- LLVM_UNREACHABLE("Unknown Dwarf Attribute Encoding");
+ llvm_unreachable("Unknown Dwarf Attribute Encoding");
return "";
}
case DW_DS_leading_separate: return "DS_leading_separate";
case DW_DS_trailing_separate: return "DS_trailing_separate";
}
- LLVM_UNREACHABLE("Unknown Dwarf Decimal Sign Attribute");
+ llvm_unreachable("Unknown Dwarf Decimal Sign Attribute");
return "";
}
case DW_END_lo_user: return "END_lo_user";
case DW_END_hi_user: return "END_hi_user";
}
- LLVM_UNREACHABLE("Unknown Dwarf Endianity");
+ llvm_unreachable("Unknown Dwarf Endianity");
return "";
}
case DW_ACCESS_protected: return "ACCESS_protected";
case DW_ACCESS_private: return "ACCESS_private";
}
- LLVM_UNREACHABLE("Unknown Dwarf Accessibility");
+ llvm_unreachable("Unknown Dwarf Accessibility");
return "";
}
case DW_VIS_exported: return "VIS_exported";
case DW_VIS_qualified: return "VIS_qualified";
}
- LLVM_UNREACHABLE("Unknown Dwarf Visibility");
+ llvm_unreachable("Unknown Dwarf Visibility");
return "";
}
case DW_VIRTUALITY_virtual: return "VIRTUALITY_virtual";
case DW_VIRTUALITY_pure_virtual: return "VIRTUALITY_pure_virtual";
}
- LLVM_UNREACHABLE("Unknown Dwarf Virtuality");
+ llvm_unreachable("Unknown Dwarf Virtuality");
return "";
}
case DW_LANG_lo_user: return "LANG_lo_user";
case DW_LANG_hi_user: return "LANG_hi_user";
}
- LLVM_UNREACHABLE("Unknown Dwarf Language");
+ llvm_unreachable("Unknown Dwarf Language");
return "";
}
case DW_ID_down_case: return "ID_down_case";
case DW_ID_case_insensitive: return "ID_case_insensitive";
}
- LLVM_UNREACHABLE("Unknown Dwarf Identifier Case");
+ llvm_unreachable("Unknown Dwarf Identifier Case");
return "";
}
case DW_CC_lo_user: return "CC_lo_user";
case DW_CC_hi_user: return "CC_hi_user";
}
- LLVM_UNREACHABLE("Unknown Dwarf Calling Convention");
+ llvm_unreachable("Unknown Dwarf Calling Convention");
return "";
}
case DW_INL_declared_not_inlined: return "INL_declared_not_inlined";
case DW_INL_declared_inlined: return "INL_declared_inlined";
}
- LLVM_UNREACHABLE("Unknown Dwarf Inline Code");
+ llvm_unreachable("Unknown Dwarf Inline Code");
return "";
}
case DW_ORD_row_major: return "ORD_row_major";
case DW_ORD_col_major: return "ORD_col_major";
}
- LLVM_UNREACHABLE("Unknown Dwarf Array Order");
+ llvm_unreachable("Unknown Dwarf Array Order");
return "";
}
case DW_DSC_label: return "DSC_label";
case DW_DSC_range: return "DSC_range";
}
- LLVM_UNREACHABLE("Unknown Dwarf Discriminant Descriptor");
+ llvm_unreachable("Unknown Dwarf Discriminant Descriptor");
return "";
}
case DW_LNS_set_epilogue_begin: return "LNS_set_epilogue_begin";
case DW_LNS_set_isa: return "LNS_set_isa";
}
- LLVM_UNREACHABLE("Unknown Dwarf Line Number Standard");
+ llvm_unreachable("Unknown Dwarf Line Number Standard");
return "";
}
case DW_LNE_lo_user: return "LNE_lo_user";
case DW_LNE_hi_user: return "LNE_hi_user";
}
- LLVM_UNREACHABLE("Unknown Dwarf Line Number Extended Opcode Encoding");
+ llvm_unreachable("Unknown Dwarf Line Number Extended Opcode Encoding");
return "";
}
case DW_MACINFO_end_file: return "MACINFO_end_file";
case DW_MACINFO_vendor_ext: return "MACINFO_vendor_ext";
}
- LLVM_UNREACHABLE("Unknown Dwarf Macinfo Type Encodings");
+ llvm_unreachable("Unknown Dwarf Macinfo Type Encodings");
return "";
}
case DW_CFA_lo_user: return "CFA_lo_user";
case DW_CFA_hi_user: return "CFA_hi_user";
}
- LLVM_UNREACHABLE("Unknown Dwarf Call Frame Instruction Encodings");
+ llvm_unreachable("Unknown Dwarf Call Frame Instruction Encodings");
return "";
}
exit(1);
}
-void llvm_unreachable(const char *msg, const char *file, unsigned line) {
+void llvm_unreachable_internal(const char *msg, const char *file, unsigned line) {
if (msg)
errs() << msg << "\n";
errs() << "UNREACHABLE executed";
else if (sizeof(long) == sizeof(long long)) {
AddInteger((unsigned long long)I);
} else {
- LLVM_UNREACHABLE("unexpected sizeof(long)");
+ llvm_unreachable("unexpected sizeof(long)");
}
}
void FoldingSetNodeID::AddInteger(long long I) {
inline static CondCodes getOppositeCondition(CondCodes CC){
switch (CC) {
- default: LLVM_UNREACHABLE("Unknown condition code");
+ default: llvm_unreachable("Unknown condition code");
case EQ: return NE;
case NE: return EQ;
case HS: return LO;
inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
switch (CC) {
- default: LLVM_UNREACHABLE("Unknown condition code");
+ default: llvm_unreachable("Unknown condition code");
case ARMCC::EQ: return "eq";
case ARMCC::NE: return "ne";
case ARMCC::HS: return "hs";
static inline const char *getShiftOpcStr(ShiftOpc Op) {
switch (Op) {
- default: LLVM_UNREACHABLE("Unknown shift opc!");
+ default: llvm_unreachable("Unknown shift opc!");
case ARM_AM::asr: return "asr";
case ARM_AM::lsl: return "lsl";
case ARM_AM::lsr: return "lsr";
static inline const char *getAMSubModeStr(AMSubMode Mode) {
switch (Mode) {
- default: LLVM_UNREACHABLE("Unknown addressing sub-mode!");
+ default: llvm_unreachable("Unknown addressing sub-mode!");
case ARM_AM::ia: return "ia";
case ARM_AM::ib: return "ib";
case ARM_AM::da: return "da";
static inline const char *getAMSubModeAltStr(AMSubMode Mode, bool isLD) {
switch (Mode) {
- default: LLVM_UNREACHABLE("Unknown addressing sub-mode!");
+ default: llvm_unreachable("Unknown addressing sub-mode!");
case ARM_AM::ia: return isLD ? "fd" : "ea";
case ARM_AM::ib: return isLD ? "ed" : "fa";
case ARM_AM::da: return isLD ? "fa" : "ed";
return 0;
switch (MI->getOpcode()) {
default:
- LLVM_UNREACHABLE("Unknown or unset size field for instr!");
+ llvm_unreachable("Unknown or unset size field for instr!");
case TargetInstrInfo::IMPLICIT_DEF:
case TargetInstrInfo::DECLARE:
case TargetInstrInfo::DBG_LABEL:
case S30: return 30;
case S31: return 31;
default:
- LLVM_UNREACHABLE("Unknown ARM register!");
+ llvm_unreachable("Unknown ARM register!");
}
}
using namespace ARM;
switch (RegEnum) {
default:
- LLVM_UNREACHABLE("Unknown ARM register!");
+ llvm_unreachable("Unknown ARM register!");
case R0: case D0: return 0;
case R1: case D1: return 1;
case R2: case D2: return 2;
}
unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
- LLVM_UNREACHABLE("What is the exception register");
+ llvm_unreachable("What is the exception register");
return 0;
}
unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
- LLVM_UNREACHABLE("What is the exception handler register");
+ llvm_unreachable("What is the exception handler register");
return 0;
}
break;
}
default:
- LLVM_UNREACHABLE("Unsupported addressing mode!");
+ llvm_unreachable("Unsupported addressing mode!");
break;
}
template<class CodeEmitter>
unsigned Emitter<CodeEmitter>::getShiftOp(unsigned Imm) const {
switch (ARM_AM::getAM2ShiftOpc(Imm)) {
- default: LLVM_UNREACHABLE("Unknown shift opc!");
+ default: llvm_unreachable("Unknown shift opc!");
case ARM_AM::asr: return 2;
case ARM_AM::lsl: return 0;
case ARM_AM::lsr: return 1;
#ifndef NDEBUG
cerr << MO;
#endif
- llvm_unreachable();
+ llvm_unreachable(0);
}
return 0;
}
NumEmitted++; // Keep track of the # of mi's emitted
switch (MI.getDesc().TSFlags & ARMII::FormMask) {
default: {
- LLVM_UNREACHABLE("Unhandled instruction encoding format!");
+ llvm_unreachable("Unhandled instruction encoding format!");
break;
}
case ARMII::Pseudo:
else if (CFP->getType() == Type::DoubleTy)
emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
else {
- LLVM_UNREACHABLE("Unable to handle this constantpool entry!");
+ llvm_unreachable("Unable to handle this constantpool entry!");
}
} else {
- LLVM_UNREACHABLE("Unable to handle this constantpool entry!");
+ llvm_unreachable("Unable to handle this constantpool entry!");
}
}
}
unsigned Opcode = MI.getDesc().Opcode;
switch (Opcode) {
default:
- LLVM_UNREACHABLE("ARMCodeEmitter::emitPseudoInstruction");//FIXME:
+ llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");//FIXME:
case TargetInstrInfo::INLINEASM: {
// We allow inline assembler nodes with empty bodies - they can
// implicitly define registers, which is ok for JIT.
// ROR - 0111
// RRX - 0110 and bit[11:8] clear.
switch (SOpc) {
- default: LLVM_UNREACHABLE("Unknown shift opc!");
+ default: llvm_unreachable("Unknown shift opc!");
case ARM_AM::lsl: SBits = 0x1; break;
case ARM_AM::lsr: SBits = 0x3; break;
case ARM_AM::asr: SBits = 0x5; break;
// ASR - 100
// ROR - 110
switch (SOpc) {
- default: LLVM_UNREACHABLE("Unknown shift opc!");
+ default: llvm_unreachable("Unknown shift opc!");
case ARM_AM::lsl: SBits = 0x0; break;
case ARM_AM::lsr: SBits = 0x2; break;
case ARM_AM::asr: SBits = 0x4; break;
// DA - Decrement after - bit U = 0 and bit P = 0
// DB - Decrement before - bit U = 0 and bit P = 1
switch (Mode) {
- default: LLVM_UNREACHABLE("Unknown addressing sub-mode!");
+ default: llvm_unreachable("Unknown addressing sub-mode!");
case ARM_AM::da: break;
case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
const TargetInstrDesc &TID = MI.getDesc();
if (TID.Opcode == ARM::TPsoft) {
- LLVM_UNREACHABLE("ARM::TPsoft FIXME"); // FIXME
+ llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
}
// Part of binary is determined by TableGn.
Bits = 8; // Taking the address of a CP entry.
break;
}
- LLVM_UNREACHABLE("Unknown addressing mode for CP reference!");
+ llvm_unreachable("Unknown addressing mode for CP reference!");
case ARMII::AddrMode1: // AM1: 8 bits << 2
Bits = 8;
Scale = 4; // Taking the address of a CP entry.
/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
switch (CC) {
- default: LLVM_UNREACHABLE("Unknown condition code!");
+ default: llvm_unreachable("Unknown condition code!");
case ISD::SETNE: return ARMCC::NE;
case ISD::SETEQ: return ARMCC::EQ;
case ISD::SETGT: return ARMCC::GT;
bool Invert = false;
CondCode2 = ARMCC::AL;
switch (CC) {
- default: LLVM_UNREACHABLE("Unknown FP condition!");
+ default: llvm_unreachable("Unknown FP condition!");
case ISD::SETEQ:
case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
case ISD::SETGT:
bool Return) const {
switch (CC) {
default:
- LLVM_UNREACHABLE("Unsupported calling convention");
+ llvm_unreachable("Unsupported calling convention");
case CallingConv::C:
case CallingConv::Fast:
// Use target triple & subtarget features to do actual dispatch.
}
switch (VA.getLocInfo()) {
- default: LLVM_UNREACHABLE("Unknown loc info!");
+ default: llvm_unreachable("Unknown loc info!");
case CCValAssign::Full: break;
case CCValAssign::BCvt:
Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val);
// Promote the value if needed.
switch (VA.getLocInfo()) {
- default: LLVM_UNREACHABLE("Unknown loc info!");
+ default: llvm_unreachable("Unknown loc info!");
case CCValAssign::Full: break;
case CCValAssign::SExt:
Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
SDValue Arg = Op.getOperand(realRVLocIdx*2+1);
switch (VA.getLocInfo()) {
- default: LLVM_UNREACHABLE("Unknown loc info!");
+ default: llvm_unreachable("Unknown loc info!");
case CCValAssign::Full: break;
case CCValAssign::BCvt:
Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
// to 32 bits. Insert an assert[sz]ext to capture this, then
// truncate to the right size.
switch (VA.getLocInfo()) {
- default: LLVM_UNREACHABLE("Unknown loc info!");
+ default: llvm_unreachable("Unknown loc info!");
case CCValAssign::Full: break;
case CCValAssign::BCvt:
ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
if (Op.getOperand(1).getValueType().isFloatingPoint()) {
switch (SetCCOpcode) {
- default: LLVM_UNREACHABLE("Illegal FP comparison"); break;
+ default: llvm_unreachable("Illegal FP comparison"); break;
case ISD::SETUNE:
case ISD::SETNE: Invert = true; // Fallthrough
case ISD::SETOEQ:
} else {
// Integer comparisons.
switch (SetCCOpcode) {
- default: LLVM_UNREACHABLE("Illegal integer comparison"); break;
+ default: llvm_unreachable("Illegal integer comparison"); break;
case ISD::SETNE: Invert = true;
case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
case ISD::SETLT: Swap = true;
}
default:
- LLVM_UNREACHABLE("unexpected size for isVMOVSplat");
+ llvm_unreachable("unexpected size for isVMOVSplat");
break;
}
case 16: CanonicalVT = MVT::v4i16; break;
case 32: CanonicalVT = MVT::v2i32; break;
case 64: CanonicalVT = MVT::v1i64; break;
- default: LLVM_UNREACHABLE("unexpected splat element type"); break;
+ default: llvm_unreachable("unexpected splat element type"); break;
}
} else {
assert(VT.is128BitVector() && "unknown splat vector size");
case 16: CanonicalVT = MVT::v8i16; break;
case 32: CanonicalVT = MVT::v4i32; break;
case 64: CanonicalVT = MVT::v2i64; break;
- default: LLVM_UNREACHABLE("unexpected splat element type"); break;
+ default: llvm_unreachable("unexpected splat element type"); break;
}
}
SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
switch (Op.getOpcode()) {
- default: LLVM_UNREACHABLE("Don't know how to custom lower this!");
+ default: llvm_unreachable("Don't know how to custom lower this!");
case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
case ISD::GlobalAddress:
return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
SelectionDAG &DAG) {
switch (N->getOpcode()) {
default:
- LLVM_UNREACHABLE("Don't know how to custom expand this!");
+ llvm_unreachable("Don't know how to custom expand this!");
return;
case ISD::BIT_CONVERT:
Results.push_back(ExpandBIT_CONVERT(N, DAG));
case Intrinsic::arm_neon_vshiftlu:
if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
break;
- LLVM_UNREACHABLE("invalid shift count for vshll intrinsic");
+ llvm_unreachable("invalid shift count for vshll intrinsic");
case Intrinsic::arm_neon_vrshifts:
case Intrinsic::arm_neon_vrshiftu:
case Intrinsic::arm_neon_vqshiftsu:
if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
break;
- LLVM_UNREACHABLE("invalid shift count for vqshlu intrinsic");
+ llvm_unreachable("invalid shift count for vqshlu intrinsic");
case Intrinsic::arm_neon_vshiftn:
case Intrinsic::arm_neon_vrshiftn:
// Narrowing shifts require an immediate right shift.
if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
break;
- LLVM_UNREACHABLE("invalid shift count for narrowing vector shift intrinsic");
+ llvm_unreachable("invalid shift count for narrowing vector shift intrinsic");
default:
- LLVM_UNREACHABLE("unhandled vector shift");
+ llvm_unreachable("unhandled vector shift");
}
switch (IntNo) {
else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
VShiftOpc = ARMISD::VSRI;
else {
- LLVM_UNREACHABLE("invalid shift count for vsli/vsri intrinsic");
+ llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
}
return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
int64_t Cnt;
switch (N->getOpcode()) {
- default: LLVM_UNREACHABLE("unexpected shift opcode");
+ default: llvm_unreachable("unexpected shift opcode");
case ISD::SHL:
if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
unsigned Opc = 0;
switch (N->getOpcode()) {
- default: LLVM_UNREACHABLE("unexpected opcode");
+ default: llvm_unreachable("unexpected opcode");
case ISD::SIGN_EXTEND:
Opc = ARMISD::VGETLANEs;
break;
);
#else // Not an ARM host
void ARMCompilationCallback() {
- LLVM_UNREACHABLE("Cannot call ARMCompilationCallback() on a non-ARM arch!");
+ llvm_unreachable("Cannot call ARMCompilationCallback() on a non-ARM arch!");
}
#endif
}
// ldr pc, [pc,#-4]
// <addr>
if (!sys::Memory::setRangeWritable((void*)StubAddr, 8)) {
- LLVM_UNREACHABLE("ERROR: Unable to mark stub writable");
+ llvm_unreachable("ERROR: Unable to mark stub writable");
}
*(intptr_t *)StubAddr = 0xe51ff004; // ldr pc, [pc, #-4]
*(intptr_t *)(StubAddr+4) = NewVal;
if (!sys::Memory::setRangeExecutable((void*)StubAddr, 8)) {
- LLVM_UNREACHABLE("ERROR: Unable to mark stub executable");
+ llvm_unreachable("ERROR: Unable to mark stub executable");
}
}
case ARM::FSTD:
NumFSTMGened++;
return ARM::FSTMD;
- default: LLVM_UNREACHABLE("Unhandled opcode!");
+ default: llvm_unreachable("Unhandled opcode!");
}
return 0;
}
case ARM::t2STRi8:
case ARM::t2STRi12:
return ARM::t2STR_PRE;
- default: LLVM_UNREACHABLE("Unhandled opcode!");
+ default: llvm_unreachable("Unhandled opcode!");
}
return 0;
}
case ARM::t2STRi8:
case ARM::t2STRi12:
return ARM::t2STR_POST;
- default: LLVM_UNREACHABLE("Unhandled opcode!");
+ default: llvm_unreachable("Unhandled opcode!");
}
return 0;
}
// Print out labels for the function.
const Function *F = MF.getFunction();
switch (F->getLinkage()) {
- default: LLVM_UNREACHABLE("Unknown linkage type!");
+ default: llvm_unreachable("Unknown linkage type!");
case Function::PrivateLinkage:
case Function::InternalLinkage:
SwitchToTextSection("\t.text", F);
O << TRI->getAsmName(Reg);
}
} else
- LLVM_UNREACHABLE("not implemented");
+ llvm_unreachable("not implemented");
break;
}
case MachineOperand::MO_Immediate: {
case GlobalValue::InternalLinkage:
break;
default:
- LLVM_UNREACHABLE("Unknown linkage type!");
+ llvm_unreachable("Unknown linkage type!");
}
EmitAlignment(Align, GVar);
break;
}
default:
- LLVM_UNREACHABLE("Unsupported addressing mode!");
+ llvm_unreachable("Unsupported addressing mode!");
break;
}
case Alpha::R30 : case Alpha::F30 : return 30;
case Alpha::R31 : case Alpha::F31 : return 31;
default:
- LLVM_UNREACHABLE("Unhandled reg");
+ llvm_unreachable("Unhandled reg");
}
}
Offset = MI.getOperand(3).getImm();
break;
default:
- LLVM_UNREACHABLE("unknown relocatable instruction");
+ llvm_unreachable("unknown relocatable instruction");
}
if (MO.isGlobal())
MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
#ifndef NDEBUG
cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
#endif
- llvm_unreachable();
+ llvm_unreachable(0);
}
return rv;
bool rev = false;
bool inv = false;
switch(CC) {
- default: DEBUG(N->dump(CurDAG)); LLVM_UNREACHABLE("Unknown FP comparison!");
+ default: DEBUG(N->dump(CurDAG)); llvm_unreachable("Unknown FP comparison!");
case ISD::SETEQ: case ISD::SETOEQ: case ISD::SETUEQ:
Opc = Alpha::CMPTEQ; break;
case ISD::SETLT: case ISD::SETOLT: case ISD::SETULT:
} else if (TypeOperands[i] == MVT::f64) {
Opc = Alpha::STT;
} else
- LLVM_UNREACHABLE("Unknown operand");
+ llvm_unreachable("Unknown operand");
SDValue Ops[] = { CallOperands[i], getI64Imm((i - 6) * 8),
CurDAG->getCopyFromReg(Chain, dl, Alpha::R30, MVT::i64),
CallOperands[i], InFlag);
InFlag = Chain.getValue(1);
} else
- LLVM_UNREACHABLE("Unknown operand");
+ llvm_unreachable("Unknown operand");
}
// Finally, once everything is in registers to pass to the call, emit the
std::vector<SDValue> CallResults;
switch (N->getValueType(0).getSimpleVT()) {
- default: LLVM_UNREACHABLE("Unexpected ret value!");
+ default: llvm_unreachable("Unexpected ret value!");
case MVT::Other: break;
case MVT::i64:
Chain = CurDAG->getCopyFromReg(Chain, dl,
SDValue());
switch (Op.getNumOperands()) {
default:
- LLVM_UNREACHABLE("Do not know how to return this many arguments!");
+ llvm_unreachable("Do not know how to return this many arguments!");
case 1:
break;
//return SDValue(); // ret void is legal
for (unsigned i = 0, e = Args.size(); i != e; ++i)
{
switch (getValueType(Args[i].Ty).getSimpleVT()) {
- default: LLVM_UNREACHABLE("Unexpected ValueType for argument!");
+ default: llvm_unreachable("Unexpected ValueType for argument!");
case MVT::i1:
case MVT::i8:
case MVT::i16:
SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getDebugLoc();
switch (Op.getOpcode()) {
- default: LLVM_UNREACHABLE("Wasn't expecting to be able to lower this!");
+ default: llvm_unreachable("Wasn't expecting to be able to lower this!");
case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG,
VarArgsBase,
VarArgsOffset);
return Lo;
}
case ISD::GlobalTLSAddress:
- LLVM_UNREACHABLE("TLS not implemented for Alpha.");
+ llvm_unreachable("TLS not implemented for Alpha.");
case ISD::GlobalAddress: {
GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
GlobalValue *GV = GSDN->getGlobal();
.addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FrameIdx).addReg(Alpha::F31);
else
- LLVM_UNREACHABLE("Unhandled register class");
+ llvm_unreachable("Unhandled register class");
}
void AlphaInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
else if (RC == Alpha::GPRCRegisterClass)
Opc = Alpha::STQ;
else
- LLVM_UNREACHABLE("Unhandled register class");
+ llvm_unreachable("Unhandled register class");
DebugLoc DL = DebugLoc::getUnknownLoc();
MachineInstrBuilder MIB =
BuildMI(MF, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill));
BuildMI(MBB, MI, DL, get(Alpha::LDQ), DestReg)
.addFrameIndex(FrameIdx).addReg(Alpha::F31);
else
- LLVM_UNREACHABLE("Unhandled register class");
+ llvm_unreachable("Unhandled register class");
}
void AlphaInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
else if (RC == Alpha::GPRCRegisterClass)
Opc = Alpha::LDQ;
else
- LLVM_UNREACHABLE("Unhandled register class");
+ llvm_unreachable("Unhandled register class");
DebugLoc DL = DebugLoc::getUnknownLoc();
MachineInstrBuilder MIB =
BuildMI(MF, DL, get(Opc), DestReg);
case Alpha::FBLE: return Alpha::FBGT;
case Alpha::FBLT: return Alpha::FBGE;
default:
- LLVM_UNREACHABLE("Unknown opcode");
+ llvm_unreachable("Unknown opcode");
}
return 0; // Not reached
}
void AlphaJITInfo::replaceMachineCodeForFunction(void *Old, void *New) {
//FIXME
- llvm_unreachable();
+ llvm_unreachable(0);
}
static TargetJITInfo::JITCompilerFn JITCompilerFunction;
);
#else
void AlphaCompilationCallback() {
- LLVM_UNREACHABLE("Cannot call AlphaCompilationCallback() on a non-Alpha arch!");
+ llvm_unreachable("Cannot call AlphaCompilationCallback() on a non-Alpha arch!");
}
#endif
}
long idx = 0;
bool doCommon = true;
switch ((Alpha::RelocationType)MR->getRelocationType()) {
- default: LLVM_UNREACHABLE("Unknown relocation type!");
+ default: llvm_unreachable("Unknown relocation type!");
case Alpha::reloc_literal:
//This is a LDQl
idx = MR->getGOTIndex();
DOUT << "LDA: " << idx << "\n";
break;
default:
- LLVM_UNREACHABLE("Cannot handle gpdist yet");
+ llvm_unreachable("Cannot handle gpdist yet");
}
break;
case Alpha::reloc_bsr: {
}
unsigned AlphaRegisterInfo::getRARegister() const {
- LLVM_UNREACHABLE("What is the return address register");
+ llvm_unreachable("What is the return address register");
return 0;
}
}
unsigned AlphaRegisterInfo::getEHExceptionRegister() const {
- LLVM_UNREACHABLE("What is the exception register");
+ llvm_unreachable("What is the exception register");
return 0;
}
unsigned AlphaRegisterInfo::getEHHandlerRegister() const {
- LLVM_UNREACHABLE("What is the exception handler register");
+ llvm_unreachable("What is the exception handler register");
return 0;
}
int AlphaRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
- LLVM_UNREACHABLE("What is the dwarf register number");
+ llvm_unreachable("What is the dwarf register number");
return -1;
}
return;
case MachineOperand::MO_Immediate:
- LLVM_UNREACHABLE("printOp() does not handle immediate values");
+ llvm_unreachable("printOp() does not handle immediate values");
return;
case MachineOperand::MO_MachineBasicBlock:
EmitAlignment(MF.getAlignment(), F);
switch (F->getLinkage()) {
- default: LLVM_UNREACHABLE("Unknown linkage type!");
+ default: llvm_unreachable("Unknown linkage type!");
case Function::InternalLinkage: // Symbols default to internal.
case Function::PrivateLinkage:
break;
// Print the assembly for the instruction.
++EmittedInsts;
if (!printInstruction(II)) {
- LLVM_UNREACHABLE("Unhandled instruction in asm writer!");
+ llvm_unreachable("Unhandled instruction in asm writer!");
}
}
}
case GlobalValue::PrivateLinkage:
break;
default:
- LLVM_UNREACHABLE("Unknown linkage type!");
+ llvm_unreachable("Unknown linkage type!");
}
// 3: Type, Size, Align
void visitBranchInst(BranchInst &I);
void visitSwitchInst(SwitchInst &I);
void visitInvokeInst(InvokeInst &I) {
- LLVM_UNREACHABLE("Lowerinvoke pass didn't work!");
+ llvm_unreachable("Lowerinvoke pass didn't work!");
}
void visitUnwindInst(UnwindInst &I) {
- LLVM_UNREACHABLE("Lowerinvoke pass didn't work!");
+ llvm_unreachable("Lowerinvoke pass didn't work!");
}
void visitUnreachableInst(UnreachableInst &I);
#ifndef NDEBUG
cerr << "C Writer does not know about " << I;
#endif
- llvm_unreachable();
+ llvm_unreachable(0);
}
void outputLValue(Instruction *I) {
#ifndef NDEBUG
cerr << "Unknown primitive type: " << *Ty << "\n";
#endif
- llvm_unreachable();
+ llvm_unreachable(0);
}
}
#ifndef NDEBUG
cerr << "Unknown primitive type: " << *Ty << "\n";
#endif
- llvm_unreachable();
+ llvm_unreachable(0);
}
}
return Out << TyName << ' ' << NameSoFar;
}
default:
- LLVM_UNREACHABLE("Unhandled case in getTypeProps!");
+ llvm_unreachable("Unhandled case in getTypeProps!");
}
return Out;
return Out << TyName << ' ' << NameSoFar;
}
default:
- LLVM_UNREACHABLE("Unhandled case in getTypeProps!");
+ llvm_unreachable("Unhandled case in getTypeProps!");
}
return Out;
Out << ')';
break;
default:
- LLVM_UNREACHABLE("Invalid cast opcode");
+ llvm_unreachable("Invalid cast opcode");
}
// Print the source type cast
case Instruction::FPToUI:
break; // These don't need a source cast.
default:
- LLVM_UNREACHABLE("Invalid cast opcode");
+ llvm_unreachable("Invalid cast opcode");
break;
}
}
case ICmpInst::ICMP_UGT: Out << " > "; break;
case ICmpInst::ICMP_SGE:
case ICmpInst::ICMP_UGE: Out << " >= "; break;
- default: LLVM_UNREACHABLE("Illegal ICmp predicate");
+ default: llvm_unreachable("Illegal ICmp predicate");
}
break;
- default: LLVM_UNREACHABLE("Illegal opcode here!");
+ default: llvm_unreachable("Illegal opcode here!");
}
printConstantWithCast(CE->getOperand(1), CE->getOpcode());
if (NeedsClosingParens)
else {
const char* op = 0;
switch (CE->getPredicate()) {
- default: LLVM_UNREACHABLE("Illegal FCmp predicate");
+ default: llvm_unreachable("Illegal FCmp predicate");
case FCmpInst::FCMP_ORD: op = "ord"; break;
case FCmpInst::FCMP_UNO: op = "uno"; break;
case FCmpInst::FCMP_UEQ: op = "ueq"; break;
cerr << "CWriter Error: Unhandled constant expression: "
<< *CE << "\n";
#endif
- llvm_unreachable();
+ llvm_unreachable(0);
}
} else if (isa<UndefValue>(CPV) && CPV->getType()->isSingleValueType()) {
Out << "((";
#ifndef NDEBUG
cerr << "Unknown constant type: " << *CPV << "\n";
#endif
- llvm_unreachable();
+ llvm_unreachable(0);
}
}
<< "}; /* Long double constant */\n";
} else {
- LLVM_UNREACHABLE("Unknown float type!");
+ llvm_unreachable("Unknown float type!");
}
}
#ifndef NDEBUG
cerr << "Invalid operator type!" << I;
#endif
- llvm_unreachable();
+ llvm_unreachable(0);
}
writeOperandWithCast(I.getOperand(1), I.getOpcode());
#ifndef NDEBUG
cerr << "Invalid icmp predicate!" << I;
#endif
- llvm_unreachable();
+ llvm_unreachable(0);
}
writeOperandWithCast(I.getOperand(1), I);
const char* op = 0;
switch (I.getPredicate()) {
- default: LLVM_UNREACHABLE("Illegal FCmp predicate");
+ default: llvm_unreachable("Illegal FCmp predicate");
case FCmpInst::FCMP_ORD: op = "ord"; break;
case FCmpInst::FCMP_UNO: op = "uno"; break;
case FCmpInst::FCMP_UEQ: op = "ueq"; break;
static const char * getFloatBitCastField(const Type *Ty) {
switch (Ty->getTypeID()) {
- default: LLVM_UNREACHABLE("Invalid Type");
+ default: llvm_unreachable("Invalid Type");
case Type::FloatTyID: return "Float";
case Type::DoubleTyID: return "Double";
case Type::IntegerTyID: {
Out << ')';
// Multiple GCC builtins multiplex onto this intrinsic.
switch (cast<ConstantInt>(I.getOperand(3))->getZExtValue()) {
- default: LLVM_UNREACHABLE("Invalid llvm.x86.sse.cmp!");
+ default: llvm_unreachable("Invalid llvm.x86.sse.cmp!");
case 0: Out << "__builtin_ia32_cmpeq"; break;
case 1: Out << "__builtin_ia32_cmplt"; break;
case 2: Out << "__builtin_ia32_cmple"; break;
}
void CWriter::visitMallocInst(MallocInst &I) {
- LLVM_UNREACHABLE("lowerallocations pass didn't work!");
+ llvm_unreachable("lowerallocations pass didn't work!");
}
void CWriter::visitAllocaInst(AllocaInst &I) {
}
void CWriter::visitFreeInst(FreeInst &I) {
- LLVM_UNREACHABLE("lowerallocations pass didn't work!");
+ llvm_unreachable("lowerallocations pass didn't work!");
}
void CWriter::printGEPExpression(Value *Ptr, gep_type_iterator I,
&& "Invalid negated immediate rotate 7-bit argument");
O << -value;
} else {
- LLVM_UNREACHABLE("Invalid/non-immediate rotate amount in printRotateNeg7Imm");
+ llvm_unreachable("Invalid/non-immediate rotate amount in printRotateNeg7Imm");
}
}
&& "Invalid negated immediate rotate 7-bit argument");
O << -value;
} else {
- LLVM_UNREACHABLE("Invalid/non-immediate rotate amount in printRotateNeg7Imm");
+ llvm_unreachable("Invalid/non-immediate rotate amount in printRotateNeg7Imm");
}
}
EmitAlignment(MF.getAlignment(), F);
switch (F->getLinkage()) {
- default: LLVM_UNREACHABLE("Unknown linkage type!");
+ default: llvm_unreachable("Unknown linkage type!");
case Function::PrivateLinkage:
case Function::InternalLinkage: // Symbols default to internal.
break;
break;
case 'v': // not offsetable
#if 1
- LLVM_UNREACHABLE("InlineAsmMemoryOperand 'v' constraint not handled.");
+ llvm_unreachable("InlineAsmMemoryOperand 'v' constraint not handled.");
#else
SelectAddrIdxOnly(Op, Op, Op0, Op1);
#endif
}
}
- LLVM_UNREACHABLE("LowerConstantPool: Relocation model other than static"
+ llvm_unreachable("LowerConstantPool: Relocation model other than static"
" not supported.");
return SDValue();
}
}
}
- LLVM_UNREACHABLE("LowerJumpTable: Relocation model other than static"
+ llvm_unreachable("LowerJumpTable: Relocation model other than static"
" not supported.");
return SDValue();
}
PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
switch (Arg.getValueType().getSimpleVT()) {
- default: LLVM_UNREACHABLE("Unexpected ValueType for argument!");
+ default: llvm_unreachable("Unexpected ValueType for argument!");
case MVT::i8:
case MVT::i16:
case MVT::i32:
// If the call has results, copy the values out of the ret val registers.
switch (TheCall->getValueType(0).getSimpleVT()) {
- default: LLVM_UNREACHABLE("Unexpected ret value!");
+ default: llvm_unreachable("Unexpected ret value!");
case MVT::Other: break;
case MVT::i32:
if (TheCall->getValueType(1) == MVT::i32) {
} else if (EltVT == MVT::i64 || EltVT == MVT::f64) {
V2EltIdx0 = 2;
} else
- LLVM_UNREACHABLE("Unhandled vector type in LowerVECTOR_SHUFFLE");
+ llvm_unreachable("Unhandled vector type in LowerVECTOR_SHUFFLE");
for (unsigned i = 0; i != MaxElts; ++i) {
if (SVN->getMaskElt(i) < 0)
// Create a constant vector:
switch (Op.getValueType().getSimpleVT()) {
- default: LLVM_UNREACHABLE("Unexpected constant value type in "
+ default: llvm_unreachable("Unexpected constant value type in "
"LowerSCALAR_TO_VECTOR");
case MVT::v16i8: n_copies = 16; VT = MVT::i8; break;
case MVT::v8i16: n_copies = 8; VT = MVT::i16; break;
} else {
// Otherwise, copy the value from one register to another:
switch (Op0.getValueType().getSimpleVT()) {
- default: LLVM_UNREACHABLE("Unexpected value type in LowerSCALAR_TO_VECTOR");
+ default: llvm_unreachable("Unexpected value type in LowerSCALAR_TO_VECTOR");
case MVT::i8:
case MVT::i16:
case MVT::i32:
// sanity checks:
if (VT == MVT::i8 && EltNo >= 16)
- LLVM_UNREACHABLE("SPU LowerEXTRACT_VECTOR_ELT: i8 extraction slot > 15");
+ llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i8 extraction slot > 15");
else if (VT == MVT::i16 && EltNo >= 8)
- LLVM_UNREACHABLE("SPU LowerEXTRACT_VECTOR_ELT: i16 extraction slot > 7");
+ llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i16 extraction slot > 7");
else if (VT == MVT::i32 && EltNo >= 4)
- LLVM_UNREACHABLE("SPU LowerEXTRACT_VECTOR_ELT: i32 extraction slot > 4");
+ llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i32 extraction slot > 4");
else if (VT == MVT::i64 && EltNo >= 2)
- LLVM_UNREACHABLE("SPU LowerEXTRACT_VECTOR_ELT: i64 extraction slot > 2");
+ llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i64 extraction slot > 2");
if (EltNo == 0 && (VT == MVT::i32 || VT == MVT::i64)) {
// i32 and i64: Element 0 is the preferred slot
assert(Op.getValueType() == MVT::i8);
switch (Opc) {
default:
- LLVM_UNREACHABLE("Unhandled i8 math operator");
+ llvm_unreachable("Unhandled i8 math operator");
/*NOTREACHED*/
break;
case ISD::ADD: {
cerr << "*Op.getNode():\n";
Op.getNode()->dump();
#endif
- llvm_unreachable();
+ llvm_unreachable(0);
}
case ISD::LOAD:
case ISD::EXTLOAD:
} else if (RC == SPU::VECREGRegisterClass) {
opc = (isValidFrameIdx) ? SPU::STQDv16i8 : SPU::STQXv16i8;
} else {
- LLVM_UNREACHABLE("Unknown regclass!");
+ llvm_unreachable("Unknown regclass!");
}
DebugLoc DL = DebugLoc::getUnknownLoc();
} else if (RC == SPU::VECREGRegisterClass) {
/* Opc = PPC::STVX; */
} else {
- LLVM_UNREACHABLE("Unknown regclass!");
+ llvm_unreachable("Unknown regclass!");
}
DebugLoc DL = DebugLoc::getUnknownLoc();
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc))
} else if (RC == SPU::VECREGRegisterClass) {
opc = (isValidFrameIdx) ? SPU::LQDv16i8 : SPU::LQXv16i8;
} else {
- LLVM_UNREACHABLE("Unknown regclass in loadRegFromStackSlot!");
+ llvm_unreachable("Unknown regclass in loadRegFromStackSlot!");
}
DebugLoc DL = DebugLoc::getUnknownLoc();
} else if (RC == SPU::GPRCRegisterClass) {
/* Opc = something else! */
} else {
- LLVM_UNREACHABLE("Unknown regclass!");
+ llvm_unreachable("Unknown regclass!");
}
DebugLoc DL = DebugLoc::getUnknownLoc();
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
void CppWriter::printVisibilityType(GlobalValue::VisibilityTypes VisType) {
switch (VisType) {
- default: LLVM_UNREACHABLE("Unknown GVar visibility");
+ default: llvm_unreachable("Unknown GVar visibility");
case GlobalValue::DefaultVisibility:
Out << "GlobalValue::DefaultVisibility";
break;
printConstant(CE->getOperand(0));
Out << "Constant* " << constName << " = ConstantExpr::getCast(";
switch (CE->getOpcode()) {
- default: LLVM_UNREACHABLE("Invalid cast opcode");
+ default: llvm_unreachable("Invalid cast opcode");
case Instruction::Trunc: Out << "Instruction::Trunc"; break;
case Instruction::ZExt: Out << "Instruction::ZExt"; break;
case Instruction::SExt: Out << "Instruction::SExt"; break;
ConstDataCoalSection:
MergeableConstSection(cast<GlobalVariable>(GV)));
default:
- LLVM_UNREACHABLE("Unsuported section kind for global");
+ llvm_unreachable("Unsuported section kind for global");
}
// FIXME: Do we have any extra special weird cases?
std::string
DarwinTargetAsmInfo::UniqueSectionForGlobal(const GlobalValue* GV,
SectionKind::Kind kind) const {
- LLVM_UNREACHABLE("Darwin does not use unique sections");
+ llvm_unreachable("Darwin does not use unique sections");
return "";
}
if (const Function *F = dyn_cast<Function>(GV)) {
switch (F->getLinkage()) {
- default: LLVM_UNREACHABLE("Unknown linkage type!");
+ default: llvm_unreachable("Unknown linkage type!");
case Function::PrivateLinkage:
case Function::InternalLinkage:
case Function::DLLExportLinkage:
case SectionKind::ThreadBSS:
return TLSBSSSection;
default:
- LLVM_UNREACHABLE("Unsuported section kind for global");
+ llvm_unreachable("Unsuported section kind for global");
}
}
} else
- LLVM_UNREACHABLE("Unsupported global");
+ llvm_unreachable("Unsupported global");
return NULL;
}
case GlobalValue::PrivateLinkage:
break;
case GlobalValue::GhostLinkage:
- LLVM_UNREACHABLE("GhostLinkage cannot appear in IA64AsmPrinter!");
+ llvm_unreachable("GhostLinkage cannot appear in IA64AsmPrinter!");
case GlobalValue::DLLImportLinkage:
- LLVM_UNREACHABLE("DLLImport linkage is not supported by this target!");
+ llvm_unreachable("DLLImport linkage is not supported by this target!");
case GlobalValue::DLLExportLinkage:
- LLVM_UNREACHABLE("DLLExport linkage is not supported by this target!");
+ llvm_unreachable("DLLExport linkage is not supported by this target!");
default:
- LLVM_UNREACHABLE("Unknown linkage type!");
+ llvm_unreachable("Unknown linkage type!");
}
EmitAlignment(Align, GVar);
if(isFP) { // if this is an FP divide, we finish up here and exit early
if(isModulus)
- LLVM_UNREACHABLE("Sorry, try another FORTRAN compiler.");
+ llvm_unreachable("Sorry, try another FORTRAN compiler.");
SDValue TmpE2, TmpY3, TmpQ0, TmpR0;
APFloat(+1.0f) : APFloat(+1.0))) {
V = CurDAG->getCopyFromReg(Chain, dl, IA64::F1, MVT::f64);
} else
- LLVM_UNREACHABLE("Unexpected FP constant!");
+ llvm_unreachable("Unexpected FP constant!");
ReplaceUses(SDValue(N, 0), V);
return 0;
#ifndef NDEBUG
N->dump(CurDAG);
#endif
- LLVM_UNREACHABLE("Cannot load this type!");
+ llvm_unreachable("Cannot load this type!");
case MVT::i1: { // this is a bool
Opc = IA64::LD1; // first we load a byte, then compare for != 0
if(N->getValueType(0) == MVT::i1) { // XXX: early exit!
unsigned Opc;
if (ISD::isNON_TRUNCStore(N)) {
switch (N->getOperand(1).getValueType().getSimpleVT()) {
- default: LLVM_UNREACHABLE("unknown type in store");
+ default: llvm_unreachable("unknown type in store");
case MVT::i1: { // this is a bool
Opc = IA64::ST1; // we store either 0 or 1 as a byte
// first load zero!
}
} else { // Truncating store
switch(ST->getMemoryVT().getSimpleVT()) {
- default: LLVM_UNREACHABLE("unknown type in truncstore");
+ default: llvm_unreachable("unknown type in truncstore");
case MVT::i8: Opc = IA64::ST1; break;
case MVT::i16: Opc = IA64::ST2; break;
case MVT::i32: Opc = IA64::ST4; break;
switch (getValueType(I->getType()).getSimpleVT()) {
default:
- LLVM_UNREACHABLE("ERROR in LowerArgs: can't lower this type of arg.");
+ llvm_unreachable("ERROR in LowerArgs: can't lower this type of arg.");
case MVT::f32:
// fixme? (well, will need to for weird FP structy stuff,
// see intel ABI docs)
// Finally, inform the code generator which regs we return values in.
// (see the ISD::RET: case in the instruction selector)
switch (getValueType(F.getReturnType()).getSimpleVT()) {
- default: LLVM_UNREACHABLE("i have no idea where to return this type!");
+ default: llvm_unreachable("i have no idea where to return this type!");
case MVT::isVoid: break;
case MVT::i1:
case MVT::i8:
SDValue ValToStore(0, 0), ValToConvert(0, 0);
unsigned ObjSize=8;
switch (ObjectVT.getSimpleVT()) {
- default: LLVM_UNREACHABLE("unexpected argument type!");
+ default: llvm_unreachable("unexpected argument type!");
case MVT::i1:
case MVT::i8:
case MVT::i16:
if (InFlag.getNode())
CallOperands.push_back(InFlag);
else
- LLVM_UNREACHABLE("this should never happen!");
+ llvm_unreachable("this should never happen!");
// to make way for a hack:
Chain = DAG.getNode(IA64ISD::BRCALL, dl, NodeTys,
SDValue RetVal;
if (RetTyVT != MVT::isVoid) {
switch (RetTyVT.getSimpleVT()) {
- default: LLVM_UNREACHABLE("Unknown value type to return!");
+ default: llvm_unreachable("Unknown value type to return!");
case MVT::i1: { // bools are just like other integers (returned in r8)
// we *could* fall through to the truncate below, but this saves a
// few redundant predicate ops
LowerOperation(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getDebugLoc();
switch (Op.getOpcode()) {
- default: LLVM_UNREACHABLE("Should not custom lower this!");
+ default: llvm_unreachable("Should not custom lower this!");
case ISD::GlobalTLSAddress:
- LLVM_UNREACHABLE("TLS not implemented for IA64.");
+ llvm_unreachable("TLS not implemented for IA64.");
case ISD::RET: {
SDValue AR_PFSVal, Copy;
switch(Op.getNumOperands()) {
default:
- LLVM_UNREACHABLE("Do not know how to return this many arguments!");
+ llvm_unreachable("Do not know how to return this many arguments!");
case 1:
AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), dl, VirtGPR, MVT::i64);
AR_PFSVal = DAG.getCopyToReg(AR_PFSVal.getValue(1), dl, IA64::AR_PFS,
.addFrameIndex(FrameIdx)
.addReg(IA64::r2);
} else
- LLVM_UNREACHABLE("sorry, I don't know how to store this sort of reg"
+ llvm_unreachable("sorry, I don't know how to store this sort of reg"
"in the stack");
}
} else if (RC == IA64::PRRegisterClass) {
Opc = IA64::ST1;
} else {
- LLVM_UNREACHABLE("sorry, I don't know how to store this sort of reg");
+ llvm_unreachable("sorry, I don't know how to store this sort of reg");
}
DebugLoc DL = DebugLoc::getUnknownLoc();
.addReg(IA64::r2)
.addReg(IA64::r0);
} else {
- LLVM_UNREACHABLE("sorry, I don't know how to load this sort of reg"
+ llvm_unreachable("sorry, I don't know how to load this sort of reg"
"from the stack");
}
}
} else if (RC == IA64::PRRegisterClass) {
Opc = IA64::LD1;
} else {
- LLVM_UNREACHABLE("sorry, I don't know how to load this sort of reg");
+ llvm_unreachable("sorry, I don't know how to load this sort of reg");
}
DebugLoc DL = DebugLoc::getUnknownLoc();
}
unsigned IA64RegisterInfo::getRARegister() const {
- LLVM_UNREACHABLE("What is the return address register");
+ llvm_unreachable("What is the return address register");
return 0;
}
}
unsigned IA64RegisterInfo::getEHExceptionRegister() const {
- LLVM_UNREACHABLE("What is the exception register");
+ llvm_unreachable("What is the exception register");
return 0;
}
unsigned IA64RegisterInfo::getEHHandlerRegister() const {
- LLVM_UNREACHABLE("What is the exception handler register");
+ llvm_unreachable("What is the exception handler register");
return 0;
}
int IA64RegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
- LLVM_UNREACHABLE("What is the dwarf register number");
+ llvm_unreachable("What is the dwarf register number");
return -1;
}
return "modopt([mscorlib]System.Runtime.CompilerServices.CallConvStdcall) ";
default:
cerr << "CallingConvID = " << CallingConvID << '\n';
- LLVM_UNREACHABLE("Unsupported calling convention");
+ llvm_unreachable("Unsupported calling convention");
}
return ""; // Not reached
}
return "float64 ";
default:
cerr << "Type = " << *Ty << '\n';
- LLVM_UNREACHABLE("Invalid primitive type");
+ llvm_unreachable("Invalid primitive type");
}
return ""; // Not reached
}
return "valuetype '"+getArrayTypeName(Ty->getTypeID(),Ty)+"' ";
default:
cerr << "Type = " << *Ty << '\n';
- LLVM_UNREACHABLE("Invalid type in getTypeName()");
+ llvm_unreachable("Invalid type in getTypeName()");
}
return ""; // Not reached
}
return "i"+utostr(TD->getTypeAllocSize(Ty));
default:
cerr << "TypeID = " << Ty->getTypeID() << '\n';
- LLVM_UNREACHABLE("Invalid type in TypeToPostfix()");
+ llvm_unreachable("Invalid type in TypeToPostfix()");
}
return ""; // Not reached
}
printSimpleInstruction("conv.u8");
break;
default:
- LLVM_UNREACHABLE("Module use not supporting pointer size");
+ llvm_unreachable("Module use not supporting pointer size");
}
}
// FIXME: Need overflow test?
if (!isUInt32(N)) {
cerr << "Value = " << utostr(N) << '\n';
- LLVM_UNREACHABLE("32-bit pointer overflowed");
+ llvm_unreachable("32-bit pointer overflowed");
}
break;
case Module::Pointer64:
printSimpleInstruction("ldc.i8",utostr(N).c_str());
break;
default:
- LLVM_UNREACHABLE("Module use not supporting pointer size");
+ llvm_unreachable("Module use not supporting pointer size");
}
}
printPtrLoad(0);
} else {
cerr << "Constant = " << *C << '\n';
- LLVM_UNREACHABLE("Invalid constant value");
+ llvm_unreachable("Invalid constant value");
}
Out << '\n';
}
break;
default:
cerr << "Value = " << *V << '\n';
- LLVM_UNREACHABLE("Invalid value location");
+ llvm_unreachable("Invalid value location");
}
}
break;
default:
cerr << "Value = " << *V << '\n';
- LLVM_UNREACHABLE("Invalid value location");
+ llvm_unreachable("Invalid value location");
}
}
break;
default:
cerr << "Opcode = " << Op << '\n';
- LLVM_UNREACHABLE("Invalid conversion instruction");
+ llvm_unreachable("Invalid conversion instruction");
}
}
Name = getConvModopt(Invoke->getCallingConv());
else {
cerr << "Instruction = " << Inst->getName() << '\n';
- LLVM_UNREACHABLE("Need \"Invoke\" or \"Call\" instruction only");
+ llvm_unreachable("Need \"Invoke\" or \"Call\" instruction only");
}
if (const Function* F = dyn_cast<Function>(FnVal)) {
// Direct call.
break;
default:
cerr << "Intrinsic ID = " << Inst->getIntrinsicID() << '\n';
- LLVM_UNREACHABLE("Invalid intrinsic function");
+ llvm_unreachable("Invalid intrinsic function");
}
}
break;
default:
cerr << "Predicate = " << Predicate << '\n';
- LLVM_UNREACHABLE("Invalid icmp predicate");
+ llvm_unreachable("Invalid icmp predicate");
}
}
printSimpleInstruction("or");
break;
default:
- LLVM_UNREACHABLE("Illegal FCmp predicate");
+ llvm_unreachable("Illegal FCmp predicate");
}
}
printAllocaInstruction(cast<AllocaInst>(Inst));
break;
case Instruction::Malloc:
- LLVM_UNREACHABLE("LowerAllocationsPass used");
+ llvm_unreachable("LowerAllocationsPass used");
break;
case Instruction::Free:
- LLVM_UNREACHABLE("LowerAllocationsPass used");
+ llvm_unreachable("LowerAllocationsPass used");
break;
case Instruction::Unreachable:
printSimpleInstruction("ldstr", "\"Unreachable instruction\"");
break;
default:
cerr << "Instruction = " << Inst->getName() << '\n';
- LLVM_UNREACHABLE("Unsupported instruction");
+ llvm_unreachable("Unsupported instruction");
}
}
break;
default:
cerr << "Expression = " << *CE << "\n";
- LLVM_UNREACHABLE("Invalid constant expression");
+ llvm_unreachable("Invalid constant expression");
}
}
printSimpleInstruction(postfix.c_str());
} else {
cerr << "Constant = " << *I->constant << '\n';
- LLVM_UNREACHABLE("Invalid static initializer");
+ llvm_unreachable("Invalid static initializer");
}
}
}
return N;
default:
cerr << "Bits = " << N << '\n';
- LLVM_UNREACHABLE("Unsupported integer width");
+ llvm_unreachable("Unsupported integer width");
}
return 0; // Not reached
}
// Null pointer initialization
if (TySize==4) Out << "int32 (0)";
else if (TySize==8) Out << "int64 (0)";
- else LLVM_UNREACHABLE("Invalid pointer size");
+ else llvm_unreachable("Invalid pointer size");
}
break;
default:
cerr << "TypeID = " << Ty->getTypeID() << '\n';
- LLVM_UNREACHABLE("Invalid type in printStaticConstant()");
+ llvm_unreachable("Invalid type in printStaticConstant()");
}
// Increase offset.
Offset += TySize;
break;
default:
cerr << "Type = " << *C << "\n";
- LLVM_UNREACHABLE("Invalid constant type");
+ llvm_unreachable("Invalid constant type");
}
// Print initializer
std::string label = Name;
EmitAlignment(FnAlign, F);
switch (F->getLinkage()) {
- default: LLVM_UNREACHABLE("Unknown linkage type!");
+ default: llvm_unreachable("Unknown linkage type!");
case Function::InternalLinkage: // Symbols default to internal.
case Function::PrivateLinkage:
break;
if (printInstruction(MI))
return;
- LLVM_UNREACHABLE("Should not happen");
+ llvm_unreachable("Should not happen");
}
void MSP430AsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
return;
}
default:
- LLVM_UNREACHABLE("Not implemented yet!");
+ llvm_unreachable("Not implemented yet!");
}
}
printOperand(MI, OpNum);
}
} else
- LLVM_UNREACHABLE("Unsupported memory operand");
+ llvm_unreachable("Unsupported memory operand");
}
void MSP430AsmPrinter::printCCOperand(const MachineInstr *MI, int OpNum) {
switch (CC) {
default:
- LLVM_UNREACHABLE("Unsupported CC code");
+ llvm_unreachable("Unsupported CC code");
break;
case MSP430::COND_E:
O << "eq";
case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
default:
- LLVM_UNREACHABLE("unimplemented operand");
+ llvm_unreachable("unimplemented operand");
return SDValue();
}
}
unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
switch (CC) {
default:
- LLVM_UNREACHABLE("Unsupported calling convention");
+ llvm_unreachable("Unsupported calling convention");
case CallingConv::C:
case CallingConv::Fast:
return LowerCCCArguments(Op, DAG);
unsigned CallingConv = TheCall->getCallingConv();
switch (CallingConv) {
default:
- LLVM_UNREACHABLE("Unsupported calling convention");
+ llvm_unreachable("Unsupported calling convention");
case CallingConv::Fast:
case CallingConv::C:
return LowerCCCCallTo(Op, DAG, CallingConv);
cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
<< RegVT.getSimpleVT() << "\n";
#endif
- llvm_unreachable();
+ llvm_unreachable(0);
}
case MVT::i16:
unsigned VReg =
// Promote the value if needed.
switch (VA.getLocInfo()) {
- default: LLVM_UNREACHABLE("Unknown loc info!");
+ default: llvm_unreachable("Unknown loc info!");
case CCValAssign::Full: break;
case CCValAssign::SExt:
Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
// FIXME: Handle jump negative someday
TargetCC = MSP430::COND_INVALID;
switch (CC) {
- default: LLVM_UNREACHABLE("Invalid integer condition!");
+ default: llvm_unreachable("Invalid integer condition!");
case ISD::SETEQ:
TargetCC = MSP430::COND_E; // aka COND_Z
break;
.addFrameIndex(FrameIdx).addImm(0)
.addReg(SrcReg, getKillRegState(isKill));
else
- LLVM_UNREACHABLE("Cannot store this register to stack slot!");
+ llvm_unreachable("Cannot store this register to stack slot!");
}
void MSP430InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
BuildMI(MBB, MI, DL, get(MSP430::MOV8rm))
.addReg(DestReg).addFrameIndex(FrameIdx).addImm(0);
else
- LLVM_UNREACHABLE("Cannot store this register to stack slot!");
+ llvm_unreachable("Cannot store this register to stack slot!");
}
bool MSP430InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
// Conditional branch.
unsigned Count = 0;
- LLVM_UNREACHABLE("Implement conditional branches!");
+ llvm_unreachable("Implement conditional branches!");
return Count;
}
switch (RetOpcode) {
case MSP430::RET: break; // These are ok
default:
- LLVM_UNREACHABLE("Can only insert epilog into returning blocks");
+ llvm_unreachable("Can only insert epilog into returning blocks");
}
// Get the number of bytes to allocate from the FrameInfo
// mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
if (MFI->hasVarSizedObjects()) {
- LLVM_UNREACHABLE("Not implemented yet!");
+ llvm_unreachable("Not implemented yet!");
} else {
// adjust stack pointer back: SPW += numbytes
if (NumBytes) {
}
int MSP430RegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
- LLVM_UNREACHABLE("Not implemented yet!");
+ llvm_unreachable("Not implemented yet!");
return 0;
}
default: break;
}
- LLVM_UNREACHABLE("Unknown Mips ABI");
+ llvm_unreachable("Unknown Mips ABI");
return NULL;
}
break;
default:
- LLVM_UNREACHABLE("<unknown operand type>");
+ llvm_unreachable("<unknown operand type>");
}
if (closeP) O << ")";
printSizeAndType = false;
break;
case GlobalValue::GhostLinkage:
- LLVM_UNREACHABLE("Should not have any unmaterialized functions!");
+ llvm_unreachable("Should not have any unmaterialized functions!");
case GlobalValue::DLLImportLinkage:
- LLVM_UNREACHABLE("DLLImport linkage is not supported by this target!");
+ llvm_unreachable("DLLImport linkage is not supported by this target!");
case GlobalValue::DLLExportLinkage:
- LLVM_UNREACHABLE("DLLExport linkage is not supported by this target!");
+ llvm_unreachable("DLLExport linkage is not supported by this target!");
default:
- LLVM_UNREACHABLE("Unknown linkage type!");
+ llvm_unreachable("Unknown linkage type!");
}
EmitAlignment(Align, GVar);
static unsigned FPBranchCodeToOpc(Mips::FPBranchCode BC) {
switch(BC) {
default:
- LLVM_UNREACHABLE("Unknown branch code");
+ llvm_unreachable("Unknown branch code");
case Mips::BRANCH_T : return Mips::BC1T;
case Mips::BRANCH_F : return Mips::BC1F;
case Mips::BRANCH_TL : return Mips::BC1TL;
static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
switch (CC) {
- default: LLVM_UNREACHABLE("Unknown fp condition code!");
+ default: llvm_unreachable("Unknown fp condition code!");
case ISD::SETEQ:
case ISD::SETOEQ: return Mips::FCOND_EQ;
case ISD::SETUNE: return Mips::FCOND_OGL;
return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo);
}
- LLVM_UNREACHABLE("Dont know how to handle GlobalAddress");
+ llvm_unreachable("Dont know how to handle GlobalAddress");
return SDValue(0,0);
}
SDValue MipsTargetLowering::
LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG)
{
- LLVM_UNREACHABLE("TLS not implemented for MIPS.");
+ llvm_unreachable("TLS not implemented for MIPS.");
return SDValue(); // Not reached
}
// Promote the value if needed.
switch (VA.getLocInfo()) {
- default: LLVM_UNREACHABLE("Unknown loc info!");
+ default: llvm_unreachable("Unknown loc info!");
case CCValAssign::Full:
if (Subtarget->isABI_O32() && VA.isRegLoc()) {
if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32)
if (!Subtarget->isSingleFloat())
RC = Mips::AFGR64RegisterClass;
} else
- LLVM_UNREACHABLE("RegVT not supported by FORMAL_ARGUMENTS Lowering");
+ llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
// Transform the arguments stored on
// physical registers into virtual ones
unsigned Reg = MipsFI->getSRetReturnReg();
if (!Reg)
- LLVM_UNREACHABLE("sret virtual register not created in the entry block");
+ llvm_unreachable("sret virtual register not created in the entry block");
SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag);
unsigned Mips::GetCondBranchFromCond(Mips::CondCode CC)
{
switch (CC) {
- default: LLVM_UNREACHABLE("Illegal condition code!");
+ default: llvm_unreachable("Illegal condition code!");
case Mips::COND_E : return Mips::BEQ;
case Mips::COND_NE : return Mips::BNE;
case Mips::COND_GZ : return Mips::BGTZ;
Mips::CondCode Mips::GetOppositeBranchCondition(Mips::CondCode CC)
{
switch (CC) {
- default: LLVM_UNREACHABLE("Illegal condition code!");
+ default: llvm_unreachable("Illegal condition code!");
case Mips::COND_E : return Mips::COND_NE;
case Mips::COND_NE : return Mips::COND_E;
case Mips::COND_GZ : return Mips::COND_LEZ;
inline static const char *MipsFCCToString(Mips::CondCode CC)
{
switch (CC) {
- default: LLVM_UNREACHABLE("Unknown condition code");
+ default: llvm_unreachable("Unknown condition code");
case FCOND_F:
case FCOND_T: return "f";
case FCOND_UN:
case Mips::SP : case Mips::F29: return 29;
case Mips::FP : case Mips::F30: case Mips::D15: return 30;
case Mips::RA : case Mips::F31: return 31;
- default: LLVM_UNREACHABLE("Unknown register number!");
+ default: llvm_unreachable("Unknown register number!");
}
return 0; // Not reached
}
unsigned MipsRegisterInfo::
getEHExceptionRegister() const {
- LLVM_UNREACHABLE("What is the exception register");
+ llvm_unreachable("What is the exception register");
return 0;
}
unsigned MipsRegisterInfo::
getEHHandlerRegister() const {
- LLVM_UNREACHABLE("What is the exception handler register");
+ llvm_unreachable("What is the exception handler register");
return 0;
}
int MipsRegisterInfo::
getDwarfRegNum(unsigned RegNum, bool isEH) const {
- LLVM_UNREACHABLE("What is the dwarf register number");
+ llvm_unreachable("What is the dwarf register number");
return -1;
}
inline static const char *PIC16CondCodeToString(PIC16CC::CondCodes CC) {
switch (CC) {
- default: LLVM_UNREACHABLE("Unknown condition code");
+ default: llvm_unreachable("Unknown condition code");
case PIC16CC::NE: return "ne";
case PIC16CC::EQ: return "eq";
case PIC16CC::LT: return "lt";
inline static bool isSignedComparison(PIC16CC::CondCodes CC) {
switch (CC) {
- default: LLVM_UNREACHABLE("Unknown condition code");
+ default: llvm_unreachable("Unknown condition code");
case PIC16CC::NE:
case PIC16CC::EQ:
case PIC16CC::LT:
if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
else
- LLVM_UNREACHABLE("not implemented");
+ llvm_unreachable("not implemented");
return;
case MachineOperand::MO_Immediate:
return;
default:
- LLVM_UNREACHABLE(" Operand type not supported.");
+ llvm_unreachable(" Operand type not supported.");
}
}
// return should have odd number of operands
if ((Op.getNumOperands() % 2) == 0 ) {
- LLVM_UNREACHABLE("Do not know how to return this many arguments!");
+ llvm_unreachable("Do not know how to return this many arguments!");
}
// Number of values to return
static PIC16CC::CondCodes IntCCToPIC16CC(ISD::CondCode CC) {
switch (CC) {
- default: LLVM_UNREACHABLE("Unknown condition code!");
+ default: llvm_unreachable("Unknown condition code!");
case ISD::SETNE: return PIC16CC::NE;
case ISD::SETEQ: return PIC16CC::EQ;
case ISD::SETGT: return PIC16CC::GT;
.addImm(1); // Emit banksel for it.
}
else
- LLVM_UNREACHABLE("Can't store this register to stack slot");
+ llvm_unreachable("Can't store this register to stack slot");
}
void PIC16InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
.addImm(1); // Emit banksel for it.
}
else
- LLVM_UNREACHABLE("Can't load this register from stack slot");
+ llvm_unreachable("Can't load this register from stack slot");
}
bool PIC16InstrInfo::copyRegToReg (MachineBasicBlock &MBB,
int PIC16RegisterInfo::
getDwarfRegNum(unsigned RegNum, bool isEH) const {
- LLVM_UNREACHABLE("Not keeping track of debug information yet!!");
+ llvm_unreachable("Not keeping track of debug information yet!!");
return -1;
}
unsigned PIC16RegisterInfo::getFrameRegister(MachineFunction &MF) const {
- LLVM_UNREACHABLE("PIC16 Does not have any frame register");
+ llvm_unreachable("PIC16 Does not have any frame register");
return 0;
}
unsigned PIC16RegisterInfo::getRARegister() const {
- LLVM_UNREACHABLE("PIC16 Does not have any return address register");
+ llvm_unreachable("PIC16 Does not have any return address register");
return 0;
}
unsigned enumRegToMachineReg(unsigned enumReg) {
switch (enumReg) {
- default: LLVM_UNREACHABLE("Unhandled register!");
+ default: llvm_unreachable("Unhandled register!");
case PPC::CR0: return 0;
case PPC::CR1: return 1;
case PPC::CR2: return 2;
case PPC::CR6: return 6;
case PPC::CR7: return 7;
}
- llvm_unreachable();
+ llvm_unreachable(0);
}
/// printInstruction - This method is automatically generated by tablegen
void PPCAsmPrinter::printOp(const MachineOperand &MO) {
switch (MO.getType()) {
case MachineOperand::MO_Immediate:
- LLVM_UNREACHABLE("printOp() does not handle immediate values");
+ llvm_unreachable("printOp() does not handle immediate values");
case MachineOperand::MO_MachineBasicBlock:
printBasicBlockLabel(MO.getMBB());
if (printInstruction(MI))
return; // Printer was automatically generated
- LLVM_UNREACHABLE("Unhandled instruction in asm writer!");
+ llvm_unreachable("Unhandled instruction in asm writer!");
}
/// runOnMachineFunction - This uses the printMachineInstruction()
SwitchToSection(TAI->SectionForGlobal(F));
switch (F->getLinkage()) {
- default: LLVM_UNREACHABLE("Unknown linkage type!");
+ default: llvm_unreachable("Unknown linkage type!");
case Function::PrivateLinkage:
case Function::InternalLinkage: // Symbols default to internal.
break;
case GlobalValue::PrivateLinkage:
break;
default:
- LLVM_UNREACHABLE("Unknown linkage type!");
+ llvm_unreachable("Unknown linkage type!");
}
EmitAlignment(Align, GVar);
SwitchToSection(TAI->SectionForGlobal(F));
switch (F->getLinkage()) {
- default: LLVM_UNREACHABLE("Unknown linkage type!");
+ default: llvm_unreachable("Unknown linkage type!");
case Function::PrivateLinkage:
case Function::InternalLinkage: // Symbols default to internal.
break;
case GlobalValue::PrivateLinkage:
break;
default:
- LLVM_UNREACHABLE("Unknown linkage type!");
+ llvm_unreachable("Unknown linkage type!");
}
EmitAlignment(Align, GVar);
assert(MovePCtoLROffset && "MovePCtoLR not seen yet?");
}
switch (MI.getOpcode()) {
- default: MI.dump(); LLVM_UNREACHABLE("Unknown instruction for relocation!");
+ default: MI.dump(); llvm_unreachable("Unknown instruction for relocation!");
case PPC::LIS:
case PPC::LIS8:
case PPC::ADDIS:
#ifndef NDEBUG
cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
#endif
- llvm_unreachable();
+ llvm_unreachable(0);
}
return rv;
return Hazard;
switch (InstrType) {
- default: LLVM_UNREACHABLE("Unknown instruction type!");
+ default: llvm_unreachable("Unknown instruction type!");
case PPCII::PPC970_FXU:
case PPCII::PPC970_LSU:
case PPCII::PPC970_FPU:
if (isLoad && NumStores) {
unsigned LoadSize;
switch (Opcode) {
- default: LLVM_UNREACHABLE("Unknown load!");
+ default: llvm_unreachable("Unknown load!");
case PPC::LBZ: case PPC::LBZU:
case PPC::LBZX:
case PPC::LBZ8: case PPC::LBZU8:
if (isStore) {
unsigned ThisStoreSize;
switch (Opcode) {
- default: LLVM_UNREACHABLE("Unknown store instruction!");
+ default: llvm_unreachable("Unknown store instruction!");
case PPC::STB: case PPC::STB8:
case PPC::STBU: case PPC::STBU8:
case PPC::STBX: case PPC::STBX8:
case ISD::SETONE:
case ISD::SETOLE:
case ISD::SETOGE:
- LLVM_UNREACHABLE("Should be lowered by legalize!");
- default: LLVM_UNREACHABLE("Unknown condition!");
+ llvm_unreachable("Should be lowered by legalize!");
+ default: llvm_unreachable("Unknown condition!");
case ISD::SETOEQ:
case ISD::SETEQ: return PPC::PRED_EQ;
case ISD::SETUNE:
Invert = false;
Other = -1;
switch (CC) {
- default: LLVM_UNREACHABLE("Unknown condition!");
+ default: llvm_unreachable("Unknown condition!");
case ISD::SETOLT:
case ISD::SETLT: return 0; // Bit #0 = SETOLT
case ISD::SETOGT:
case ISD::SETOGE:
case ISD::SETOLE:
case ISD::SETONE:
- LLVM_UNREACHABLE("Invalid branch code: should be expanded by legalize");
+ llvm_unreachable("Invalid branch code: should be expanded by legalize");
// These are invalid for floating point. Assume integer.
case ISD::SETULT: return 0;
case ISD::SETUGT: return 1;
// Handle PPC32 integer and normal FP loads.
assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
switch (LoadedVT.getSimpleVT()) {
- default: LLVM_UNREACHABLE("Invalid PPC load type!");
+ default: llvm_unreachable("Invalid PPC load type!");
case MVT::f64: Opcode = PPC::LFDU; break;
case MVT::f32: Opcode = PPC::LFSU; break;
case MVT::i32: Opcode = PPC::LWZU; break;
assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
switch (LoadedVT.getSimpleVT()) {
- default: LLVM_UNREACHABLE("Invalid PPC load type!");
+ default: llvm_unreachable("Invalid PPC load type!");
case MVT::i64: Opcode = PPC::LDU; break;
case MVT::i32: Opcode = PPC::LWZU8; break;
case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
PPCLowering.getPointerTy(),
MVT::Other, Ops, 3);
} else {
- LLVM_UNREACHABLE("R+R preindex loads not supported yet!");
+ llvm_unreachable("R+R preindex loads not supported yet!");
}
}
SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
SelectionDAG &DAG) {
- LLVM_UNREACHABLE("TLS not implemented for PPC.");
+ llvm_unreachable("TLS not implemented for PPC.");
return SDValue(); // Not reached
}
unsigned VarArgsNumFPR,
const PPCSubtarget &Subtarget) {
- LLVM_UNREACHABLE("VAARG not yet implemented for the SVR4 ABI!");
+ llvm_unreachable("VAARG not yet implemented for the SVR4 ABI!");
return SDValue(); // Not reached
}
switch (ValVT.getSimpleVT()) {
default:
- LLVM_UNREACHABLE("ValVT not supported by FORMAL_ARGUMENTS Lowering");
+ llvm_unreachable("ValVT not supported by FORMAL_ARGUMENTS Lowering");
case MVT::i32:
RC = PPC::GPRCRegisterClass;
break;
}
switch(ObjectVT.getSimpleVT()) {
- default: LLVM_UNREACHABLE("Unhandled argument type!");
+ default: llvm_unreachable("Unhandled argument type!");
case MVT::i32:
case MVT::f32:
VecArgOffset += isPPC64 ? 8 : 4;
}
switch (ObjectVT.getSimpleVT()) {
- default: LLVM_UNREACHABLE("Unhandled argument type!");
+ default: llvm_unreachable("Unhandled argument type!");
case MVT::i32:
if (!isPPC64) {
if (GPR_idx != Num_GPR_Regs) {
cerr << "Call operand #" << i << " has unhandled type "
<< ArgVT.getMVTString() << "\n";
#endif
- llvm_unreachable();
+ llvm_unreachable(0);
}
}
} else {
}
switch (Arg.getValueType().getSimpleVT()) {
- default: LLVM_UNREACHABLE("Unexpected ValueType for argument!");
+ default: llvm_unreachable("Unexpected ValueType for argument!");
case MVT::i32:
case MVT::i64:
if (GPR_idx != NumGPRs) {
SDValue Tmp;
switch (Op.getValueType().getSimpleVT()) {
- default: LLVM_UNREACHABLE("Unhandled FP_TO_INT type in custom expander!");
+ default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
case MVT::i32:
Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
PPCISD::FCTIDZ,
int ShufIdxs[16];
switch (OpNum) {
- default: LLVM_UNREACHABLE("Unknown i32 permute!");
+ default: llvm_unreachable("Unknown i32 permute!");
case OP_VMRGHW:
ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
}
return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
} else {
- LLVM_UNREACHABLE("Unknown mul to lower!");
+ llvm_unreachable("Unknown mul to lower!");
}
}
///
SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
switch (Op.getOpcode()) {
- default: LLVM_UNREACHABLE("Wasn't expecting to be able to lower this!");
+ default: llvm_unreachable("Wasn't expecting to be able to lower this!");
case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
BB = exitMBB;
BuildMI(BB, dl, TII->get(PPC::SRW),dest).addReg(TmpReg).addReg(ShiftReg);
} else {
- LLVM_UNREACHABLE("Unexpected instr type to insert");
+ llvm_unreachable("Unexpected instr type to insert");
}
F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
if (!CST) return; // Must be an immediate to match.
unsigned Value = CST->getZExtValue();
switch (Letter) {
- default: LLVM_UNREACHABLE("Unknown constraint letter!");
+ default: llvm_unreachable("Unknown constraint letter!");
case 'I': // "I" is a signed 16-bit constant.
if ((short)Value == (int)Value)
Result = DAG.getTargetConstant(Value, Op.getValueType());
.addReg(PPC::R0)
.addReg(PPC::R0));
} else {
- LLVM_UNREACHABLE("Unknown regclass!");
+ llvm_unreachable("Unknown regclass!");
}
return false;
} else if (RC == PPC::VRRCRegisterClass) {
Opc = PPC::STVX;
} else {
- LLVM_UNREACHABLE("Unknown regclass!");
+ llvm_unreachable("Unknown regclass!");
}
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc))
.addReg(SrcReg, getKillRegState(isKill));
NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0)
.addReg(PPC::R0));
} else {
- LLVM_UNREACHABLE("Unknown regclass!");
+ llvm_unreachable("Unknown regclass!");
}
}
} else if (RC == PPC::VRRCRegisterClass) {
Opc = PPC::LVX;
} else {
- LLVM_UNREACHABLE("Unknown regclass!");
+ llvm_unreachable("Unknown regclass!");
}
DebugLoc DL = DebugLoc::getUnknownLoc();
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
);
#else
void PPC32CompilationCallback() {
- LLVM_UNREACHABLE("This is not a power pc, you can't execute this!");
+ llvm_unreachable("This is not a power pc, you can't execute this!");
}
#endif
);
#else
void PPC64CompilationCallback() {
- LLVM_UNREACHABLE("This is not a power pc, you can't execute this!");
+ llvm_unreachable("This is not a power pc, you can't execute this!");
}
#endif
unsigned *RelocPos = (unsigned*)Function + MR->getMachineCodeOffset()/4;
intptr_t ResultPtr = (intptr_t)MR->getResultPointer();
switch ((PPC::RelocationType)MR->getRelocationType()) {
- default: LLVM_UNREACHABLE("Unknown relocation type!");
+ default: llvm_unreachable("Unknown relocation type!");
case PPC::reloc_pcrel_bx:
// PC-relative relocation for b and bl instructions.
ResultPtr = (ResultPtr-(intptr_t)RelocPos) >> 2;
Addr = (uintptr_t)MR.getResultPointer() + ToAddr;
switch ((PPC::RelocationType)MR.getRelocationType()) {
- default: LLVM_UNREACHABLE("Unknown PPC relocation type!");
+ default: llvm_unreachable("Unknown PPC relocation type!");
case PPC::reloc_absolute_low_ix:
- LLVM_UNREACHABLE("Unhandled PPC relocation type!");
+ llvm_unreachable("Unhandled PPC relocation type!");
break;
case PPC::reloc_vanilla:
{
PPC::Predicate PPC::InvertPredicate(PPC::Predicate Opcode) {
switch (Opcode) {
- default: LLVM_UNREACHABLE("Unknown PPC branch opcode!");
+ default: llvm_unreachable("Unknown PPC branch opcode!");
case PPC::PRED_EQ: return PPC::PRED_NE;
case PPC::PRED_NE: return PPC::PRED_EQ;
case PPC::PRED_LT: return PPC::PRED_GE;
case R30: case X30: case F30: case V30: case CR7EQ: return 30;
case R31: case X31: case F31: case V31: case CR7UN: return 31;
default:
- LLVM_UNREACHABLE("Unhandled reg in PPCRegisterInfo::getRegisterNumbering!");
+ llvm_unreachable("Unhandled reg in PPCRegisterInfo::getRegisterNumbering!");
}
}
MinVR = Reg;
}
} else {
- LLVM_UNREACHABLE("Unknown RegisterClass!");
+ llvm_unreachable("Unknown RegisterClass!");
}
}
<< MO.getIndex();
break;
default:
- LLVM_UNREACHABLE("<unknown operand type>");
+ llvm_unreachable("<unknown operand type>");
}
if (CloseParen) O << ")";
}
case GlobalValue::InternalLinkage:
break;
case GlobalValue::GhostLinkage:
- LLVM_UNREACHABLE("Should not have any unmaterialized functions!");
+ llvm_unreachable("Should not have any unmaterialized functions!");
case GlobalValue::DLLImportLinkage:
- LLVM_UNREACHABLE("DLLImport linkage is not supported by this target!");
+ llvm_unreachable("DLLImport linkage is not supported by this target!");
case GlobalValue::DLLExportLinkage:
- LLVM_UNREACHABLE("DLLExport linkage is not supported by this target!");
+ llvm_unreachable("DLLExport linkage is not supported by this target!");
default:
- LLVM_UNREACHABLE("Unknown linkage type!");
+ llvm_unreachable("Unknown linkage type!");
}
EmitAlignment(Align, GVar);
OddReg = OddHalvesOfPairs[i];
return;
}
- LLVM_UNREACHABLE("Can't find reg");
+ llvm_unreachable("Can't find reg");
}
/// runOnMachineBasicBlock - Fixup FpMOVD instructions in this MBB.
else if (MI->getOpcode() == SP::FpABSD)
MI->setDesc(TII->get(SP::FABSS));
else
- LLVM_UNREACHABLE("Unknown opcode!");
+ llvm_unreachable("Unknown opcode!");
MI->getOperand(0).setReg(EvenDestReg);
MI->getOperand(1).setReg(EvenSrcReg);
inline static const char *SPARCCondCodeToString(SPCC::CondCodes CC) {
switch (CC) {
- default: LLVM_UNREACHABLE("Unknown condition code");
+ default: llvm_unreachable("Unknown condition code");
case SPCC::ICC_NE: return "ne";
case SPCC::ICC_E: return "e";
case SPCC::ICC_G: return "g";
MVT ObjectVT = getValueType(I->getType());
switch (ObjectVT.getSimpleVT()) {
- default: LLVM_UNREACHABLE("Unhandled argument type!");
+ default: llvm_unreachable("Unhandled argument type!");
case MVT::i1:
case MVT::i8:
case MVT::i16:
unsigned ArgsSize = 0;
for (unsigned i = 0, e = TheCall->getNumArgs(); i != e; ++i) {
switch (TheCall->getArg(i).getValueType().getSimpleVT()) {
- default: LLVM_UNREACHABLE("Unknown value type!");
+ default: llvm_unreachable("Unknown value type!");
case MVT::i1:
case MVT::i8:
case MVT::i16:
// Promote the value if needed.
switch (VA.getLocInfo()) {
- default: LLVM_UNREACHABLE("Unknown loc info!");
+ default: llvm_unreachable("Unknown loc info!");
case CCValAssign::Full: break;
case CCValAssign::SExt:
Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
SDValue ValToStore(0, 0);
unsigned ObjSize;
switch (ObjectVT.getSimpleVT()) {
- default: LLVM_UNREACHABLE("Unhandled argument type!");
+ default: llvm_unreachable("Unhandled argument type!");
case MVT::i32:
ObjSize = 4;
/// condition.
static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
switch (CC) {
- default: LLVM_UNREACHABLE("Unknown integer condition code!");
+ default: llvm_unreachable("Unknown integer condition code!");
case ISD::SETEQ: return SPCC::ICC_E;
case ISD::SETNE: return SPCC::ICC_NE;
case ISD::SETLT: return SPCC::ICC_L;
/// FCC condition.
static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
switch (CC) {
- default: LLVM_UNREACHABLE("Unknown fp condition code!");
+ default: llvm_unreachable("Unknown fp condition code!");
case ISD::SETEQ:
case ISD::SETOEQ: return SPCC::FCC_E;
case ISD::SETNE:
SDValue SparcTargetLowering::
LowerOperation(SDValue Op, SelectionDAG &DAG) {
switch (Op.getOpcode()) {
- default: LLVM_UNREACHABLE("Should not custom lower this!");
+ default: llvm_unreachable("Should not custom lower this!");
// Frame & Return address. Currently unimplemented
case ISD::RETURNADDR: return SDValue();
case ISD::FRAMEADDR: return SDValue();
case ISD::GlobalTLSAddress:
- LLVM_UNREACHABLE("TLS not implemented for Sparc.");
+ llvm_unreachable("TLS not implemented for Sparc.");
case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG);
case ISD::ConstantPool: return LowerCONSTANTPOOL(Op, DAG);
case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
DebugLoc dl = MI->getDebugLoc();
// Figure out the conditional branch opcode to use for this select_cc.
switch (MI->getOpcode()) {
- default: LLVM_UNREACHABLE("Unknown SELECT_CC!");
+ default: llvm_unreachable("Unknown SELECT_CC!");
case SP::SELECT_CC_Int_ICC:
case SP::SELECT_CC_FP_ICC:
case SP::SELECT_CC_DFP_ICC:
BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
.addReg(SrcReg, getKillRegState(isKill));
else
- LLVM_UNREACHABLE("Can't store this register to stack slot");
+ llvm_unreachable("Can't store this register to stack slot");
}
void SparcInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
else if (RC == SP::DFPRegsRegisterClass)
Opc = SP::STDFri;
else
- LLVM_UNREACHABLE("Can't load this register");
+ llvm_unreachable("Can't load this register");
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
MIB.addOperand(Addr[i]);
else if (RC == SP::DFPRegsRegisterClass)
BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0);
else
- LLVM_UNREACHABLE("Can't load this register from stack slot");
+ llvm_unreachable("Can't load this register from stack slot");
}
void SparcInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
else if (RC == SP::DFPRegsRegisterClass)
Opc = SP::LDDFri;
else
- LLVM_UNREACHABLE("Can't load this register");
+ llvm_unreachable("Can't load this register");
DebugLoc DL = DebugLoc::getUnknownLoc();
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
}
unsigned SparcRegisterInfo::getRARegister() const {
- LLVM_UNREACHABLE("What is the return address register");
+ llvm_unreachable("What is the return address register");
return 0;
}
unsigned SparcRegisterInfo::getFrameRegister(MachineFunction &MF) const {
- LLVM_UNREACHABLE("What is the frame register");
+ llvm_unreachable("What is the frame register");
return SP::G1;
}
unsigned SparcRegisterInfo::getEHExceptionRegister() const {
- LLVM_UNREACHABLE("What is the exception register");
+ llvm_unreachable("What is the exception register");
return 0;
}
unsigned SparcRegisterInfo::getEHHandlerRegister() const {
- LLVM_UNREACHABLE("What is the exception handler register");
+ llvm_unreachable("What is the exception handler register");
return 0;
}
int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
- LLVM_UNREACHABLE("What is the dwarf register number");
+ llvm_unreachable("What is the dwarf register number");
return -1;
}
Flags |= SectionFlags::Small;
break;
default:
- LLVM_UNREACHABLE("Unexpected section kind!");
+ llvm_unreachable("Unexpected section kind!");
}
if (GV->isWeakForLinker())
case SectionKind::ThreadBSS:
return ".gnu.linkonce.tb." + GV->getName();
default:
- LLVM_UNREACHABLE("Unknown section kind");
+ llvm_unreachable("Unknown section kind");
}
return NULL;
}
case Type::VectorTyID:
return cast<VectorType>(Ty)->getBitWidth();
default:
- LLVM_UNREACHABLE("TargetData::getTypeSizeInBits(): Unsupported type");
+ llvm_unreachable("TargetData::getTypeSizeInBits(): Unsupported type");
break;
}
return 0;
AlignType = VECTOR_ALIGN;
break;
default:
- LLVM_UNREACHABLE("Bad type for getAlignment!!!");
+ llvm_unreachable("Bad type for getAlignment!!!");
break;
}
else if (Subtarget->isTargetELF())
O << ".Lllvm$" << getFunctionNumber() << ".$piclabel";
else
- LLVM_UNREACHABLE("Don't know how to print PIC label!");
+ llvm_unreachable("Don't know how to print PIC label!");
}
/// PrintUnmangledNameSafely - Print out the printable characters in the name.
}
break;
default:
- LLVM_UNREACHABLE("Unsupported DecorationStyle");
+ llvm_unreachable("Unsupported DecorationStyle");
}
}
SwitchToSection(TAI->SectionForGlobal(F));
switch (F->getLinkage()) {
- default: LLVM_UNREACHABLE("Unknown linkage type!");
+ default: llvm_unreachable("Unknown linkage type!");
case Function::InternalLinkage: // Symbols default to internal.
case Function::PrivateLinkage:
EmitAlignment(FnAlign, F);
/// which print to a label with various suffixes for relocation types etc.
void X86ATTAsmPrinter::printSymbolOperand(const MachineOperand &MO) {
switch (MO.getType()) {
- default: LLVM_UNREACHABLE("unknown symbol type!");
+ default: llvm_unreachable("unknown symbol type!");
case MachineOperand::MO_JumpTableIndex:
O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber() << '_'
<< MO.getIndex();
switch (MO.getTargetFlags()) {
default:
- LLVM_UNREACHABLE("Unknown target flag on GV operand");
+ llvm_unreachable("Unknown target flag on GV operand");
case X86II::MO_NO_FLAG: // No flag.
break;
case X86II::MO_DARWIN_NONLAZY:
void X86ATTAsmPrinter::print_pcrel_imm(const MachineInstr *MI, unsigned OpNo) {
const MachineOperand &MO = MI->getOperand(OpNo);
switch (MO.getType()) {
- default: LLVM_UNREACHABLE("Unknown pcrel immediate operand");
+ default: llvm_unreachable("Unknown pcrel immediate operand");
case MachineOperand::MO_Immediate:
O << MO.getImm();
return;
const char *Modifier) {
const MachineOperand &MO = MI->getOperand(OpNo);
switch (MO.getType()) {
- default: LLVM_UNREACHABLE("unknown operand type!");
+ default: llvm_unreachable("unknown operand type!");
case MachineOperand::MO_Register: {
assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
"Virtual registers should not make it this far!");
} else if (MO.isMBB()) {
MCOp.MakeMBBLabel(getFunctionNumber(), MO.getMBB()->getNumber());
} else {
- LLVM_UNREACHABLE("Unimp");
+ llvm_unreachable("Unimp");
}
TmpInst.addOperand(MCOp);
case GlobalValue::InternalLinkage:
break;
default:
- LLVM_UNREACHABLE("Unknown linkage type!");
+ llvm_unreachable("Unknown linkage type!");
}
EmitAlignment(Align, GVar);
void X86ATTAsmPrinter::printSSECC(const MCInst *MI, unsigned Op) {
switch (MI->getOperand(Op).getImm()) {
- default: LLVM_UNREACHABLE("Invalid ssecc argument!");
+ default: llvm_unreachable("Invalid ssecc argument!");
case 0: O << "eq"; break;
case 1: O << "lt"; break;
case 2: O << "le"; break;
void X86ATTAsmPrinter::printPICLabel(const MCInst *MI, unsigned Op) {
- LLVM_UNREACHABLE("This is only used for MOVPC32r,"
+ llvm_unreachable("This is only used for MOVPC32r,"
"should lower before asm printing!");
}
O << TAI->getPrivateGlobalPrefix() << "BB" << Op.getMBBLabelFunction()
<< '_' << Op.getMBBLabelBlock();
else
- LLVM_UNREACHABLE("Unknown pcrel immediate operand");
+ llvm_unreachable("Unknown pcrel immediate operand");
}
if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
O << DispVal;
} else {
- LLVM_UNREACHABLE("non-immediate displacement for LEA?");
+ llvm_unreachable("non-immediate displacement for LEA?");
//assert(DispSpec.isGlobal() || DispSpec.isCPI() ||
// DispSpec.isJTI() || DispSpec.isSymbol());
//printOperand(MI, Op+3, "mem");
break;
default:
- LLVM_UNREACHABLE("Unsupported DecorationStyle");
+ llvm_unreachable("Unsupported DecorationStyle");
}
}
SwitchToTextSection("_text", F);
switch (F->getLinkage()) {
- default: LLVM_UNREACHABLE("Unsupported linkage type!");
+ default: llvm_unreachable("Unsupported linkage type!");
case Function::PrivateLinkage:
case Function::InternalLinkage:
EmitAlignment(FnAlign);
void X86IntelAsmPrinter::print_pcrel_imm(const MachineInstr *MI, unsigned OpNo){
const MachineOperand &MO = MI->getOperand(OpNo);
switch (MO.getType()) {
- default: LLVM_UNREACHABLE("Unknown pcrel immediate operand");
+ default: llvm_unreachable("Unknown pcrel immediate operand");
case MachineOperand::MO_Immediate:
O << MO.getImm();
return;
SwitchToSection(TAI->getDataSection());
break;
default:
- LLVM_UNREACHABLE("Unknown linkage type!");
+ llvm_unreachable("Unknown linkage type!");
}
if (!bCustomSegment)
unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_picrel_word;
emitJumpTableAddress(RelocOp->getIndex(), rt, PCAdj);
} else {
- LLVM_UNREACHABLE("Unknown value to relocate!");
+ llvm_unreachable("Unknown value to relocate!");
}
}
case X86II::GS:
MCE.emitByte(0x65);
break;
- default: LLVM_UNREACHABLE("Invalid segment!");
+ default: llvm_unreachable("Invalid segment!");
case 0: break; // No segment override!
}
(((Desc->TSFlags & X86II::Op0Mask)-X86II::D8)
>> X86II::Op0Shift));
break; // Two-byte opcode prefix
- default: LLVM_UNREACHABLE("Invalid prefix!");
+ default: llvm_unreachable("Invalid prefix!");
case 0: break; // No prefix!
}
unsigned char BaseOpcode = II->getBaseOpcodeFor(Desc);
switch (Desc->TSFlags & X86II::FormMask) {
- default: LLVM_UNREACHABLE("Unknown FormMask value in X86 MachineCodeEmitter!");
+ default: llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!");
case X86II::Pseudo:
// Remember the current PC offset, this is the PIC relocation
// base address.
switch (Opcode) {
default:
- LLVM_UNREACHABLE("psuedo instructions should be removed before code emission");
+ llvm_unreachable("psuedo instructions should be removed before code emission");
break;
case TargetInstrInfo::INLINEASM: {
// We allow inline assembler nodes with empty bodies - they can
} else
emitConstant(MO.getImm(), X86InstrInfo::sizeOfImm(Desc));
} else {
- LLVM_UNREACHABLE("Unknown RawFrm operand!");
+ llvm_unreachable("Unknown RawFrm operand!");
}
}
break;
#ifndef NDEBUG
cerr << "Cannot encode: " << MI << "\n";
#endif
- llvm_unreachable();
+ llvm_unreachable(0);
}
}
return R_X86_64_64;
case X86::reloc_picrel_word:
default:
- LLVM_UNREACHABLE("unknown relocation type");
+ llvm_unreachable("unknown relocation type");
}
} else {
switch(MachineRelTy) {
case X86::reloc_absolute_dword:
case X86::reloc_picrel_word:
default:
- LLVM_UNREACHABLE("unknown relocation type");
+ llvm_unreachable("unknown relocation type");
}
}
return 0;
case R_X86_64_PC32: return -4;
break;
default:
- LLVM_UNREACHABLE("unknown x86 relocation type");
+ llvm_unreachable("unknown x86 relocation type");
}
}
return 0;
// Promote the value if needed.
switch (VA.getLocInfo()) {
- default: LLVM_UNREACHABLE("Unknown loc info!");
+ default: llvm_unreachable("Unknown loc info!");
case CCValAssign::Full: break;
case CCValAssign::SExt: {
bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
case X86II::CompareFP: handleCompareFP(I); break;
case X86II::CondMovFP: handleCondMovFP(I); break;
case X86II::SpecialFP: handleSpecialFP(I); break;
- default: LLVM_UNREACHABLE("Unknown FP Type!");
+ default: llvm_unreachable("Unknown FP Type!");
}
// Check to see if any of the values defined by this instruction are dead
MachineInstr *MI = I;
DebugLoc dl = MI->getDebugLoc();
switch (MI->getOpcode()) {
- default: LLVM_UNREACHABLE("Unknown SpecialFP instruction!");
+ default: llvm_unreachable("Unknown SpecialFP instruction!");
case X86::FpGET_ST0_32:// Appears immediately after a call returning FP type!
case X86::FpGET_ST0_64:// Appears immediately after a call returning FP type!
case X86::FpGET_ST0_80:// Appears immediately after a call returning FP type!
bool isSigned = Opcode == ISD::SMUL_LOHI;
if (!isSigned)
switch (NVT.getSimpleVT()) {
- default: LLVM_UNREACHABLE("Unsupported VT!");
+ default: llvm_unreachable("Unsupported VT!");
case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
case MVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break;
}
else
switch (NVT.getSimpleVT()) {
- default: LLVM_UNREACHABLE("Unsupported VT!");
+ default: llvm_unreachable("Unsupported VT!");
case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
unsigned LoReg, HiReg;
switch (NVT.getSimpleVT()) {
- default: LLVM_UNREACHABLE("Unsupported VT!");
+ default: llvm_unreachable("Unsupported VT!");
case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break;
case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break;
case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break;
bool isSigned = Opcode == ISD::SDIVREM;
if (!isSigned)
switch (NVT.getSimpleVT()) {
- default: LLVM_UNREACHABLE("Unsupported VT!");
+ default: llvm_unreachable("Unsupported VT!");
case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
}
else
switch (NVT.getSimpleVT()) {
- default: LLVM_UNREACHABLE("Unsupported VT!");
+ default: llvm_unreachable("Unsupported VT!");
case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
unsigned LoReg, HiReg;
unsigned ClrOpcode, SExtOpcode;
switch (NVT.getSimpleVT()) {
- default: LLVM_UNREACHABLE("Unsupported VT!");
+ default: llvm_unreachable("Unsupported VT!");
case MVT::i8:
LoReg = X86::AL; HiReg = X86::AH;
ClrOpcode = 0;
}
}
} else {
- LLVM_UNREACHABLE("Unknown argument type!");
+ llvm_unreachable("Unknown argument type!");
}
unsigned Reg = DAG.getMachineFunction().addLiveIn(VA.getLocReg(), RC);
// Promote the value if needed.
switch (VA.getLocInfo()) {
- default: LLVM_UNREACHABLE("Unknown loc info!");
+ default: llvm_unreachable("Unknown loc info!");
case CCValAssign::Full: break;
case CCValAssign::SExt:
Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
}
switch (SetCCOpcode) {
- default: LLVM_UNREACHABLE("Invalid integer condition!");
+ default: llvm_unreachable("Invalid integer condition!");
case ISD::SETEQ: return X86::COND_E;
case ISD::SETGT: return X86::COND_G;
case ISD::SETGE: return X86::COND_GE;
// 1 | 0 | 0 | X == Y
// 1 | 1 | 1 | unordered
switch (SetCCOpcode) {
- default: LLVM_UNREACHABLE("Condcode should be pre-legalized away");
+ default: llvm_unreachable("Condcode should be pre-legalized away");
case ISD::SETUEQ:
case ISD::SETEQ: return X86::COND_E;
case ISD::SETOLT: // flipped
Subtarget->is64Bit());
}
- LLVM_UNREACHABLE("Unreachable");
+ llvm_unreachable("Unreachable");
return SDValue();
}
unsigned Opc;
switch (DstTy.getSimpleVT()) {
- default: LLVM_UNREACHABLE("Invalid FP_TO_SINT to lower!");
+ default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
}
- LLVM_UNREACHABLE("Illegal FP comparison");
+ llvm_unreachable("Illegal FP comparison");
}
// Handle all other FP comparisons here.
return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
case Intrinsic::x86_mmx_psrai_d:
NewIntNo = Intrinsic::x86_mmx_psra_d;
break;
- default: LLVM_UNREACHABLE("Impossible intrinsic"); // Can't reach here.
+ default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
}
break;
}
switch (CC) {
default:
- LLVM_UNREACHABLE("Unsupported calling convention");
+ llvm_unreachable("Unsupported calling convention");
case CallingConv::C:
case CallingConv::X86_StdCall: {
// Pass 'nest' parameter in ECX.
DebugLoc dl = Op.getDebugLoc();
switch (Op.getOpcode()) {
- default: LLVM_UNREACHABLE("Unknown ovf instruction!");
+ default: llvm_unreachable("Unknown ovf instruction!");
case ISD::SADDO:
// A subtract of one will be selected as a INC. Note that INC doesn't
// set CF, so we can't do this for UADDO.
///
SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
switch (Op.getOpcode()) {
- default: LLVM_UNREACHABLE("Should not custom lower this!");
+ default: llvm_unreachable("Should not custom lower this!");
case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
// Get the X86 opcode to use.
unsigned Opc;
switch (MI->getOpcode()) {
- default: LLVM_UNREACHABLE("illegal opcode!");
+ default: llvm_unreachable("illegal opcode!");
case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
SDValue ValOp = N->getOperand(0);
switch (N->getOpcode()) {
default:
- LLVM_UNREACHABLE("Unknown shift opcode!");
+ llvm_unreachable("Unknown shift opcode!");
break;
case ISD::SHL:
if (VT == MVT::v2i64)
unsigned Opc;
unsigned Size;
switch (MI->getOpcode()) {
- default: LLVM_UNREACHABLE("Unreachable!");
+ default: llvm_unreachable("Unreachable!");
case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
switch (CC) {
- default: LLVM_UNREACHABLE("Illegal condition code!");
+ default: llvm_unreachable("Illegal condition code!");
case X86::COND_E: return X86::JE;
case X86::COND_NE: return X86::JNE;
case X86::COND_L: return X86::JL;
/// e.g. turning COND_E to COND_NE.
X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
switch (CC) {
- default: LLVM_UNREACHABLE("Illegal condition code!");
+ default: llvm_unreachable("Illegal condition code!");
case X86::COND_E: return X86::COND_NE;
case X86::COND_NE: return X86::COND_E;
case X86::COND_L: return X86::COND_GE;
} else if (RC == &X86::VR64RegClass) {
Opc = X86::MMX_MOVQ64mr;
} else {
- LLVM_UNREACHABLE("Unknown regclass");
+ llvm_unreachable("Unknown regclass");
}
return Opc;
} else if (RC == &X86::VR64RegClass) {
Opc = X86::MMX_MOVQ64rm;
} else {
- LLVM_UNREACHABLE("Unknown regclass");
+ llvm_unreachable("Unknown regclass");
}
return Opc;
case X86II::Imm16: return 2;
case X86II::Imm32: return 4;
case X86II::Imm64: return 8;
- default: LLVM_UNREACHABLE("Immediate size not set!");
+ default: llvm_unreachable("Immediate size not set!");
return 0;
}
}
} else if (RelocOp->isJTI()) {
FinalSize += sizeJumpTableAddress(false);
} else {
- LLVM_UNREACHABLE("Unknown value to relocate!");
+ llvm_unreachable("Unknown value to relocate!");
}
return FinalSize;
}
case X86II::GS:
++FinalSize;
break;
- default: LLVM_UNREACHABLE("Invalid segment!");
+ default: llvm_unreachable("Invalid segment!");
case 0: break; // No segment override!
}
case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
++FinalSize;
break; // Two-byte opcode prefix
- default: LLVM_UNREACHABLE("Invalid prefix!");
+ default: llvm_unreachable("Invalid prefix!");
case 0: break; // No prefix!
}
--NumOps;
switch (Desc->TSFlags & X86II::FormMask) {
- default: LLVM_UNREACHABLE("Unknown FormMask value in X86 MachineCodeEmitter!");
+ default: llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!");
case X86II::Pseudo:
// Remember the current PC offset, this is the PIC relocation
// base address.
} else if (MO.isImm()) {
FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
} else {
- LLVM_UNREACHABLE("Unknown RawFrm operand!");
+ llvm_unreachable("Unknown RawFrm operand!");
}
}
break;
#else // Not an i386 host
void X86CompilationCallback() {
- LLVM_UNREACHABLE("Cannot call X86CompilationCallback() on a non-x86 arch!");
+ llvm_unreachable("Cannot call X86CompilationCallback() on a non-x86 arch!");
}
#endif
}
TLSOffset -= size;
return TLSOffset;
#else
- LLVM_UNREACHABLE("Cannot allocate thread local storage on this arch!");
+ llvm_unreachable("Cannot allocate thread local storage on this arch!");
return 0;
#endif
}
default:
assert(isVirtualRegister(RegNo) && "Unknown physical register!");
- LLVM_UNREACHABLE("Register allocator hasn't allocated reg correctly yet!");
+ llvm_unreachable("Register allocator hasn't allocated reg correctly yet!");
return 0;
}
}
case X86::TAILJMPr:
case X86::TAILJMPm: break; // These are ok
default:
- LLVM_UNREACHABLE("Can only insert epilog into returning blocks");
+ llvm_unreachable("Can only insert epilog into returning blocks");
}
// Get the number of bytes to allocate from the FrameInfo
}
unsigned X86RegisterInfo::getEHExceptionRegister() const {
- LLVM_UNREACHABLE("What is the exception register");
+ llvm_unreachable("What is the exception register");
return 0;
}
unsigned X86RegisterInfo::getEHHandlerRegister() const {
- LLVM_UNREACHABLE("What is the exception handler register");
+ llvm_unreachable("What is the exception handler register");
return 0;
}
case SectionKind::RODataMergeStr:
return ".rdata$linkonce" + GV->getName();
default:
- LLVM_UNREACHABLE("Unknown section kind");
+ llvm_unreachable("Unknown section kind");
}
return NULL;
}
case GlobalValue::PrivateLinkage:
break;
case GlobalValue::GhostLinkage:
- LLVM_UNREACHABLE("Should not have any unmaterialized functions!");
+ llvm_unreachable("Should not have any unmaterialized functions!");
case GlobalValue::DLLImportLinkage:
- LLVM_UNREACHABLE("DLLImport linkage is not supported by this target!");
+ llvm_unreachable("DLLImport linkage is not supported by this target!");
case GlobalValue::DLLExportLinkage:
- LLVM_UNREACHABLE("DLLExport linkage is not supported by this target!");
+ llvm_unreachable("DLLExport linkage is not supported by this target!");
default:
- LLVM_UNREACHABLE("Unknown linkage type!");
+ llvm_unreachable("Unknown linkage type!");
}
EmitAlignment(Align, GV, 2);
O << "\t.cc_top " << CurrentFnName << ".function," << CurrentFnName << "\n";
switch (F->getLinkage()) {
- default: LLVM_UNREACHABLE("Unknown linkage type!");
+ default: llvm_unreachable("Unknown linkage type!");
case Function::InternalLinkage: // Symbols default to internal.
case Function::PrivateLinkage:
break;
if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
else
- LLVM_UNREACHABLE("not implemented");
+ llvm_unreachable("not implemented");
break;
case MachineOperand::MO_Immediate:
O << MO.getImm();
<< '_' << MO.getIndex();
break;
default:
- LLVM_UNREACHABLE("not implemented");
+ llvm_unreachable("not implemented");
}
}
if (printInstruction(MI)) {
return;
}
- LLVM_UNREACHABLE("Unhandled instruction in asm writer!");
+ llvm_unreachable("Unhandled instruction in asm writer!");
}
bool XCoreAsmPrinter::doInitialization(Module &M) {
case ISD::SUB: return ExpandADDSUB(Op.getNode(), DAG);
case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
default:
- LLVM_UNREACHABLE("unimplemented operand");
+ llvm_unreachable("unimplemented operand");
return SDValue();
}
}
SelectionDAG &DAG) {
switch (N->getOpcode()) {
default:
- LLVM_UNREACHABLE("Don't know how to custom expand this!");
+ llvm_unreachable("Don't know how to custom expand this!");
return;
case ISD::ADD:
case ISD::SUB:
GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal());
}
if (! GVar) {
- LLVM_UNREACHABLE("Thread local object not a GlobalVariable?");
+ llvm_unreachable("Thread local object not a GlobalVariable?");
return SDValue();
}
const Type *Ty = cast<PointerType>(GV->getType())->getElementType();
cerr << "Size of thread local object " << GVar->getName()
<< " is unknown\n";
#endif
- llvm_unreachable();
+ llvm_unreachable(0);
}
SDValue base = getGlobalAddressWrapper(GA, GV, DAG);
const TargetData *TD = TM.getTargetData();
// FIXME there isn't really debug info here
DebugLoc dl = CP->getDebugLoc();
if (Subtarget.isXS1A()) {
- LLVM_UNREACHABLE("Lowering of constant pool unimplemented");
+ llvm_unreachable("Lowering of constant pool unimplemented");
return SDValue();
} else {
MVT PtrVT = Op.getValueType();
SDValue XCoreTargetLowering::
LowerVAARG(SDValue Op, SelectionDAG &DAG)
{
- LLVM_UNREACHABLE("unimplemented");
+ llvm_unreachable("unimplemented");
// FIX Arguments passed by reference need a extra dereference.
SDNode *Node = Op.getNode();
DebugLoc dl = Node->getDebugLoc();
switch (CallingConv)
{
default:
- LLVM_UNREACHABLE("Unsupported calling convention");
+ llvm_unreachable("Unsupported calling convention");
case CallingConv::Fast:
case CallingConv::C:
return LowerCCCCallTo(Op, DAG, CallingConv);
// Promote the value if needed.
switch (VA.getLocInfo()) {
- default: LLVM_UNREACHABLE("Unknown loc info!");
+ default: llvm_unreachable("Unknown loc info!");
case CCValAssign::Full: break;
case CCValAssign::SExt:
Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
switch(CC)
{
default:
- LLVM_UNREACHABLE("Unsupported calling convention");
+ llvm_unreachable("Unsupported calling convention");
case CallingConv::C:
case CallingConv::Fast:
return LowerCCCArguments(Op, DAG);
cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
<< RegVT.getSimpleVT() << "\n";
#endif
- llvm_unreachable();
+ llvm_unreachable(0);
}
case MVT::i32:
unsigned VReg = RegInfo.createVirtualRegister(
static inline unsigned GetCondBranchFromCond(XCore::CondCode CC)
{
switch (CC) {
- default: LLVM_UNREACHABLE("Illegal condition code!");
+ default: llvm_unreachable("Illegal condition code!");
case XCore::COND_TRUE : return XCore::BRFT_lru6;
case XCore::COND_FALSE : return XCore::BRFF_lru6;
}
static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC)
{
switch (CC) {
- default: LLVM_UNREACHABLE("Illegal condition code!");
+ default: llvm_unreachable("Illegal condition code!");
case XCore::COND_TRUE : return XCore::COND_FALSE;
case XCore::COND_FALSE : return XCore::COND_TRUE;
}
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const
{
- LLVM_UNREACHABLE("unimplemented");
+ llvm_unreachable("unimplemented");
}
void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const
{
- LLVM_UNREACHABLE("unimplemented");
+ llvm_unreachable("unimplemented");
}
bool XCoreInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
cerr << "eliminateCallFramePseudoInstr size too big: "
<< Amount << "\n";
#endif
- llvm_unreachable();
+ llvm_unreachable(0);
}
MachineInstr *New;
.addReg(ScratchReg, RegState::Kill);
break;
default:
- LLVM_UNREACHABLE("Unexpected Opcode");
+ llvm_unreachable("Unexpected Opcode");
}
} else {
switch (MI.getOpcode()) {
.addImm(Offset);
break;
default:
- LLVM_UNREACHABLE("Unexpected Opcode");
+ llvm_unreachable("Unexpected Opcode");
}
}
} else {
.addImm(Offset);
break;
default:
- LLVM_UNREACHABLE("Unexpected Opcode");
+ llvm_unreachable("Unexpected Opcode");
}
}
// Erase old instruction.
Value *LV = new LoadInst(InitBool, InitBool->getName()+".val", CI);
InitBoolUsed = true;
switch (CI->getPredicate()) {
- default: LLVM_UNREACHABLE("Unknown ICmp Predicate!");
+ default: llvm_unreachable("Unknown ICmp Predicate!");
case ICmpInst::ICMP_ULT:
case ICmpInst::ICMP_SLT:
LV = Context->getConstantIntFalse(); // X < null -> always false
PN->getName()+".f"+utostr(FieldNo), PN);
PHIsToRewrite.push_back(std::make_pair(PN, FieldNo));
} else {
- LLVM_UNREACHABLE("Unknown usable value");
+ llvm_unreachable("Unknown usable value");
Result = 0;
}
for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i)
Elts.push_back(Context->getUndef(STy->getElementType(i)));
} else {
- LLVM_UNREACHABLE("This code is out of sync with "
+ llvm_unreachable("This code is out of sync with "
" ConstantFoldLoadThroughGEPConstantExpr");
}
Constant *Elt = Context->getUndef(ATy->getElementType());
Elts.assign(ATy->getNumElements(), Elt);
} else {
- LLVM_UNREACHABLE("This code is out of sync with "
+ llvm_unreachable("This code is out of sync with "
" ConstantFoldLoadThroughGEPConstantExpr");
}
return false;
default:
- LLVM_UNREACHABLE("Unknown type!");
+ llvm_unreachable("Unknown type!");
return false;
case Type::PointerTyID: {
return ExternalStrong;
}
- LLVM_UNREACHABLE("Unknown LinkageType.");
+ llvm_unreachable("Unknown LinkageType.");
return ExternalWeak;
}
case Internal:
switch (catG) {
case ExternalStrong:
- llvm_unreachable();
+ llvm_unreachable(0);
// fall-through
case ExternalWeak:
if (F->hasAddressTaken())
TransCache[v] = v;
return v;
}
- LLVM_UNREACHABLE("Value not handled");
+ llvm_unreachable("Value not handled");
return 0;
}
Expression::ExpressionOpcode ValueTable::getOpcode(BinaryOperator* BO) {
switch(BO->getOpcode()) {
default: // THIS SHOULD NEVER HAPPEN
- LLVM_UNREACHABLE("Binary operator with unknown opcode?");
+ llvm_unreachable("Binary operator with unknown opcode?");
case Instruction::Add: return Expression::ADD;
case Instruction::FAdd: return Expression::FADD;
case Instruction::Sub: return Expression::SUB;
if (isa<ICmpInst>(C)) {
switch (C->getPredicate()) {
default: // THIS SHOULD NEVER HAPPEN
- LLVM_UNREACHABLE("Comparison with unknown predicate?");
+ llvm_unreachable("Comparison with unknown predicate?");
case ICmpInst::ICMP_EQ: return Expression::ICMPEQ;
case ICmpInst::ICMP_NE: return Expression::ICMPNE;
case ICmpInst::ICMP_UGT: return Expression::ICMPUGT;
} else {
switch (C->getPredicate()) {
default: // THIS SHOULD NEVER HAPPEN
- LLVM_UNREACHABLE("Comparison with unknown predicate?");
+ llvm_unreachable("Comparison with unknown predicate?");
case FCmpInst::FCMP_OEQ: return Expression::FCMPOEQ;
case FCmpInst::FCMP_OGT: return Expression::FCMPOGT;
case FCmpInst::FCMP_OGE: return Expression::FCMPOGE;
Expression::ExpressionOpcode ValueTable::getOpcode(CastInst* C) {
switch(C->getOpcode()) {
default: // THIS SHOULD NEVER HAPPEN
- LLVM_UNREACHABLE("Cast operator with unknown opcode?");
+ llvm_unreachable("Cast operator with unknown opcode?");
case Instruction::Trunc: return Expression::TRUNC;
case Instruction::ZExt: return Expression::ZEXT;
case Instruction::SExt: return Expression::SEXT;
// THIS SHOULD NEVER HAPPEN
default:
- LLVM_UNREACHABLE("Binary operator with unknown opcode?");
+ llvm_unreachable("Binary operator with unknown opcode?");
return Expression::ADD;
}
}
// THIS SHOULD NEVER HAPPEN
default:
- LLVM_UNREACHABLE("Comparison with unknown predicate?");
+ llvm_unreachable("Comparison with unknown predicate?");
return Expression::ICMPEQ;
}
} else {
// THIS SHOULD NEVER HAPPEN
default:
- LLVM_UNREACHABLE("Comparison with unknown predicate?");
+ llvm_unreachable("Comparison with unknown predicate?");
return Expression::FCMPOEQ;
}
}
// THIS SHOULD NEVER HAPPEN
default:
- LLVM_UNREACHABLE("Cast operator with unknown opcode?");
+ llvm_unreachable("Cast operator with unknown opcode?");
return Expression::BITCAST;
}
}
if (VI != valueNumbering.end())
return VI->second;
else
- LLVM_UNREACHABLE("Value not numbered?");
+ llvm_unreachable("Value not numbered?");
return 0;
}
if (v == VN.lookup(*I))
return *I;
- LLVM_UNREACHABLE("No leader found, but present bit is set?");
+ llvm_unreachable("No leader found, but present bit is set?");
return 0;
}
UndefElts = UndefElts2;
if (VWidth > InVWidth) {
- LLVM_UNREACHABLE("Unimp");
+ llvm_unreachable("Unimp");
// If there are more elements in the result than there are in the source,
// then an output element is undef if the corresponding input element is
// undef.
if (UndefElts2[OutIdx/Ratio])
UndefElts.set(OutIdx);
} else if (VWidth < InVWidth) {
- LLVM_UNREACHABLE("Unimp");
+ llvm_unreachable("Unimp");
// If there are more elements in the source than there are in the result,
// then a result element is undef if all of the corresponding input
// elements are undef.
RHS = InsertNewInstBefore(new ExtractElementInst(RHS, 0U,"tmp"), *II);
switch (II->getIntrinsicID()) {
- default: LLVM_UNREACHABLE("Case stmts out of sync!");
+ default: llvm_unreachable("Case stmts out of sync!");
case Intrinsic::x86_sse_sub_ss:
case Intrinsic::x86_sse2_sub_sd:
TmpV = InsertNewInstBefore(BinaryOperator::CreateFSub(LHS, RHS,
New = CmpInst::Create(*Context, CI->getOpcode(), CI->getPredicate(),
Op0, Op1, SO->getName()+".cmp");
else {
- LLVM_UNREACHABLE("Unknown binary instruction type!");
+ llvm_unreachable("Unknown binary instruction type!");
}
return IC->InsertNewInstBefore(New, I);
}
PN->getIncomingValue(i), C, "phitmp",
NonConstBB->getTerminator());
else
- LLVM_UNREACHABLE("Unknown binop!");
+ llvm_unreachable("Unknown binop!");
AddToWorkList(cast<Instruction>(InV));
}
case ICmpInst::ICMP_SLE: return 6; // 110
// True -> 7
default:
- LLVM_UNREACHABLE("Invalid ICmp predicate!");
+ llvm_unreachable("Invalid ICmp predicate!");
return 0;
}
}
// True -> 7
default:
// Not expecting FCMP_FALSE and FCMP_TRUE;
- LLVM_UNREACHABLE("Unexpected FCmp predicate!");
+ llvm_unreachable("Unexpected FCmp predicate!");
return 0;
}
}
static Value *getICmpValue(bool sign, unsigned code, Value *LHS, Value *RHS,
LLVMContext *Context) {
switch (code) {
- default: LLVM_UNREACHABLE("Illegal ICmp code!");
+ default: llvm_unreachable("Illegal ICmp code!");
case 0: return Context->getConstantIntFalse();
case 1:
if (sign)
static Value *getFCmpValue(bool isordered, unsigned code,
Value *LHS, Value *RHS, LLVMContext *Context) {
switch (code) {
- default: LLVM_UNREACHABLE("Illegal FCmp code!");
+ default: llvm_unreachable("Illegal FCmp code!");
case 0:
if (isordered)
return new FCmpInst(*Context, FCmpInst::FCMP_ORD, LHS, RHS);
case Instruction::And: Code = LHSCode & RHSCode; break;
case Instruction::Or: Code = LHSCode | RHSCode; break;
case Instruction::Xor: Code = LHSCode ^ RHSCode; break;
- default: LLVM_UNREACHABLE("Illegal logical opcode!"); return 0;
+ default: llvm_unreachable("Illegal logical opcode!"); return 0;
}
bool isSigned = ICmpInst::isSignedPredicate(RHSICI->getPredicate()) ||
assert(LHSCst != RHSCst && "Compares not folded above?");
switch (LHSCC) {
- default: LLVM_UNREACHABLE("Unknown integer condition code!");
+ default: llvm_unreachable("Unknown integer condition code!");
case ICmpInst::ICMP_EQ:
switch (RHSCC) {
- default: LLVM_UNREACHABLE("Unknown integer condition code!");
+ default: llvm_unreachable("Unknown integer condition code!");
case ICmpInst::ICMP_EQ: // (X == 13 & X == 15) -> false
case ICmpInst::ICMP_UGT: // (X == 13 & X > 15) -> false
case ICmpInst::ICMP_SGT: // (X == 13 & X > 15) -> false
}
case ICmpInst::ICMP_NE:
switch (RHSCC) {
- default: LLVM_UNREACHABLE("Unknown integer condition code!");
+ default: llvm_unreachable("Unknown integer condition code!");
case ICmpInst::ICMP_ULT:
if (LHSCst == SubOne(RHSCst, Context)) // (X != 13 & X u< 14) -> X < 13
return new ICmpInst(*Context, ICmpInst::ICMP_ULT, Val, LHSCst);
break;
case ICmpInst::ICMP_ULT:
switch (RHSCC) {
- default: LLVM_UNREACHABLE("Unknown integer condition code!");
+ default: llvm_unreachable("Unknown integer condition code!");
case ICmpInst::ICMP_EQ: // (X u< 13 & X == 15) -> false
case ICmpInst::ICMP_UGT: // (X u< 13 & X u> 15) -> false
return ReplaceInstUsesWith(I, Context->getConstantIntFalse());
break;
case ICmpInst::ICMP_SLT:
switch (RHSCC) {
- default: LLVM_UNREACHABLE("Unknown integer condition code!");
+ default: llvm_unreachable("Unknown integer condition code!");
case ICmpInst::ICMP_EQ: // (X s< 13 & X == 15) -> false
case ICmpInst::ICMP_SGT: // (X s< 13 & X s> 15) -> false
return ReplaceInstUsesWith(I, Context->getConstantIntFalse());
break;
case ICmpInst::ICMP_UGT:
switch (RHSCC) {
- default: LLVM_UNREACHABLE("Unknown integer condition code!");
+ default: llvm_unreachable("Unknown integer condition code!");
case ICmpInst::ICMP_EQ: // (X u> 13 & X == 15) -> X == 15
case ICmpInst::ICMP_UGT: // (X u> 13 & X u> 15) -> X u> 15
return ReplaceInstUsesWith(I, RHS);
break;
case ICmpInst::ICMP_SGT:
switch (RHSCC) {
- default: LLVM_UNREACHABLE("Unknown integer condition code!");
+ default: llvm_unreachable("Unknown integer condition code!");
case ICmpInst::ICMP_EQ: // (X s> 13 & X == 15) -> X == 15
case ICmpInst::ICMP_SGT: // (X s> 13 & X s> 15) -> X s> 15
return ReplaceInstUsesWith(I, RHS);
assert(LHSCst != RHSCst && "Compares not folded above?");
switch (LHSCC) {
- default: LLVM_UNREACHABLE("Unknown integer condition code!");
+ default: llvm_unreachable("Unknown integer condition code!");
case ICmpInst::ICMP_EQ:
switch (RHSCC) {
- default: LLVM_UNREACHABLE("Unknown integer condition code!");
+ default: llvm_unreachable("Unknown integer condition code!");
case ICmpInst::ICMP_EQ:
if (LHSCst == SubOne(RHSCst, Context)) {
// (X == 13 | X == 14) -> X-13 <u 2
break;
case ICmpInst::ICMP_NE:
switch (RHSCC) {
- default: LLVM_UNREACHABLE("Unknown integer condition code!");
+ default: llvm_unreachable("Unknown integer condition code!");
case ICmpInst::ICMP_EQ: // (X != 13 | X == 15) -> X != 13
case ICmpInst::ICMP_UGT: // (X != 13 | X u> 15) -> X != 13
case ICmpInst::ICMP_SGT: // (X != 13 | X s> 15) -> X != 13
break;
case ICmpInst::ICMP_ULT:
switch (RHSCC) {
- default: LLVM_UNREACHABLE("Unknown integer condition code!");
+ default: llvm_unreachable("Unknown integer condition code!");
case ICmpInst::ICMP_EQ: // (X u< 13 | X == 14) -> no change
break;
case ICmpInst::ICMP_UGT: // (X u< 13 | X u> 15) -> (X-13) u> 2
break;
case ICmpInst::ICMP_SLT:
switch (RHSCC) {
- default: LLVM_UNREACHABLE("Unknown integer condition code!");
+ default: llvm_unreachable("Unknown integer condition code!");
case ICmpInst::ICMP_EQ: // (X s< 13 | X == 14) -> no change
break;
case ICmpInst::ICMP_SGT: // (X s< 13 | X s> 15) -> (X-13) s> 2
break;
case ICmpInst::ICMP_UGT:
switch (RHSCC) {
- default: LLVM_UNREACHABLE("Unknown integer condition code!");
+ default: llvm_unreachable("Unknown integer condition code!");
case ICmpInst::ICMP_EQ: // (X u> 13 | X == 15) -> X u> 13
case ICmpInst::ICMP_UGT: // (X u> 13 | X u> 15) -> X u> 13
return ReplaceInstUsesWith(I, LHS);
break;
case ICmpInst::ICMP_SGT:
switch (RHSCC) {
- default: LLVM_UNREACHABLE("Unknown integer condition code!");
+ default: llvm_unreachable("Unknown integer condition code!");
case ICmpInst::ICMP_EQ: // (X s> 13 | X == 15) -> X > 13
case ICmpInst::ICMP_SGT: // (X s> 13 | X s> 15) -> X > 13
return ReplaceInstUsesWith(I, LHS);
ICmpInst::Predicate Pred;
switch (I.getPredicate()) {
- default: LLVM_UNREACHABLE("Unexpected predicate!");
+ default: llvm_unreachable("Unexpected predicate!");
case FCmpInst::FCMP_UEQ:
case FCmpInst::FCMP_OEQ:
Pred = ICmpInst::ICMP_EQ;
// the compare predicate and sometimes the value. RHSC is rounded towards
// zero at this point.
switch (Pred) {
- default: LLVM_UNREACHABLE("Unexpected integer comparison!");
+ default: llvm_unreachable("Unexpected integer comparison!");
case ICmpInst::ICMP_NE: // (float)int != 4.4 --> true
return ReplaceInstUsesWith(I, Context->getConstantIntTrue());
case ICmpInst::ICMP_EQ: // (float)int == 4.4 --> false
// Simplify 'fcmp pred X, X'
if (Op0 == Op1) {
switch (I.getPredicate()) {
- default: LLVM_UNREACHABLE("Unknown predicate!");
+ default: llvm_unreachable("Unknown predicate!");
case FCmpInst::FCMP_UEQ: // True if unordered or equal
case FCmpInst::FCMP_UGE: // True if unordered, greater than, or equal
case FCmpInst::FCMP_ULE: // True if unordered, less than, or equal
// icmp's with boolean values can always be turned into bitwise operations
if (Ty == Type::Int1Ty) {
switch (I.getPredicate()) {
- default: LLVM_UNREACHABLE("Invalid icmp instruction!");
+ default: llvm_unreachable("Invalid icmp instruction!");
case ICmpInst::ICMP_EQ: { // icmp eq i1 A, B -> ~(A^B)
Instruction *Xor = BinaryOperator::CreateXor(Op0, Op1, I.getName()+"tmp");
InsertNewInstBefore(Xor, I);
// Based on the range information we know about the LHS, see if we can
// simplify this comparison. For example, (x&4) < 8 is always true.
switch (I.getPredicate()) {
- default: LLVM_UNREACHABLE("Unknown icmp opcode!");
+ default: llvm_unreachable("Unknown icmp opcode!");
case ICmpInst::ICMP_EQ:
if (Op0Max.ult(Op1Min) || Op0Min.ugt(Op1Max))
return ReplaceInstUsesWith(I, Context->getConstantIntFalse());
Value *X = DivI->getOperand(0);
switch (Pred) {
- default: LLVM_UNREACHABLE("Unhandled icmp opcode!");
+ default: llvm_unreachable("Unhandled icmp opcode!");
case ICmpInst::ICMP_EQ:
if (LoOverflow && HiOverflow)
return ReplaceInstUsesWith(ICI, Context->getConstantIntFalse());
}
default:
// TODO: Can handle more cases here.
- LLVM_UNREACHABLE("Unreachable!");
+ llvm_unreachable("Unreachable!");
break;
}
default:
// All the others use floating point so we shouldn't actually
// get here because of the check above.
- LLVM_UNREACHABLE("Unknown cast type");
+ llvm_unreachable("Unknown cast type");
case Instruction::Trunc:
DoXForm = true;
break;
assert(Res->getType() == DestTy);
switch (CI.getOpcode()) {
- default: LLVM_UNREACHABLE("Unknown cast type!");
+ default: llvm_unreachable("Unknown cast type!");
case Instruction::Trunc:
// Just replace this cast with the result.
return ReplaceInstUsesWith(CI, Res);
static Constant *GetSelectFoldableConstant(Instruction *I,
LLVMContext *Context) {
switch (I->getOpcode()) {
- default: LLVM_UNREACHABLE("This cannot happen!");
+ default: llvm_unreachable("This cannot happen!");
case Instruction::Add:
case Instruction::Sub:
case Instruction::Or:
else
return BinaryOperator::Create(BO->getOpcode(), NewSI, MatchOp);
}
- LLVM_UNREACHABLE("Shouldn't get here");
+ llvm_unreachable("Shouldn't get here");
return 0;
}
NewSel->takeName(TVI);
if (BinaryOperator *BO = dyn_cast<BinaryOperator>(TVI))
return BinaryOperator::Create(BO->getOpcode(), FalseVal, NewSel);
- LLVM_UNREACHABLE("Unknown instruction!!");
+ llvm_unreachable("Unknown instruction!!");
}
}
}
NewSel->takeName(FVI);
if (BinaryOperator *BO = dyn_cast<BinaryOperator>(FVI))
return BinaryOperator::Create(BO->getOpcode(), TrueVal, NewSel);
- LLVM_UNREACHABLE("Unknown instruction!!");
+ llvm_unreachable("Unknown instruction!!");
}
}
}
} else if (SCValue.isConstant())
Succs[SI->findCaseValue(cast<ConstantInt>(SCValue.getConstant()))] = true;
} else {
- LLVM_UNREACHABLE("SCCP: Don't know how to handle this terminator!");
+ llvm_unreachable("SCCP: Don't know how to handle this terminator!");
}
}
#ifndef NDEBUG
cerr << "Unknown terminator instruction: " << *TI;
#endif
- llvm_unreachable();
+ llvm_unreachable(0);
}
}
} else if (SwitchInst *SI = dyn_cast<SwitchInst>(I)) {
assert(isa<UndefValue>(SI->getCondition()) && "Switch should fold");
} else {
- LLVM_UNREACHABLE("Didn't fold away reference to block!");
+ llvm_unreachable("Didn't fold away reference to block!");
}
#endif
// Check that all of the users of the allocation are capable of being
// transformed.
switch (isSafeAllocaToScalarRepl(AI)) {
- default: LLVM_UNREACHABLE("Unexpected value!");
+ default: llvm_unreachable("Unexpected value!");
case 0: // Not safe to scalar replace.
break;
case 1: // Safe, but requires cleanup/canonicalizations first
continue;
}
- LLVM_UNREACHABLE("Unsupported operation!");
+ llvm_unreachable("Unsupported operation!");
}
}
case Instruction::Switch: // Should remove entry
default:
case Instruction::Ret: // Cannot happen, has no successors!
- LLVM_UNREACHABLE("Unhandled terminator instruction type in RemoveSuccessor!");
+ llvm_unreachable("Unhandled terminator instruction type in RemoveSuccessor!");
}
if (NewTI) // If it's a different instruction, replace.
// If NewBBDominatesDestBB hasn't been computed yet, do so with DF.
if (!OtherPreds.empty()) {
// FIXME: IMPLEMENT THIS!
- LLVM_UNREACHABLE("Requiring domfrontiers but not idom/domtree/domset."
+ llvm_unreachable("Requiring domfrontiers but not idom/domtree/domset."
" not implemented yet!");
}
return VM[V] = C;
} else {
- LLVM_UNREACHABLE("Unknown type of constant!");
+ llvm_unreachable("Unknown type of constant!");
}
}
unsigned NameLen, PrefixType Prefix) {
assert(NameStr && "Cannot get empty name!");
switch (Prefix) {
- default: LLVM_UNREACHABLE("Bad prefix!");
+ default: llvm_unreachable("Bad prefix!");
case NoPrefix: break;
case GlobalPrefix: OS << '@'; break;
case LabelPrefix: break;
else if (&CFP->getValueAPF().getSemantics() == &APFloat::PPCDoubleDouble)
Out << 'M';
else
- LLVM_UNREACHABLE("Unsupported floating point type");
+ llvm_unreachable("Unsupported floating point type");
// api needed to prevent premature destruction
APInt api = CFP->getValueAPF().bitcastToAPInt();
const uint64_t* p = api.getRawData();
else if (const Function *F = dyn_cast<Function>(G))
printFunction(F);
else
- LLVM_UNREACHABLE("Unknown global");
+ llvm_unreachable("Unknown global");
}
void write(const BasicBlock *BB) { printBasicBlock(BB); }
case GlobalValue::ExternalWeakLinkage: Out << "extern_weak "; break;
case GlobalValue::ExternalLinkage: break;
case GlobalValue::GhostLinkage:
- LLVM_UNREACHABLE("GhostLinkage not allowed in AsmWriter!");
+ llvm_unreachable("GhostLinkage not allowed in AsmWriter!");
}
}
static void PrintVisibility(GlobalValue::VisibilityTypes Vis,
raw_ostream &Out) {
switch (Vis) {
- default: LLVM_UNREACHABLE("Invalid visibility style!");
+ default: llvm_unreachable("Invalid visibility style!");
case GlobalValue::DefaultVisibility: break;
case GlobalValue::HiddenVisibility: Out << "hidden "; break;
case GlobalValue::ProtectedVisibility: Out << "protected "; break;
} else if (isa<InlineAsm>(this)) {
WriteAsOperand(OS, this, true, 0);
} else {
- LLVM_UNREACHABLE("Unknown value to print out!");
+ llvm_unreachable("Unknown value to print out!");
}
}
// Clean up the old call now that it has been completely upgraded.
CI->eraseFromParent();
} else {
- LLVM_UNREACHABLE("Unknown function for CallInst upgrade.");
+ llvm_unreachable("Unknown function for CallInst upgrade.");
}
return;
}
switch (NewFn->getIntrinsicID()) {
- default: LLVM_UNREACHABLE("Unknown function for CallInst upgrade.");
+ default: llvm_unreachable("Unknown function for CallInst upgrade.");
case Intrinsic::x86_mmx_psll_d:
case Intrinsic::x86_mmx_psll_q:
case Intrinsic::x86_mmx_psll_w:
break;
}
- LLVM_UNREACHABLE("Failed to cast constant expression");
+ llvm_unreachable("Failed to cast constant expression");
return 0;
}
APInt V1 = cast<ConstantInt>(C1)->getValue();
APInt V2 = cast<ConstantInt>(C2)->getValue();
switch (pred) {
- default: LLVM_UNREACHABLE("Invalid ICmp Predicate"); return 0;
+ default: llvm_unreachable("Invalid ICmp Predicate"); return 0;
case ICmpInst::ICMP_EQ:
return Context.getConstantInt(Type::Int1Ty, V1 == V2);
case ICmpInst::ICMP_NE:
APFloat C2V = cast<ConstantFP>(C2)->getValueAPF();
APFloat::cmpResult R = C1V.compare(C2V);
switch (pred) {
- default: LLVM_UNREACHABLE("Invalid FCmp Predicate"); return 0;
+ default: llvm_unreachable("Invalid FCmp Predicate"); return 0;
case FCmpInst::FCMP_FALSE: return Context.getConstantIntFalse();
case FCmpInst::FCMP_TRUE: return Context.getConstantIntTrue();
case FCmpInst::FCMP_UNO:
if (C1->getType()->isFloatingPoint()) {
int Result = -1; // -1 = unknown, 0 = known false, 1 = known true.
switch (evaluateFCmpRelation(Context, C1, C2)) {
- default: LLVM_UNREACHABLE("Unknown relation!");
+ default: llvm_unreachable("Unknown relation!");
case FCmpInst::FCMP_UNO:
case FCmpInst::FCMP_ORD:
case FCmpInst::FCMP_UEQ:
// Evaluate the relation between the two constants, per the predicate.
int Result = -1; // -1 = unknown, 0 = known false, 1 = known true.
switch (evaluateICmpRelation(Context, C1, C2, CmpInst::isSigned(pred))) {
- default: LLVM_UNREACHABLE("Unknown relational!");
+ default: llvm_unreachable("Unknown relational!");
case ICmpInst::BAD_ICMP_PREDICATE:
break; // Couldn't determine anything about these constants.
case ICmpInst::ICMP_EQ: // We know the constants are equal!
template<class ConstantClass, class TypeClass>
struct VISIBILITY_HIDDEN ConvertConstantType {
static void convert(ConstantClass *OldC, const TypeClass *NewTy) {
- LLVM_UNREACHABLE("This type cannot be converted!");
+ llvm_unreachable("This type cannot be converted!");
}
};
if (V.opcode == Instruction::FCmp)
return new CompareConstantExpr(Ty, Instruction::FCmp, V.predicate,
V.operands[0], V.operands[1]);
- LLVM_UNREACHABLE("Invalid ConstantExpr!");
+ llvm_unreachable("Invalid ConstantExpr!");
return 0;
}
};
switch (opc) {
default:
- LLVM_UNREACHABLE("Invalid cast opcode");
+ llvm_unreachable("Invalid cast opcode");
break;
case Instruction::Trunc: return getTrunc(C, Ty);
case Instruction::ZExt: return getZExt(C, Ty);
Constant *ConstantExpr::getCompareTy(unsigned short predicate,
Constant *C1, Constant *C2) {
switch (predicate) {
- default: LLVM_UNREACHABLE("Invalid CmpInst predicate");
+ default: llvm_unreachable("Invalid CmpInst predicate");
case CmpInst::FCMP_FALSE: case CmpInst::FCMP_OEQ: case CmpInst::FCMP_OGT:
case CmpInst::FCMP_OGE: case CmpInst::FCMP_OLT: case CmpInst::FCMP_OLE:
case CmpInst::FCMP_ONE: case CmpInst::FCMP_ORD: case CmpInst::FCMP_UNO:
if (C2 == From) C2 = To;
Replacement = ConstantExpr::get(getOpcode(), C1, C2);
} else {
- LLVM_UNREACHABLE("Unknown ConstantExpr type!");
+ llvm_unreachable("Unknown ConstantExpr type!");
return;
}
return CI->getCallingConv();
else if (InvokeInst *II = dyn_cast<InvokeInst>(V))
return II->getCallingConv();
- LLVM_UNREACHABLE("LLVMGetInstructionCallConv applies only to call and invoke!");
+ llvm_unreachable("LLVMGetInstructionCallConv applies only to call and invoke!");
return 0;
}
return CI->setCallingConv(CC);
else if (InvokeInst *II = dyn_cast<InvokeInst>(V))
return II->setCallingConv(CC);
- LLVM_UNREACHABLE("LLVMSetInstructionCallConv applies only to call and invoke!");
+ llvm_unreachable("LLVMSetInstructionCallConv applies only to call and invoke!");
}
void LLVMAddInstrAttribute(LLVMValueRef Instr, unsigned index,
/// Override destroyConstant to make sure it doesn't get called on
/// GlobalValue's because they shouldn't be treated like other constants.
void GlobalValue::destroyConstant() {
- LLVM_UNREACHABLE("You can't GV->destroyConstant()!");
+ llvm_unreachable("You can't GV->destroyConstant()!");
}
/// copyAttributesFrom - copy all additional attributes (those not needed to
CE->getOpcode() == Instruction::GetElementPtr))
return dyn_cast<GlobalValue>(CE->getOperand(0));
else
- LLVM_UNREACHABLE("Unsupported aliasee");
+ llvm_unreachable("Unsupported aliasee");
}
}
return 0;
/// Out-of-line ReturnInst method, put here so the C++ compiler can choose to
/// emit the vtable for the class in this translation unit.
void ReturnInst::setSuccessorV(unsigned idx, BasicBlock *NewSucc) {
- LLVM_UNREACHABLE("ReturnInst has no successors!");
+ llvm_unreachable("ReturnInst has no successors!");
}
BasicBlock *ReturnInst::getSuccessorV(unsigned idx) const {
- LLVM_UNREACHABLE("ReturnInst has no successors!");
+ llvm_unreachable("ReturnInst has no successors!");
return 0;
}
}
void UnwindInst::setSuccessorV(unsigned idx, BasicBlock *NewSucc) {
- LLVM_UNREACHABLE("UnwindInst has no successors!");
+ llvm_unreachable("UnwindInst has no successors!");
}
BasicBlock *UnwindInst::getSuccessorV(unsigned idx) const {
- LLVM_UNREACHABLE("UnwindInst has no successors!");
+ llvm_unreachable("UnwindInst has no successors!");
return 0;
}
}
void UnreachableInst::setSuccessorV(unsigned idx, BasicBlock *NewSucc) {
- LLVM_UNREACHABLE("UnwindInst has no successors!");
+ llvm_unreachable("UnwindInst has no successors!");
}
BasicBlock *UnreachableInst::getSuccessorV(unsigned idx) const {
- LLVM_UNREACHABLE("UnwindInst has no successors!");
+ llvm_unreachable("UnwindInst has no successors!");
return 0;
}
PTy = NULL;
return BitCast; // same size, no-op cast
} else {
- LLVM_UNREACHABLE("Casting pointer or non-first class to float");
+ llvm_unreachable("Casting pointer or non-first class to float");
}
} else if (const VectorType *DestPTy = dyn_cast<VectorType>(DestTy)) {
if (const VectorType *SrcPTy = dyn_cast<VectorType>(SrcTy)) {
APInt Upper(C);
uint32_t BitWidth = C.getBitWidth();
switch (pred) {
- default: LLVM_UNREACHABLE("Invalid ICmp opcode to ConstantRange ctor!");
+ default: llvm_unreachable("Invalid ICmp opcode to ConstantRange ctor!");
case ICmpInst::ICMP_EQ: Upper++; break;
case ICmpInst::ICMP_NE: Lower++; break;
case ICmpInst::ICMP_ULT: Lower = APInt::getMinValue(BitWidth); break;
OtherDT.dump();
cerr << "----- Invalid -----\n";
DT->dump();
- LLVM_UNREACHABLE("Invalid dominator info");
+ llvm_unreachable("Invalid dominator info");
}
DominanceFrontier *DF = P.getAnalysisIfAvailable<DominanceFrontier>();
OtherDF.dump();
cerr << "----- Invalid -----\n";
DF->dump();
- LLVM_UNREACHABLE("Invalid dominator info");
+ llvm_unreachable("Invalid dominator info");
}
}
// Keep track of higher level analysis used by this manager.
HigherLevelAnalysis.push_back(PRequired);
} else
- LLVM_UNREACHABLE("Unable to accomodate Required Pass");
+ llvm_unreachable("Unable to accomodate Required Pass");
}
// Set P as P's last user until someone starts using P.
cerr << "Unable to schedule '" << RequiredPass->getPassName();
cerr << "' required by '" << P->getPassName() << "'\n";
#endif
- LLVM_UNREACHABLE("Unable to schedule pass");
+ llvm_unreachable("Unable to schedule pass");
}
// Destructor
}
void Type::refineAbstractType(const DerivedType *OldTy, const Type *NewTy) {
- LLVM_UNREACHABLE("Attempting to refine a derived type!");
+ llvm_unreachable("Attempting to refine a derived type!");
}
void Type::typeBecameConcrete(const DerivedType *AbsTy) {
- LLVM_UNREACHABLE("DerivedType is already a concrete type!");
+ llvm_unreachable("DerivedType is already a concrete type!");
}
}
return true;
} else {
- LLVM_UNREACHABLE("Unknown derived type!");
+ llvm_unreachable("Unknown derived type!");
return false;
}
}
cerr << "While deleting: " << *V->getType() << " %" << V->getNameStr()
<< "\n";
#endif
- LLVM_UNREACHABLE("An asserting value handle still pointed to this"
+ llvm_unreachable("An asserting value handle still pointed to this"
" value!");
case Weak:
// Weak just goes to null, which will unlink it from the list.
getVectorElementType().getMVTString();
if (isInteger())
return "i" + utostr(getSizeInBits());
- LLVM_UNREACHABLE("Invalid MVT!");
+ llvm_unreachable("Invalid MVT!");
return "?";
case MVT::i1: return "i1";
case MVT::i8: return "i8";
switch (Ty->getTypeID()) {
default:
if (HandleUnknown) return MVT::Other;
- LLVM_UNREACHABLE("Unknown type!");
+ llvm_unreachable("Unknown type!");
return MVT::isVoid;
case Type::VoidTyID:
return MVT::isVoid;
if (!Broken) return false;
msgs << "Broken module found, ";
switch (action) {
- default: LLVM_UNREACHABLE("Unknown action");
+ default: llvm_unreachable("Unknown action");
case AbortProcessAction:
msgs << "compilation aborted!\n";
cerr << msgs.str();
"Shift return type must be same as operands!", &B);
break;
default:
- LLVM_UNREACHABLE("Unknown BinaryOperator opcode!");
+ llvm_unreachable("Unknown BinaryOperator opcode!");
}
visitInstruction(B);
projects / oota-llvm.git / commitdiff