InMips16Mode(false), InMips16HardFloat(Mips16HardFloat),
InMicroMipsMode(false), HasDSP(false), HasDSPR2(false),
AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false),
- RM(_RM), OverrideMode(NoOverride), TM(_TM), TargetTriple(TT) {
+ RM(_RM), OverrideMode(NoOverride), TM(_TM), TargetTriple(TT), JITInfo() {
std::string CPUName = CPU;
CPUName = selectMipsCPU(TT, CPUName);
#ifndef MIPSSUBTARGET_H
#define MIPSSUBTARGET_H
+#include "MipsJITInfo.h"
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Target/TargetSubtargetInfo.h"
MipsTargetMachine *TM;
Triple TargetTriple;
+
+ MipsJITInfo JITInfo;
public:
bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
AntiDepBreakMode& Mode,
/// specify which component of the system provides it. Hardware, software, and
/// hybrid implementations are all valid.
bool systemSupportsUnalignedAccess() const { return hasMips32r6(); }
+
+ MipsJITInfo *getJITInfo() { return &JITInfo; }
};
} // End llvm namespace
Subtarget(TT, CPU, FS, isLittle, RM, this),
DL(computeDataLayout(Subtarget)), InstrInfo(MipsInstrInfo::create(*this)),
FrameLowering(MipsFrameLowering::create(*this, Subtarget)),
- TLInfo(MipsTargetLowering::create(*this)), TSInfo(DL), JITInfo() {
+ TLInfo(MipsTargetLowering::create(*this)), TSInfo(DL) {
initAsmInfo();
}
#include "MipsFrameLowering.h"
#include "MipsISelLowering.h"
#include "MipsInstrInfo.h"
-#include "MipsJITInfo.h"
#include "MipsSelectionDAGInfo.h"
#include "MipsSubtarget.h"
#include "llvm/CodeGen/Passes.h"
std::unique_ptr<const MipsFrameLowering> FrameLoweringSE;
std::unique_ptr<const MipsTargetLowering> TLInfoSE;
MipsSelectionDAGInfo TSInfo;
- MipsJITInfo JITInfo;
public:
MipsTargetMachine(const Target &T, StringRef TT,
: &getSubtargetImpl()->getInstrItineraryData();
}
- MipsJITInfo *getJITInfo() override { return &JITInfo; }
+ MipsJITInfo *getJITInfo() override {
+ return Subtarget.getJITInfo();
+ }
const MipsRegisterInfo *getRegisterInfo() const override {
return &InstrInfo->getRegisterInfo();