simplify some code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43198 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAGTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAGTypes.cpp
index dca937d562fbf331762f4b658eae91fabc98efce..81f55f2ffb4fd569edb4162b48511cfa229f9607 100644 (file)
--- a/lib/CodeGen/SelectionDAG/LegalizeDAGTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAGTypes.cpp
@@ -668,7 +668,7 @@ SDOperand DAGTypeLegalizer::PromoteResult_SRL(SDNode *N) {
   // The input value must be properly zero extended.
   MVT::ValueType VT = N->getValueType(0);
   MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
-  SDOperand Res = DAG.getZeroExtendInReg(GetPromotedOp(N->getOperand(0)), VT);
+  SDOperand Res = GetPromotedZExtOp(N->getOperand(0));
   return DAG.getNode(ISD::SRL, NVT, Res, N->getOperand(1));
 }