specify triple and tighten checks using update_llc_test_checks.py

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252962 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/X86/clz.ll b/test/CodeGen/X86/clz.ll
index 6a6f5256f44d78e4d17ea5387abc1a9c2a3e8032..e50d7ec437ca92f691e599b4456be0ca3352644f 100644 (file)
--- a/test/CodeGen/X86/clz.ll
+++ b/test/CodeGen/X86/clz.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86-64 -mcpu=yonah | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
 
 declare i8 @llvm.cttz.i8(i8, i1)
 declare i16 @llvm.cttz.i16(i16, i1)
@@ -10,131 +10,132 @@ declare i32 @llvm.ctlz.i32(i32, i1)
 declare i64 @llvm.ctlz.i64(i64, i1)
 
 define i8 @cttz_i8(i8 %x)  {
+; CHECK-LABEL: cttz_i8:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movzbl %dil, %eax
+; CHECK-NEXT:    bsfl %eax, %eax
+; CHECK-NEXT:    retq
   %tmp = call i8 @llvm.cttz.i8( i8 %x, i1 true )
   ret i8 %tmp
-; CHECK-LABEL: cttz_i8:
-; CHECK: bsfl
-; CHECK-NOT: cmov
-; CHECK: ret
 }
 
 define i16 @cttz_i16(i16 %x)  {
+; CHECK-LABEL: cttz_i16:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    bsfw %di, %ax
+; CHECK-NEXT:    retq
   %tmp = call i16 @llvm.cttz.i16( i16 %x, i1 true )
   ret i16 %tmp
-; CHECK-LABEL: cttz_i16:
-; CHECK: bsfw
-; CHECK-NOT: cmov
-; CHECK: ret
 }
 
 define i32 @cttz_i32(i32 %x)  {
+; CHECK-LABEL: cttz_i32:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    bsfl %edi, %eax
+; CHECK-NEXT:    retq
   %tmp = call i32 @llvm.cttz.i32( i32 %x, i1 true )
   ret i32 %tmp
-; CHECK-LABEL: cttz_i32:
-; CHECK: bsfl
-; CHECK-NOT: cmov
-; CHECK: ret
 }
 
 define i64 @cttz_i64(i64 %x)  {
+; CHECK-LABEL: cttz_i64:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    bsfq %rdi, %rax
+; CHECK-NEXT:    retq
   %tmp = call i64 @llvm.cttz.i64( i64 %x, i1 true )
   ret i64 %tmp
-; CHECK-LABEL: cttz_i64:
-; CHECK: bsfq
-; CHECK-NOT: cmov
-; CHECK: ret
 }
 
 define i8 @ctlz_i8(i8 %x) {
-entry:
+; CHECK-LABEL: ctlz_i8:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movzbl %dil, %eax
+; CHECK-NEXT:    bsrl %eax, %eax
+; CHECK-NEXT:    xorl $7, %eax
+; CHECK-NEXT:    retq
   %tmp2 = call i8 @llvm.ctlz.i8( i8 %x, i1 true )
   ret i8 %tmp2
-; CHECK-LABEL: ctlz_i8:
-; CHECK: bsrl
-; CHECK-NOT: cmov
-; CHECK: xorl $7,
-; CHECK: ret
 }
 
 define i16 @ctlz_i16(i16 %x) {
-entry:
+; CHECK-LABEL: ctlz_i16:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    bsrw %di, %ax
+; CHECK-NEXT:    xorl $15, %eax
+; CHECK-NEXT:    retq
   %tmp2 = call i16 @llvm.ctlz.i16( i16 %x, i1 true )
   ret i16 %tmp2
-; CHECK-LABEL: ctlz_i16:
-; CHECK: bsrw
-; CHECK-NOT: cmov
-; CHECK: xorl $15,
-; CHECK: ret
 }
 
 define i32 @ctlz_i32(i32 %x) {
+; CHECK-LABEL: ctlz_i32:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    bsrl %edi, %eax
+; CHECK-NEXT:    xorl $31, %eax
+; CHECK-NEXT:    retq
   %tmp = call i32 @llvm.ctlz.i32( i32 %x, i1 true )
   ret i32 %tmp
-; CHECK-LABEL: ctlz_i32:
-; CHECK: bsrl
-; CHECK-NOT: cmov
-; CHECK: xorl $31,
-; CHECK: ret
 }
 
 define i64 @ctlz_i64(i64 %x) {
+; CHECK-LABEL: ctlz_i64:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    bsrq %rdi, %rax
+; CHECK-NEXT:    xorq $63, %rax
+; CHECK-NEXT:    retq
   %tmp = call i64 @llvm.ctlz.i64( i64 %x, i1 true )
   ret i64 %tmp
-; CHECK-LABEL: ctlz_i64:
-; CHECK: bsrq
-; CHECK-NOT: cmov
-; CHECK: xorq $63,
-; CHECK: ret
 }
 
 define i32 @ctlz_i32_cmov(i32 %n) {
-entry:
-; Generate a cmov to handle zero inputs when necessary.
 ; CHECK-LABEL: ctlz_i32_cmov:
-; CHECK: bsrl
-; CHECK: cmov
-; CHECK: xorl $31,
-; CHECK: ret
+; CHECK:       # BB#0:
+; CHECK-NEXT:    bsrl %edi, %ecx
+; CHECK-NEXT:    movl $63, %eax
+; CHECK-NEXT:    cmovnel %ecx, %eax
+; CHECK-NEXT:    xorl $31, %eax
+; CHECK-NEXT:    retq
+; Generate a cmov to handle zero inputs when necessary.
   %tmp1 = call i32 @llvm.ctlz.i32(i32 %n, i1 false)
   ret i32 %tmp1
 }
 
 define i32 @ctlz_i32_fold_cmov(i32 %n) {
-entry:
+; CHECK-LABEL: ctlz_i32_fold_cmov:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    orl $1, %edi
+; CHECK-NEXT:    bsrl %edi, %eax
+; CHECK-NEXT:    xorl $31, %eax
+; CHECK-NEXT:    retq
 ; Don't generate the cmovne when the source is known non-zero (and bsr would
 ; not set ZF).
 ; rdar://9490949
-; CHECK-LABEL: ctlz_i32_fold_cmov:
-; CHECK: bsrl
-; CHECK-NOT: cmov
-; CHECK: xorl $31,
-; CHECK: ret
   %or = or i32 %n, 1
   %tmp1 = call i32 @llvm.ctlz.i32(i32 %or, i1 false)
   ret i32 %tmp1
 }
 
 define i32 @ctlz_bsr(i32 %n) {
-entry:
+; CHECK-LABEL: ctlz_bsr:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    bsrl %edi, %eax
+; CHECK-NEXT:    retq
 ; Don't generate any xors when a 'ctlz' intrinsic is actually used to compute
 ; the most significant bit, which is what 'bsr' does natively.
-; CHECK-LABEL: ctlz_bsr:
-; CHECK: bsrl
-; CHECK-NOT: xorl
-; CHECK: ret
   %ctlz = call i32 @llvm.ctlz.i32(i32 %n, i1 true)
   %bsr = xor i32 %ctlz, 31
   ret i32 %bsr
 }
 
 define i32 @ctlz_bsr_cmov(i32 %n) {
-entry:
+; CHECK-LABEL: ctlz_bsr_cmov:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    bsrl %edi, %ecx
+; CHECK-NEXT:    movl $63, %eax
+; CHECK-NEXT:    cmovnel %ecx, %eax
+; CHECK-NEXT:    retq
 ; Same as ctlz_bsr, but ensure this happens even when there is a potential
 ; zero.
-; CHECK-LABEL: ctlz_bsr_cmov:
-; CHECK: bsrl
-; CHECK-NOT: xorl
-; CHECK: ret
   %ctlz = call i32 @llvm.ctlz.i32(i32 %n, i1 false)
   %bsr = xor i32 %ctlz, 31
   ret i32 %bsr