[AArch64] Add ARMv8.2-A new AT instruction variants

ARMv8.2-A adds new variants of the "at" (address translate) system
instruction, which take the PSTATE.PAN bit (added in ARMv8.1-A). These
are a required part of ARMv8.2-A, so no additional subtarget features
are required.

Differential Revision: http://reviews.llvm.org/D15018

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254159 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 48dfcbbf74aaab0ce6199b17e36f8afecd14ef1d..e8bea2a68b2ae52717f77e4b1177a85a5d57b650 100644 (file)
--- a/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -2513,6 +2513,20 @@ bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
     } else if (!Op.compare_lower("s12e0w")) {
       // SYS #4, C7, C8, #7
       SYS_ALIAS(4, 7, 8, 7);
+    } else if (!Op.compare_lower("s1e1rp")) {
+      if (getSTI().getFeatureBits()[AArch64::HasV8_2aOps]) {
+        // SYS #0, C7, C9, #0
+        SYS_ALIAS(0, 7, 9, 0);
+      } else {
+        return TokError("AT S1E1RP requires ARMv8.2a");
+      }
+    } else if (!Op.compare_lower("s1e1wp")) {
+      if (getSTI().getFeatureBits()[AArch64::HasV8_2aOps]) {
+        // SYS #0, C7, C9, #1
+        SYS_ALIAS(0, 7, 9, 1);
+      } else {
+        return TokError("AT S1E1WP requires ARMv8.2a");
+      }
     } else {
       return TokError("invalid operand for AT instruction");
     }

diff --git a/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp b/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp
index 3153fb2d650898c256f2c2ac5f4ad30e00e432eb..d8937b57e490158c477e7cb9d9276c657998867d 100644 (file)
--- a/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp
+++ b/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp
@@ -780,6 +780,21 @@ bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
         break;
       }
       break;
+    case 9:
+      switch (Op1Val) {
+      default:
+        break;
+      case 0:
+        if (STI.getFeatureBits()[AArch64::HasV8_2aOps]) {
+          switch (Op2Val) {
+          default:
+            break;
+          case 0: Asm = "at\ts1e1rp"; break;
+          case 1: Asm = "at\ts1e1wp"; break;
+          }
+        }
+        break;
+      }
     }
   } else if (CnVal == 8) {
     // TLBI aliases

diff --git a/lib/Target/AArch64/Utils/AArch64BaseInfo.h b/lib/Target/AArch64/Utils/AArch64BaseInfo.h
index 79fb61502d82628d857f23f3c903e89d51051908..5a6b54bbee83498f46f4b31cbd898b3f04216f8e 100644 (file)
--- a/lib/Target/AArch64/Utils/AArch64BaseInfo.h
+++ b/lib/Target/AArch64/Utils/AArch64BaseInfo.h
@@ -337,7 +337,9 @@ namespace AArch64AT {
     S12E1R = 0x63c4, // 01  100  0111  1000  100
     S12E1W = 0x63c5, // 01  100  0111  1000  101
     S12E0R = 0x63c6, // 01  100  0111  1000  110
-    S12E0W = 0x63c7  // 01  100  0111  1000  111
+    S12E0W = 0x63c7, // 01  100  0111  1000  111
+    S1E1RP = 0x43c8, // 01  000  0111  1001  000
+    S1E1WP = 0x43c9  // 01  000  0111  1001  001
   };
 
   struct ATMapper : AArch64NamedImmMapper {

diff --git a/test/MC/AArch64/armv8.2a-at.s b/test/MC/AArch64/armv8.2a-at.s
new file mode 100644 (file)
index 0000000..741f692
--- /dev/null
+++ b/test/MC/AArch64/armv8.2a-at.s
@@ -0,0 +1,9 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a < %s | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.2a < %s 2>&1 | FileCheck %s --check-prefix=ERROR
+
+  at s1e1rp, x1
+  at s1e1wp, x2
+// CHECK: at      s1e1rp, x1              // encoding: [0x01,0x79,0x08,0xd5]
+// CHECK: at      s1e1wp, x2              // encoding: [0x22,0x79,0x08,0xd5]
+// ERROR: error: AT S1E1RP requires ARMv8.2a
+// ERROR: error: AT S1E1WP requires ARMv8.2a

diff --git a/test/MC/Disassembler/AArch64/armv8.2a-at.txt b/test/MC/Disassembler/AArch64/armv8.2a-at.txt
new file mode 100644 (file)
index 0000000..81841f2
--- /dev/null
+++ b/test/MC/Disassembler/AArch64/armv8.2a-at.txt
@@ -0,0 +1,9 @@
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.2a --disassemble < %s | FileCheck %s --check-prefix=NO_V82
+
+[0x01,0x79,0x08,0xd5]
+[0x22,0x79,0x08,0xd5]
+# CHECK: at s1e1rp, x1
+# CHECK: at s1e1wp, x2
+# NO_V82: sys     #0, c7, c9, #0, x1
+# NO_V82: sys     #0, c7, c9, #1, x2