[ARM] Enable shrink-wrapping by default.

Differential Revision: http://reviews.llvm.org/D14357

rdar://problem/21942589

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253411 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMFrameLowering.h b/lib/Target/ARM/ARMFrameLowering.h
index c85d7ee33096ad9c8fde07bfc9730e17d0c89e57..66f4dfb6ef52314a13d29e4df5908c1651c65b41 100644 (file)
--- a/lib/Target/ARM/ARMFrameLowering.h
+++ b/lib/Target/ARM/ARMFrameLowering.h
@@ -57,6 +57,11 @@ public:
   void adjustForSegmentedStacks(MachineFunction &MF,
                                 MachineBasicBlock &MBB) const override;
 
   void adjustForSegmentedStacks(MachineFunction &MF,
                                 MachineBasicBlock &MBB) const override;
 

+  /// Returns true if the target will correctly handle shrink wrapping.
+  bool enableShrinkWrapping(const MachineFunction &MF) const override {
+    return true;
+  }
+

  private:
   void emitPushInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
                     const std::vector<CalleeSavedInfo> &CSI, unsigned StmOpc,
  private:
   void emitPushInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
                     const std::vector<CalleeSavedInfo> &CSI, unsigned StmOpc,

diff --git a/test/CodeGen/ARM/call-tc.ll b/test/CodeGen/ARM/call-tc.ll
index b2b6aaec8131bd1d25015e9d1448403505ecff28..8821029520fe42cb7e31d1850b4546c13e91ff36 100644 (file)
--- a/test/CodeGen/ARM/call-tc.ll
+++ b/test/CodeGen/ARM/call-tc.ll
@@ -83,9 +83,11 @@ declare void @foo() nounwind
 define void @t7() nounwind {
 entry:
 ; CHECKT2D-LABEL: t7:
 define void @t7() nounwind {
 entry:
 ; CHECKT2D-LABEL: t7:

-; CHECKT2D: blxeq _foo
-; CHECKT2D-NEXT: pop.w
-; CHECKT2D-NEXT: b.w _foo
+; CHECKT2D: it ne
+; CHECKT2D-NEXT: bne.w _foo
+; CHECKT2D-NEXT: push
+; CHECKT2D-NEXT: mov r7, sp
+; CHECKT2D-NEXT: blx _foo

   br i1 undef, label %bb, label %bb1.lr.ph
 
 bb1.lr.ph:
   br i1 undef, label %bb, label %bb1.lr.ph
 
 bb1.lr.ph:

diff --git a/test/CodeGen/ARM/fold-stack-adjust.ll b/test/CodeGen/ARM/fold-stack-adjust.ll
index 5bec6445560f223b7604a221f83f0f95316b9bfc..8944a40f311fb76def6fb1ea8b82ad1d94eef457 100644 (file)
--- a/test/CodeGen/ARM/fold-stack-adjust.ll
+++ b/test/CodeGen/ARM/fold-stack-adjust.ll
@@ -1,4 +1,6 @@
-; RUN: llc -mtriple=thumbv7-apple-none-macho < %s | FileCheck %s
+; Disable shrink-wrapping on the first test otherwise we wouldn't
+; exerce the path for PR18136.
+; RUN: llc -mtriple=thumbv7-apple-none-macho < %s -enable-shrink-wrap=false | FileCheck %s

 ; RUN: llc -mtriple=thumbv6m-apple-none-macho -disable-fp-elim < %s | FileCheck %s --check-prefix=CHECK-T1
 ; RUN: llc -mtriple=thumbv7-apple-darwin-ios -disable-fp-elim < %s | FileCheck %s --check-prefix=CHECK-IOS
 ; RUN: llc -mtriple=thumbv7--linux-gnueabi -disable-fp-elim < %s | FileCheck %s --check-prefix=CHECK-LINUX
 ; RUN: llc -mtriple=thumbv6m-apple-none-macho -disable-fp-elim < %s | FileCheck %s --check-prefix=CHECK-T1
 ; RUN: llc -mtriple=thumbv7-apple-darwin-ios -disable-fp-elim < %s | FileCheck %s --check-prefix=CHECK-IOS
 ; RUN: llc -mtriple=thumbv7--linux-gnueabi -disable-fp-elim < %s | FileCheck %s --check-prefix=CHECK-LINUX

diff --git a/test/CodeGen/ARM/ifcvt5.ll b/test/CodeGen/ARM/ifcvt5.ll
index 3aa2139cc03a9230c4956b8205c02983466e02db..9fb8abde6130d1193aae522443e6fc5de1d089a4 100644 (file)
--- a/test/CodeGen/ARM/ifcvt5.ll
+++ b/test/CodeGen/ARM/ifcvt5.ll
@@ -13,10 +13,10 @@ entry:
 
 define i32 @t1(i32 %a, i32 %b) {
 ; A8-LABEL: t1:
 
 define i32 @t1(i32 %a, i32 %b) {
 ; A8-LABEL: t1:

-; A8: poplt {r7, pc}
+; A8: bxlt lr

 
 ; SWIFT-LABEL: t1:
 
 ; SWIFT-LABEL: t1:

-; SWIFT: pop {r7, pc}
+; SWIFT: bxlt lr

 ; SWIFT: pop {r7, pc}
 entry:
        %tmp1 = icmp sgt i32 %a, 10             ; <i1> [#uses=1]
 ; SWIFT: pop {r7, pc}
 entry:
        %tmp1 = icmp sgt i32 %a, 10             ; <i1> [#uses=1]

diff --git a/test/CodeGen/ARM/ifcvt6.ll b/test/CodeGen/ARM/ifcvt6.ll
index 78901930e4b269bb51ba19a7d603274415ddae14..668069751cf1b8b00b7f9141d2407f3b6812fcab 100644 (file)
--- a/test/CodeGen/ARM/ifcvt6.ll
+++ b/test/CodeGen/ARM/ifcvt6.ll
@@ -3,7 +3,7 @@
 define void @foo(i32 %X, i32 %Y) {
 entry:
 ; CHECK: cmpne
 define void @foo(i32 %X, i32 %Y) {
 entry:
 ; CHECK: cmpne

-; CHECK: pophi
+; CHECK: bxhi lr

        %tmp1 = icmp ult i32 %X, 4              ; <i1> [#uses=1]
        %tmp4 = icmp eq i32 %Y, 0               ; <i1> [#uses=1]
        %tmp7 = or i1 %tmp4, %tmp1              ; <i1> [#uses=1]
        %tmp1 = icmp ult i32 %X, 4              ; <i1> [#uses=1]
        %tmp4 = icmp eq i32 %Y, 0               ; <i1> [#uses=1]
        %tmp7 = or i1 %tmp4, %tmp1              ; <i1> [#uses=1]

diff --git a/test/CodeGen/ARM/ifcvt8.ll b/test/CodeGen/ARM/ifcvt8.ll
index ca9a5c63cda67c1af7f1c05df9f2218e2fe731ad..e8b7f6926396ec54123a9fc285439551c78777e4 100644 (file)
--- a/test/CodeGen/ARM/ifcvt8.ll
+++ b/test/CodeGen/ARM/ifcvt8.ll
@@ -5,7 +5,9 @@
 declare void @abort()
 
 define fastcc void @t(%struct.SString* %word, i8 signext  %c) {
 declare void @abort()
 
 define fastcc void @t(%struct.SString* %word, i8 signext  %c) {

-; CHECK: popne
+; CHECK-NOT: pop
+; CHECK: bxne
+; CHECK-NOT: pop

 entry:
        %tmp1 = icmp eq %struct.SString* %word, null            ; <i1> [#uses=1]
        br i1 %tmp1, label %cond_true, label %cond_false
 entry:
        %tmp1 = icmp eq %struct.SString* %word, null            ; <i1> [#uses=1]
        br i1 %tmp1, label %cond_true, label %cond_false

diff --git a/test/CodeGen/ARM/machine-cse-cmp.ll b/test/CodeGen/ARM/machine-cse-cmp.ll
index 1f92ff4e11923696a8271102a5943e0ddb2636b5..611cba6ed1fcb63ef252a183d9dbc8c0d472592b 100644 (file)
--- a/test/CodeGen/ARM/machine-cse-cmp.ll
+++ b/test/CodeGen/ARM/machine-cse-cmp.ll
@@ -27,7 +27,7 @@ define void @f2() nounwind ssp {
 entry:
 ; CHECK-LABEL: f2:
 ; CHECK: cmp
 entry:
 ; CHECK-LABEL: f2:
 ; CHECK: cmp

-; CHECK: poplt
+; CHECK: bxlt

 ; CHECK-NOT: cmp
 ; CHECK: movle
   %0 = load i32, i32* @foo, align 4
 ; CHECK-NOT: cmp
 ; CHECK: movle
   %0 = load i32, i32* @foo, align 4

diff --git a/test/CodeGen/ARM/thumb-alignment.ll b/test/CodeGen/ARM/thumb-alignment.ll
index c11d4b6da3c994d6ff06ed39245a0b5b4a388ae8..b9ddfbb714d1add958c5864081f9a31bf19f9809 100644 (file)
--- a/test/CodeGen/ARM/thumb-alignment.ll
+++ b/test/CodeGen/ARM/thumb-alignment.ll
@@ -23,7 +23,7 @@ define i32* @bar() {
 
 ; CHECK: .globl        baz
 ; CHECK-NEXT: .align   2
 
 ; CHECK: .globl        baz
 ; CHECK-NEXT: .align   2

-; CHECK: adr.w
+; CHECK: tbb

 define i32 @baz() {
   %1 = load i32, i32* @c, align 4
   switch i32 %1, label %7 [
 define i32 @baz() {
   %1 = load i32, i32* @c, align 4
   switch i32 %1, label %7 [

diff --git a/test/CodeGen/Thumb2/ifcvt-compare.ll b/test/CodeGen/Thumb2/ifcvt-compare.ll
index 8af139a5ef6ed5abd2e858e089ec6749ce7d2ba5..7b5ce4fa3f5f33b15344b6057e11a432b2483bb0 100644 (file)
--- a/test/CodeGen/Thumb2/ifcvt-compare.ll
+++ b/test/CodeGen/Thumb2/ifcvt-compare.ll
@@ -19,7 +19,8 @@ f:
 define void @f1(i32 %x) optsize {
   ; CHECK-LABEL: f1:
   ; CHECK: cmp r0, #1
 define void @f1(i32 %x) optsize {
   ; CHECK-LABEL: f1:
   ; CHECK: cmp r0, #1

-  ; CHECK: it eq
+  ; CHECK: it ne
+  ; CHECK-NEXT: bxne lr

   %p = icmp eq i32 %x, 1
   br i1 %p, label %t, label %f
 
   %p = icmp eq i32 %x, 1
   br i1 %p, label %t, label %f
 


@@ -34,7 +35,8 @@ f:
 define void @f2(i32 %x) {
   ; CHECK-LABEL: f2:
   ; CHECK: cmp r0, #0
 define void @f2(i32 %x) {
   ; CHECK-LABEL: f2:
   ; CHECK: cmp r0, #0

-  ; CHECK: it eq
+  ; CHECK: it ne
+  ; CHECK-NEXT: bxne lr

   %p = icmp eq i32 %x, 0
   br i1 %p, label %t, label %f
 
   %p = icmp eq i32 %x, 0
   br i1 %p, label %t, label %f
 

diff --git a/test/CodeGen/Thumb2/thumb2-ifcvt1.ll b/test/CodeGen/Thumb2/thumb2-ifcvt1.ll
index 09def7372f5bad22659bd5e59c9a5a071cba4123..eb48ffb7d80e5c95781a379e7fdd44950dc7862c 100644 (file)
--- a/test/CodeGen/Thumb2/thumb2-ifcvt1.ll
+++ b/test/CodeGen/Thumb2/thumb2-ifcvt1.ll
@@ -72,9 +72,10 @@ entry:
 define void @t3(i32 %a, i32 %b) nounwind {
 entry:
 ; CHECK-LABEL: t3:
 define void @t3(i32 %a, i32 %b) nounwind {
 entry:
 ; CHECK-LABEL: t3:

-; CHECK: itt ge
-; CHECK: movge r0, r1
-; CHECK: blge  {{_?}}foo
+; CHECK: it lt
+; CHECK-NEXT: bxlt lr
+; CHECK: mov r0, r1
+; CHECK: bl  {{_?}}foo

        %tmp1 = icmp sgt i32 %a, 10             ; <i1> [#uses=1]
        br i1 %tmp1, label %cond_true, label %UnifiedReturnBlock
 
        %tmp1 = icmp sgt i32 %a, 10             ; <i1> [#uses=1]
        br i1 %tmp1, label %cond_true, label %UnifiedReturnBlock
 

diff --git a/test/CodeGen/Thumb2/thumb2-ifcvt2.ll b/test/CodeGen/Thumb2/thumb2-ifcvt2.ll
index 1d2ba0008be82a0f71f2667c15de661dca86e414..4a76e100b65804ff92aacc11cd2598b04c42b645 100644 (file)
--- a/test/CodeGen/Thumb2/thumb2-ifcvt2.ll
+++ b/test/CodeGen/Thumb2/thumb2-ifcvt2.ll
@@ -8,7 +8,7 @@ entry:
 ; CHECK: it ne
 ; CHECK: cmpne
 ; CHECK: it hi
 ; CHECK: it ne
 ; CHECK: cmpne
 ; CHECK: it hi

-; CHECK: pophi {r7, pc}
+; CHECK: bxhi lr

        %tmp1 = icmp ult i32 %X, 4              ; <i1> [#uses=1]
        %tmp4 = icmp eq i32 %Y, 0               ; <i1> [#uses=1]
        %tmp7 = or i1 %tmp4, %tmp1              ; <i1> [#uses=1]
        %tmp1 = icmp ult i32 %X, 4              ; <i1> [#uses=1]
        %tmp4 = icmp eq i32 %Y, 0               ; <i1> [#uses=1]
        %tmp7 = or i1 %tmp4, %tmp1              ; <i1> [#uses=1]


@@ -69,7 +69,7 @@ define fastcc void @t1(%struct.SString* %word, i8 signext  %c) {
 entry:
 ; CHECK-LABEL: t1:
 ; CHECK: it ne
 entry:
 ; CHECK-LABEL: t1:
 ; CHECK: it ne

-; CHECK: popne {r7, pc}
+; CHECK: bxne lr

        %tmp1 = icmp eq %struct.SString* %word, null            ; <i1> [#uses=1]
        br i1 %tmp1, label %cond_true, label %cond_false
 
        %tmp1 = icmp eq %struct.SString* %word, null            ; <i1> [#uses=1]
        br i1 %tmp1, label %cond_true, label %cond_false
 

diff --git a/test/CodeGen/Thumb2/v8_IT_5.ll b/test/CodeGen/Thumb2/v8_IT_5.ll
index 08df9e699b1bfcf50a665d0e48893c284ebc862f..6a7a7a0b0aa05668f3001474dd93e69408317a0d 100644 (file)
--- a/test/CodeGen/Thumb2/v8_IT_5.ll
+++ b/test/CodeGen/Thumb2/v8_IT_5.ll
@@ -9,7 +9,7 @@
 ; CHECK-NEXT: b
 ; CHECK: [[JUMPTARGET]]:{{.*}}%if.else173
 ; CHECK-NEXT: mov.w
 ; CHECK-NEXT: b
 ; CHECK: [[JUMPTARGET]]:{{.*}}%if.else173
 ; CHECK-NEXT: mov.w

-; CHECK-NEXT: pop
+; CHECK-NEXT: bx lr

 ; CHECK-NEXT: %if.else145
 ; CHECK-NEXT: mov.w
 
 ; CHECK-NEXT: %if.else145
 ; CHECK-NEXT: mov.w