git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140443
91177308-0d34-0410-b5e6-
96231b3b80d8
*.pyc
# vim swap files
.*.swp
*.pyc
# vim swap files
.*.swp
#==============================================================================#
# Explicit files to ignore (only matches one).
#==============================================================================#
.gitusers
#==============================================================================#
# Explicit files to ignore (only matches one).
#==============================================================================#
.gitusers
autom4te.cache
cscope.files
cscope.out
autom4te.cache
cscope.files
cscope.out
addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
+ if (HasMips64)
+ addRegisterClass(MVT::i64, Mips::CPU64RegsRegisterClass);
+
// When dealing with single precision only, use libcalls
if (!Subtarget->isSingleFloat()) {
if (HasMips64)
// When dealing with single precision only, use libcalls
if (!Subtarget->isSingleFloat()) {
if (HasMips64)
if (RegVT == MVT::i32)
RC = Mips::CPURegsRegisterClass;
if (RegVT == MVT::i32)
RC = Mips::CPURegsRegisterClass;
+ else if (RegVT == MVT::i64)
+ RC = Mips::CPU64RegsRegisterClass;
else if (RegVT == MVT::f32)
RC = Mips::FGR32RegisterClass;
else if (RegVT == MVT::f64) {
else if (RegVT == MVT::f32)
RC = Mips::FGR32RegisterClass;
else if (RegVT == MVT::f64) {
//===----------------------------------------------------------------------===//
include "MipsInstrFPU.td"
//===----------------------------------------------------------------------===//
include "MipsInstrFPU.td"
+include "Mips64InstrInfo.td"