x86 atomic: optimize a.store(reg op a.load(acquire), release)
authorJF Bastien <jfb@google.com>
Wed, 5 Aug 2015 21:04:59 +0000 (21:04 +0000)
committerJF Bastien <jfb@google.com>
Wed, 5 Aug 2015 21:04:59 +0000 (21:04 +0000)
Summary: PR24191 finds that the expected memory-register operations aren't generated when relaxed { load ; modify ; store } is used. This is similar to PR17281 which was addressed in D4796, but only for memory-immediate operations (and for memory orderings up to acquire and release). This patch also handles some floating-point operations.

Reviewers: reames, kcc, dvyukov, nadav, morisset, chandlerc, t.p.northover, pete

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11382

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244128 91177308-0d34-0410-b5e6-96231b3b80d8


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