tablegen(LLVM MipsGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM MipsGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM MipsGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM MipsGenCodeEmitter.inc -gen-emitter)
tablegen(LLVM MipsGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
tablegen(LLVM MipsGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM MipsGenDAGISel.inc -gen-dag-isel)
tablegen(LLVM MipsGenCallingConv.inc -gen-callingconv)
tablegen(LLVM MipsGenSubtargetInfo.inc -gen-subtarget)
+tablegen(LLVM MipsGenEDInfo.inc -gen-enhanced-disassembly-info)
add_public_tablegen_target(MipsCommonTableGen)
add_llvm_target(MipsCodeGen
)
add_subdirectory(InstPrinter)
+add_subdirectory(Disassembler)
add_subdirectory(TargetInfo)
add_subdirectory(MCTargetDesc)
add_subdirectory(AsmParser)
--- /dev/null
+include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. ${CMAKE_CURRENT_SOURCE_DIR}/.. )
+
+add_llvm_library(LLVMMipsDisassembler
+ MipsDisassembler.cpp
+ )
+
+# workaround for hanging compilation on MSVC9 and 10
+if( MSVC_VERSION EQUAL 1400 OR MSVC_VERSION EQUAL 1500 OR MSVC_VERSION EQUAL 1600 )
+set_property(
+ SOURCE MipsDisassembler.cpp
+ PROPERTY COMPILE_FLAGS "/Od"
+ )
+endif()
+
+add_dependencies(LLVMMipsDisassembler MipsCommonTableGen)
+include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. ${CMAKE_CURRENT_SOURCE_DIR}/.. )
+
+add_llvm_library(LLVMMipsDisassembler
+ MipsDisassembler.cpp
+ )
+
+# workaround for hanging compilation on MSVC9 and 10
+if( MSVC_VERSION EQUAL 1400 OR MSVC_VERSION EQUAL 1500 OR MSVC_VERSION EQUAL 1600 )
+set_property(
+ SOURCE MipsDisassembler.cpp
+ PROPERTY COMPILE_FLAGS "/Od"
+ )
+endif()
+
+add_dependencies(LLVMMipsDisassembler MipsCommonTableGen)
--- /dev/null
+;===- ./lib/Target/Mips/Disassembler/LLVMBuild.txt --------------*- Conf -*--===;
+;
+; The LLVM Compiler Infrastructure
+;
+; This file is distributed under the University of Illinois Open Source
+; License. See LICENSE.TXT for details.
+;
+;===------------------------------------------------------------------------===;
+;
+; This is an LLVMBuild description file for the components in this subdirectory.
+;
+; For more information on the LLVMBuild system, please see:
+;
+; http://llvm.org/docs/LLVMBuild.html
+;
+;===------------------------------------------------------------------------===;
+
+[component_0]
+type = Library
+name = MipsDisassembler
+parent = Mips
+required_libraries = MC Support MipsInfo
+add_to_library_groups = Mips
+;===- ./lib/Target/Mips/Disassembler/LLVMBuild.txt --------------*- Conf -*--===;
+;
+; The LLVM Compiler Infrastructure
+;
+; This file is distributed under the University of Illinois Open Source
+; License. See LICENSE.TXT for details.
+;
+;===------------------------------------------------------------------------===;
+;
+; This is an LLVMBuild description file for the components in this subdirectory.
+;
+; For more information on the LLVMBuild system, please see:
+;
+; http://llvm.org/docs/LLVMBuild.html
+;
+;===------------------------------------------------------------------------===;
+
+[component_0]
+type = Library
+name = MipsDisassembler
+parent = Mips
+required_libraries = MC Support MipsInfo
+add_to_library_groups = Mips
--- /dev/null
+##===- lib/Target/Mips/Disassembler/Makefile ----------------*- Makefile -*-===##
+#
+# The LLVM Compiler Infrastructure
+#
+# This file is distributed under the University of Illinois Open Source
+# License. See LICENSE.TXT for details.
+#
+##===----------------------------------------------------------------------===##
+
+LEVEL = ../../../..
+LIBRARYNAME = LLVMMipsDisassembler
+
+# Hack: we need to include 'main' Mips target directory to grab private headers
+CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
+
+include $(LEVEL)/Makefile.common
+##===- lib/Target/Mips/Disassembler/Makefile ----------------*- Makefile -*-===##
+#
+# The LLVM Compiler Infrastructure
+#
+# This file is distributed under the University of Illinois Open Source
+# License. See LICENSE.TXT for details.
+#
+##===----------------------------------------------------------------------===##
+
+LEVEL = ../../../..
+LIBRARYNAME = LLVMMipsDisassembler
+
+# Hack: we need to include 'main' Mips target directory to grab private headers
+CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
+
+include $(LEVEL)/Makefile.common
--- /dev/null
+//===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file is part of the Mips Disassembler.
+//
+//===----------------------------------------------------------------------===//
+
+#include "Mips.h"
+#include "MipsSubtarget.h"
+#include "llvm/MC/EDInstInfo.h"
+#include "llvm/MC/MCDisassembler.h"
+#include "llvm/Support/MemoryObject.h"
+#include "llvm/Support/TargetRegistry.h"
+#include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/Support/MathExtras.h"
+
+
+#include "MipsGenEDInfo.inc"
+
+using namespace llvm;
+
+typedef MCDisassembler::DecodeStatus DecodeStatus;
+
+/// MipsDisassembler - a disasembler class for Mips32.
+class MipsDisassembler : public MCDisassembler {
+public:
+ /// Constructor - Initializes the disassembler.
+ ///
+ MipsDisassembler(const MCSubtargetInfo &STI, bool bigEndian) :
+ MCDisassembler(STI), isBigEndian(bigEndian) {
+ }
+
+ ~MipsDisassembler() {
+ }
+
+ /// getInstruction - See MCDisassembler.
+ DecodeStatus getInstruction(MCInst &instr,
+ uint64_t &size,
+ const MemoryObject ®ion,
+ uint64_t address,
+ raw_ostream &vStream,
+ raw_ostream &cStream) const;
+
+ /// getEDInfo - See MCDisassembler.
+ const EDInstInfo *getEDInfo() const;
+
+private:
+ bool isBigEndian;
+};
+
+
+/// Mips64Disassembler - a disasembler class for Mips64.
+class Mips64Disassembler : public MCDisassembler {
+public:
+ /// Constructor - Initializes the disassembler.
+ ///
+ Mips64Disassembler(const MCSubtargetInfo &STI, bool bigEndian) :
+ MCDisassembler(STI), isBigEndian(bigEndian) {
+ }
+
+ ~Mips64Disassembler() {
+ }
+
+ /// getInstruction - See MCDisassembler.
+ DecodeStatus getInstruction(MCInst &instr,
+ uint64_t &size,
+ const MemoryObject ®ion,
+ uint64_t address,
+ raw_ostream &vStream,
+ raw_ostream &cStream) const;
+
+ /// getEDInfo - See MCDisassembler.
+ const EDInstInfo *getEDInfo() const;
+
+private:
+ bool isBigEndian;
+};
+
+const EDInstInfo *MipsDisassembler::getEDInfo() const {
+ return instInfoMips;
+}
+
+const EDInstInfo *Mips64Disassembler::getEDInfo() const {
+ return instInfoMips;
+}
+
+// Decoder tables for Mips register
+static const unsigned CPURegsTable[] = {
+ Mips::ZERO, Mips::AT, Mips::V0, Mips::V1,
+ Mips::A0, Mips::A1, Mips::A2, Mips::A3,
+ Mips::T0, Mips::T1, Mips::T2, Mips::T3,
+ Mips::T4, Mips::T5, Mips::T6, Mips::T7,
+ Mips::S0, Mips::S1, Mips::S2, Mips::S3,
+ Mips::S4, Mips::S5, Mips::S6, Mips::S7,
+ Mips::T8, Mips::T9, Mips::K0, Mips::K1,
+ Mips::GP, Mips::SP, Mips::FP, Mips::RA
+};
+
+static const unsigned FGR32RegsTable[] = {
+ Mips::F0, Mips::F1, Mips::F2, Mips::F3,
+ Mips::F4, Mips::F5, Mips::F6, Mips::F7,
+ Mips::F8, Mips::F9, Mips::F10, Mips::F11,
+ Mips::F12, Mips::F13, Mips::F14, Mips::F15,
+ Mips::F16, Mips::F17, Mips::F18, Mips::F18,
+ Mips::F20, Mips::F21, Mips::F22, Mips::F23,
+ Mips::F24, Mips::F25, Mips::F26, Mips::F27,
+ Mips::F28, Mips::F29, Mips::F30, Mips::F31
+};
+
+static const unsigned CPU64RegsTable[] = {
+ Mips::ZERO_64, Mips::AT_64, Mips::V0_64, Mips::V1_64,
+ Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
+ Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64,
+ Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64,
+ Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64,
+ Mips::S4_64, Mips::S5_64, Mips::S6_64, Mips::S7_64,
+ Mips::T8_64, Mips::T9_64, Mips::K0_64, Mips::K1_64,
+ Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64
+};
+
+static const unsigned FGR64RegsTable[] = {
+ Mips::D0_64, Mips::D1_64, Mips::D2_64, Mips::D3_64,
+ Mips::D4_64, Mips::D5_64, Mips::D6_64, Mips::D7_64,
+ Mips::D8_64, Mips::D9_64, Mips::D10_64, Mips::D11_64,
+ Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
+ Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64,
+ Mips::D20_64, Mips::D21_64, Mips::D22_64, Mips::D23_64,
+ Mips::D24_64, Mips::D25_64, Mips::D26_64, Mips::D27_64,
+ Mips::D28_64, Mips::D29_64, Mips::D30_64, Mips::D31_64
+};
+
+static const unsigned AFGR64RegsTable[] = {
+ Mips::D0, Mips::D1, Mips::D2, Mips::D3,
+ Mips::D4, Mips::D5, Mips::D6, Mips::D7,
+ Mips::D8, Mips::D9, Mips::D10, Mips::D11,
+ Mips::D12, Mips::D13, Mips::D14, Mips::D15
+};
+
+// Forward declare these because the autogenerated code will reference them.
+// Definitions are further down.
+static DecodeStatus DecodeCPU64RegsRegisterClass(MCInst &Inst,
+ unsigned RegNo,
+ uint64_t Address,
+ const void *Decoder);
+
+static DecodeStatus DecodeCPURegsRegisterClass(MCInst &Inst,
+ unsigned RegNo,
+ uint64_t Address,
+ const void *Decoder);
+
+static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
+ unsigned RegNo,
+ uint64_t Address,
+ const void *Decoder);
+
+static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
+ unsigned RegNo,
+ uint64_t Address,
+ const void *Decoder);
+
+static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
+ unsigned RegNo,
+ uint64_t Address,
+ const void *Decoder);
+
+static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
+ unsigned Insn,
+ uint64_t Address,
+ const void *Decoder);
+
+static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
+ unsigned RegNo,
+ uint64_t Address,
+ const void *Decoder);
+
+static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst,
+ unsigned Insn,
+ uint64_t Address,
+ const void *Decoder);
+
+static DecodeStatus DecodeBranchTarget(MCInst &Inst,
+ unsigned Offset,
+ uint64_t Address,
+ const void *Decoder);
+
+static DecodeStatus DecodeBC1(MCInst &Inst,
+ unsigned Insn,
+ uint64_t Address,
+ const void *Decoder);
+
+
+static DecodeStatus DecodeJumpTarget(MCInst &Inst,
+ unsigned Insn,
+ uint64_t Address,
+ const void *Decoder);
+
+static DecodeStatus DecodeMem(MCInst &Inst,
+ unsigned Insn,
+ uint64_t Address,
+ const void *Decoder);
+
+static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
+ uint64_t Address,
+ const void *Decoder);
+
+static DecodeStatus DecodeSimm16(MCInst &Inst,
+ unsigned Insn,
+ uint64_t Address,
+ const void *Decoder);
+
+static DecodeStatus DecodeCondCode(MCInst &Inst,
+ unsigned Insn,
+ uint64_t Address,
+ const void *Decoder);
+
+static DecodeStatus DecodeInsSize(MCInst &Inst,
+ unsigned Insn,
+ uint64_t Address,
+ const void *Decoder);
+
+static DecodeStatus DecodeExtSize(MCInst &Inst,
+ unsigned Insn,
+ uint64_t Address,
+ const void *Decoder);
+
+namespace llvm {
+extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
+ TheMips64elTarget;
+}
+
+static MCDisassembler *createMipsDisassembler(
+ const Target &T,
+ const MCSubtargetInfo &STI) {
+ return new MipsDisassembler(STI,true);
+}
+
+static MCDisassembler *createMipselDisassembler(
+ const Target &T,
+ const MCSubtargetInfo &STI) {
+ return new MipsDisassembler(STI,false);
+}
+
+static MCDisassembler *createMips64Disassembler(
+ const Target &T,
+ const MCSubtargetInfo &STI) {
+ return new Mips64Disassembler(STI,true);
+}
+
+static MCDisassembler *createMips64elDisassembler(
+ const Target &T,
+ const MCSubtargetInfo &STI) {
+ return new Mips64Disassembler(STI, false);
+}
+
+extern "C" void LLVMInitializeMipsDisassembler() {
+ // Register the disassembler.
+ TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
+ createMipsDisassembler);
+ TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
+ createMipselDisassembler);
+ TargetRegistry::RegisterMCDisassembler(TheMips64Target,
+ createMips64Disassembler);
+ TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
+ createMips64elDisassembler);
+}
+
+
+#include "MipsGenDisassemblerTables.inc"
+
+ /// readInstruction - read four bytes from the MemoryObject
+ /// and return 32 bit word sorted according to the given endianess
+static DecodeStatus readInstruction32(const MemoryObject ®ion,
+ uint64_t address,
+ uint64_t &size,
+ uint32_t &insn,
+ bool isBigEndian) {
+ uint8_t Bytes[4];
+
+ // We want to read exactly 4 Bytes of data.
+ if (region.readBytes(address, 4, (uint8_t*)Bytes, NULL) == -1) {
+ size = 0;
+ return MCDisassembler::Fail;
+ }
+
+ if (isBigEndian) {
+ // Encoded as a big-endian 32-bit word in the stream.
+ insn = (Bytes[3] << 0) |
+ (Bytes[2] << 8) |
+ (Bytes[1] << 16) |
+ (Bytes[0] << 24);
+ }
+ else {
+ // Encoded as a small-endian 32-bit word in the stream.
+ insn = (Bytes[0] << 0) |
+ (Bytes[1] << 8) |
+ (Bytes[2] << 16) |
+ (Bytes[3] << 24);
+ }
+
+ return MCDisassembler::Success;
+}
+
+DecodeStatus
+MipsDisassembler::getInstruction(MCInst &instr,
+ uint64_t &Size,
+ const MemoryObject &Region,
+ uint64_t Address,
+ raw_ostream &vStream,
+ raw_ostream &cStream) const {
+ uint32_t Insn;
+
+ DecodeStatus Result = readInstruction32(Region, Address, Size,
+ Insn, isBigEndian);
+ if (Result == MCDisassembler::Fail)
+ return MCDisassembler::Fail;
+
+ // Calling the auto-generated decoder function.
+ Result = decodeMipsInstruction32(instr, Insn, Address, this, STI);
+ if (Result != MCDisassembler::Fail) {
+ Size = 4;
+ return Result;
+ }
+
+ return MCDisassembler::Fail;
+}
+
+DecodeStatus
+Mips64Disassembler::getInstruction(MCInst &instr,
+ uint64_t &Size,
+ const MemoryObject &Region,
+ uint64_t Address,
+ raw_ostream &vStream,
+ raw_ostream &cStream) const {
+ uint32_t Insn;
+
+ DecodeStatus Result = readInstruction32(Region, Address, Size,
+ Insn, isBigEndian);
+ if (Result == MCDisassembler::Fail)
+ return MCDisassembler::Fail;
+
+ // Calling the auto-generated decoder function.
+ Result = decodeMips64Instruction32(instr, Insn, Address, this, STI);
+ if (Result != MCDisassembler::Fail) {
+ Size = 4;
+ return Result;
+ }
+ // If we fail to decode in Mips64 decoder space we can try in Mips32
+ Result = decodeMipsInstruction32(instr, Insn, Address, this, STI);
+ if (Result != MCDisassembler::Fail) {
+ Size = 4;
+ return Result;
+ }
+
+ return MCDisassembler::Fail;
+}
+
+static DecodeStatus DecodeCPU64RegsRegisterClass(MCInst &Inst,
+ unsigned RegNo,
+ uint64_t Address,
+ const void *Decoder) {
+
+ if (RegNo > 31)
+ return MCDisassembler::Fail;
+
+ Inst.addOperand(MCOperand::CreateReg(CPU64RegsTable[RegNo]));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeCPURegsRegisterClass(MCInst &Inst,
+ unsigned RegNo,
+ uint64_t Address,
+ const void *Decoder) {
+ if (RegNo > 31)
+ return MCDisassembler::Fail;
+
+ Inst.addOperand(MCOperand::CreateReg(CPURegsTable[RegNo]));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
+ unsigned RegNo,
+ uint64_t Address,
+ const void *Decoder) {
+ if (RegNo > 31)
+ return MCDisassembler::Fail;
+
+ Inst.addOperand(MCOperand::CreateReg(FGR64RegsTable[RegNo]));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
+ unsigned RegNo,
+ uint64_t Address,
+ const void *Decoder) {
+ if (RegNo > 31)
+ return MCDisassembler::Fail;
+
+ Inst.addOperand(MCOperand::CreateReg(FGR32RegsTable[RegNo]));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
+ unsigned RegNo,
+ uint64_t Address,
+ const void *Decoder) {
+ Inst.addOperand(MCOperand::CreateReg(RegNo));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeMem(MCInst &Inst,
+ unsigned Insn,
+ uint64_t Address,
+ const void *Decoder) {
+ int Offset = SignExtend32<16>(Insn & 0xffff);
+ int Reg = (int)fieldFromInstruction32(Insn, 16, 5);
+ int Base = (int)fieldFromInstruction32(Insn, 21, 5);
+
+ if(Inst.getOpcode() == Mips::SC){
+ Inst.addOperand(MCOperand::CreateReg(CPURegsTable[Reg]));
+ }
+
+ Inst.addOperand(MCOperand::CreateReg(CPURegsTable[Reg]));
+ Inst.addOperand(MCOperand::CreateReg(CPURegsTable[Base]));
+ Inst.addOperand(MCOperand::CreateImm(Offset));
+
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeFMem(MCInst &Inst,
+ unsigned Insn,
+ uint64_t Address,
+ const void *Decoder) {
+ int Offset = SignExtend32<16>(Insn & 0xffff);
+ int Reg = (int)fieldFromInstruction32(Insn, 16, 5);
+ int Base = (int)fieldFromInstruction32(Insn, 21, 5);
+
+ Inst.addOperand(MCOperand::CreateReg(FGR64RegsTable[Reg]));
+ Inst.addOperand(MCOperand::CreateReg(CPURegsTable[Base]));
+ Inst.addOperand(MCOperand::CreateImm(Offset));
+
+ return MCDisassembler::Success;
+}
+
+
+static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
+ unsigned RegNo,
+ uint64_t Address,
+ const void *Decoder) {
+ // Currently only hardware register 29 is supported.
+ if (RegNo != 29)
+ return MCDisassembler::Fail;
+ Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeCondCode(MCInst &Inst,
+ unsigned Insn,
+ uint64_t Address,
+ const void *Decoder) {
+ int CondCode = Insn & 0xf;
+ Inst.addOperand(MCOperand::CreateImm(CondCode));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
+ unsigned RegNo,
+ uint64_t Address,
+ const void *Decoder) {
+ if (RegNo > 31)
+ return MCDisassembler::Fail;
+
+ Inst.addOperand(MCOperand::CreateReg(AFGR64RegsTable[RegNo]));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst,
+ unsigned RegNo,
+ uint64_t Address,
+ const void *Decoder) {
+ //Currently only hardware register 29 is supported
+ if (RegNo != 29)
+ return MCDisassembler::Fail;
+ Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeBranchTarget(MCInst &Inst,
+ unsigned Offset,
+ uint64_t Address,
+ const void *Decoder) {
+ unsigned BranchOffset = Offset & 0xffff;
+ BranchOffset = SignExtend32<18>(BranchOffset << 2) + 4;
+ Inst.addOperand(MCOperand::CreateImm(BranchOffset));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeBC1(MCInst &Inst,
+ unsigned Insn,
+ uint64_t Address,
+ const void *Decoder) {
+ unsigned BranchOffset = Insn & 0xffff;
+ BranchOffset = SignExtend32<18>(BranchOffset << 2) + 4;
+ Inst.addOperand(MCOperand::CreateImm(BranchOffset));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeJumpTarget(MCInst &Inst,
+ unsigned Insn,
+ uint64_t Address,
+ const void *Decoder) {
+
+ unsigned JumpOffset = fieldFromInstruction32(Insn, 0, 26) << 2;
+ Inst.addOperand(MCOperand::CreateImm(JumpOffset));
+ return MCDisassembler::Success;
+}
+
+
+static DecodeStatus DecodeSimm16(MCInst &Inst,
+ unsigned Insn,
+ uint64_t Address,
+ const void *Decoder) {
+ Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeInsSize(MCInst &Inst,
+ unsigned Insn,
+ uint64_t Address,
+ const void *Decoder) {
+ // First we need to grab the pos(lsb) from MCInst.
+ int Pos = Inst.getOperand(2).getImm();
+ int Size = (int) Insn - Pos + 1;
+ Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeExtSize(MCInst &Inst,
+ unsigned Insn,
+ uint64_t Address,
+ const void *Decoder) {
+ int Size = (int) Insn + 1;
+ Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
+ return MCDisassembler::Success;
+}
;===------------------------------------------------------------------------===;
[common]
-subdirectories = AsmParser InstPrinter MCTargetDesc TargetInfo
+subdirectories = AsmParser Disassembler InstPrinter MCTargetDesc TargetInfo
[component_0]
type = TargetGroup
parent = Target
has_asmparser = 1
has_asmprinter = 1
+has_disassembler = 1
has_jit = 1
[component_1]
using namespace llvm;
+static std::string ParseMipsTriple(StringRef TT, StringRef CPU) {
+ std::string MipsArchFeature;
+ size_t DashPosition = 0;
+ StringRef TheTriple;
+
+ // Let's see if there is a dash, like mips-unknown-linux.
+ DashPosition = TT.find('-');
+
+ if (DashPosition == StringRef::npos) {
+ // No dash, we check the string size.
+ TheTriple = TT.substr(0);
+ } else {
+ // We are only interested in substring before dash.
+ TheTriple = TT.substr(0,DashPosition);
+ }
+
+ if (TheTriple == "mips" || TheTriple == "mipsel") {
+ if (CPU.empty() || CPU == "mips32") {
+ MipsArchFeature = "+mips32";
+ } else if (CPU == "mips32r2") {
+ MipsArchFeature = "+mips32r2";
+ }
+ } else {
+ if (CPU.empty() || CPU == "mips64") {
+ MipsArchFeature = "+mips64";
+ } else if (CPU == "mips64r2") {
+ MipsArchFeature = "+mips64r2";
+ }
+ }
+ return MipsArchFeature;
+}
+
static MCInstrInfo *createMipsMCInstrInfo() {
MCInstrInfo *X = new MCInstrInfo();
InitMipsMCInstrInfo(X);
static MCSubtargetInfo *createMipsMCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS) {
+ std::string ArchFS = ParseMipsTriple(TT,CPU);
+ if (!FS.empty()) {
+ if (!ArchFS.empty())
+ ArchFS = ArchFS + "," + FS.str();
+ else
+ ArchFS = FS;
+ }
MCSubtargetInfo *X = new MCSubtargetInfo();
- InitMipsMCSubtargetInfo(X, TT, CPU, FS);
+ InitMipsMCSubtargetInfo(X, TT, CPU, ArchFS);
return X;
}
BUILT_SOURCES = MipsGenRegisterInfo.inc MipsGenInstrInfo.inc \
MipsGenAsmWriter.inc MipsGenCodeEmitter.inc \
MipsGenDAGISel.inc MipsGenCallingConv.inc \
- MipsGenSubtargetInfo.inc MipsGenMCCodeEmitter.inc
-
-DIRS = InstPrinter AsmParser TargetInfo MCTargetDesc
+ MipsGenSubtargetInfo.inc MipsGenMCCodeEmitter.inc \
+ MipsGenEDInfo.inc MipsGenDisassemblerTables.inc
+DIRS = InstPrinter Disassembler AsmParser TargetInfo MCTargetDesc
include $(LEVEL)/Makefile.common
//===----------------------------------------------------------------------===//
// Shifts
// 64-bit shift instructions.
+let DecoderNamespace = "Mips64" in {
class shift_rotate_imm64<bits<6> func, bits<5> isRotate, string instr_asm,
SDNode OpNode>:
shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt6, shamt,
multiclass Atomic2Ops64<PatFrag Op, string Opstr> {
def #NAME# : Atomic2Ops<Op, Opstr, CPU64Regs, CPURegs>, Requires<[NotN64]>;
- def _P8 : Atomic2Ops<Op, Opstr, CPU64Regs, CPU64Regs>, Requires<[IsN64]>;
+ def _P8 : Atomic2Ops<Op, Opstr, CPU64Regs, CPU64Regs>, Requires<[IsN64]> {
+ let isCodeGenOnly = 1;
+ }
}
multiclass AtomicCmpSwap64<PatFrag Op, string Width> {
def #NAME# : AtomicCmpSwap<Op, Width, CPU64Regs, CPURegs>, Requires<[NotN64]>;
def _P8 : AtomicCmpSwap<Op, Width, CPU64Regs, CPU64Regs>,
- Requires<[IsN64]>;
+ Requires<[IsN64]> {
+ let isCodeGenOnly = 1;
+ }
}
-
-let usesCustomInserter = 1, Predicates = [HasMips64] in {
+}
+let usesCustomInserter = 1, Predicates = [HasMips64],
+ DecoderNamespace = "Mips64" in {
defm ATOMIC_LOAD_ADD_I64 : Atomic2Ops64<atomic_load_add_64, "load_add_64">;
defm ATOMIC_LOAD_SUB_I64 : Atomic2Ops64<atomic_load_sub_64, "load_sub_64">;
defm ATOMIC_LOAD_AND_I64 : Atomic2Ops64<atomic_load_and_64, "load_and_64">;
//===----------------------------------------------------------------------===//
// Instruction definition
//===----------------------------------------------------------------------===//
-
+let DecoderNamespace = "Mips64" in {
/// Arithmetic Instructions (ALU Immediate)
def DADDiu : ArithLogicI<0x19, "daddiu", add, simm16_64, immSExt16,
CPU64Regs>;
def DSLL : shift_rotate_imm64<0x38, 0x00, "dsll", shl>;
def DSRL : shift_rotate_imm64<0x3a, 0x00, "dsrl", srl>;
def DSRA : shift_rotate_imm64<0x3b, 0x00, "dsra", sra>;
-def DSLLV : shift_rotate_reg<0x24, 0x00, "dsllv", shl, CPU64Regs>;
-def DSRLV : shift_rotate_reg<0x26, 0x00, "dsrlv", srl, CPU64Regs>;
-def DSRAV : shift_rotate_reg<0x27, 0x00, "dsrav", sra, CPU64Regs>;
-
+def DSLLV : shift_rotate_reg<0x14, 0x00, "dsllv", shl, CPU64Regs>;
+def DSRLV : shift_rotate_reg<0x16, 0x00, "dsrlv", srl, CPU64Regs>;
+def DSRAV : shift_rotate_reg<0x17, 0x00, "dsrav", sra, CPU64Regs>;
+}
// Rotate Instructions
-let Predicates = [HasMips64r2] in {
+let Predicates = [HasMips64r2], DecoderNamespace = "Mips64" in {
def DROTR : shift_rotate_imm64<0x3a, 0x01, "drotr", rotr>;
def DROTRV : shift_rotate_reg<0x16, 0x01, "drotrv", rotr, CPU64Regs>;
}
+let DecoderNamespace = "Mips64" in {
/// Load and Store Instructions
/// aligned
defm LB64 : LoadM64<0x20, "lb", sextloadi8>;
/// Load-linked, Store-conditional
def LLD : LLBase<0x34, "lld", CPU64Regs, mem>, Requires<[NotN64]>;
-def LLD_P8 : LLBase<0x34, "lld", CPU64Regs, mem64>, Requires<[IsN64]>;
+def LLD_P8 : LLBase<0x34, "lld", CPU64Regs, mem64>, Requires<[IsN64]> {
+ let isCodeGenOnly = 1;
+}
def SCD : SCBase<0x3c, "scd", CPU64Regs, mem>, Requires<[NotN64]>;
-def SCD_P8 : SCBase<0x3c, "scd", CPU64Regs, mem64>, Requires<[IsN64]>;
+def SCD_P8 : SCBase<0x3c, "scd", CPU64Regs, mem64>, Requires<[IsN64]> {
+ let isCodeGenOnly = 1;
+}
/// Jump and Branch Instructions
def JR64 : JumpFR<0x00, 0x08, "jr", CPU64Regs>;
def BNE64 : CBranch<0x05, "bne", setne, CPU64Regs>;
def BGEZ64 : CBranchZero<0x01, 1, "bgez", setge, CPU64Regs>;
def BGTZ64 : CBranchZero<0x07, 0, "bgtz", setgt, CPU64Regs>;
-def BLEZ64 : CBranchZero<0x07, 0, "blez", setle, CPU64Regs>;
+def BLEZ64 : CBranchZero<0x06, 0, "blez", setle, CPU64Regs>;
def BLTZ64 : CBranchZero<0x01, 0, "bltz", setlt, CPU64Regs>;
-
+}
+let DecoderNamespace = "Mips64" in
def JALR64 : JumpLinkReg<0x00, 0x09, "jalr", CPU64Regs>;
+let DecoderNamespace = "Mips64" in {
/// Multiply and Divide Instructions.
def DMULT : Mult64<0x1c, "dmult", IIImul>;
def DMULTu : Mult64<0x1d, "dmultu", IIImul>;
def DSHD : SubwordSwap<0x24, 0x5, "dshd", CPU64Regs>;
def LEA_ADDiu64 : EffectiveAddress<"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>;
-
-let Uses = [SP_64] in
+}
+let Uses = [SP_64], DecoderNamespace = "Mips64" in
def DynAlloc64 : EffectiveAddress<"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>,
- Requires<[IsN64]>;
-
+ Requires<[IsN64]> {
+ let isCodeGenOnly = 1;
+}
+let DecoderNamespace = "Mips64" in {
def RDHWR64 : ReadHardware<CPU64Regs, HWRegs64>;
def DEXT : ExtBase<3, "dext", CPU64Regs>;
def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
"sll\t$rd, $rt, 0", [], IIAlu>;
+let isCodeGenOnly = 1 in
def SLL64_64 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt),
"sll\t$rd, $rt, 0", [], IIAlu>;
-
+}
//===----------------------------------------------------------------------===//
// Arbitrary patterns that map to one or more instructions
//===----------------------------------------------------------------------===//
// Instantiation of instructions.
def MOVZ_I_I : CondMovIntInt<CPURegs, CPURegs, 0x0a, "movz">;
-let Predicates = [HasMips64] in {
+let Predicates = [HasMips64],DecoderNamespace = "Mips64" in {
def MOVZ_I_I64 : CondMovIntInt<CPURegs, CPU64Regs, 0x0a, "movz">;
- def MOVZ_I64_I : CondMovIntInt<CPU64Regs, CPURegs, 0x0a, "movz">;
- def MOVZ_I64_I64 : CondMovIntInt<CPU64Regs, CPU64Regs, 0x0a, "movz">;
+ def MOVZ_I64_I : CondMovIntInt<CPU64Regs, CPURegs, 0x0a, "movz"> {
+ let isCodeGenOnly = 1;
+ }
+ def MOVZ_I64_I64 : CondMovIntInt<CPU64Regs, CPU64Regs, 0x0a, "movz"> {
+ let isCodeGenOnly = 1;
+ }
}
def MOVN_I_I : CondMovIntInt<CPURegs, CPURegs, 0x0b, "movn">;
-let Predicates = [HasMips64] in {
+let Predicates = [HasMips64],DecoderNamespace = "Mips64" in {
def MOVN_I_I64 : CondMovIntInt<CPURegs, CPU64Regs, 0x0b, "movn">;
- def MOVN_I64_I : CondMovIntInt<CPU64Regs, CPURegs, 0x0b, "movn">;
- def MOVN_I64_I64 : CondMovIntInt<CPU64Regs, CPU64Regs, 0x0b, "movn">;
+ def MOVN_I64_I : CondMovIntInt<CPU64Regs, CPURegs, 0x0b, "movn"> {
+ let isCodeGenOnly = 1;
+ }
+ def MOVN_I64_I64 : CondMovIntInt<CPU64Regs, CPU64Regs, 0x0b, "movn"> {
+ let isCodeGenOnly = 1;
+ }
}
def MOVZ_I_S : CondMovIntFP<CPURegs, FGR32, 16, 18, "movz.s">;
def MOVZ_I64_S : CondMovIntFP<CPU64Regs, FGR32, 16, 18, "movz.s">,
- Requires<[HasMips64]>;
+ Requires<[HasMips64]> {
+ let DecoderNamespace = "Mips64";
+}
def MOVN_I_S : CondMovIntFP<CPURegs, FGR32, 16, 19, "movn.s">;
def MOVN_I64_S : CondMovIntFP<CPU64Regs, FGR32, 16, 19, "movn.s">,
- Requires<[HasMips64]>;
+ Requires<[HasMips64]> {
+ let DecoderNamespace = "Mips64";
+}
let Predicates = [NotFP64bit] in {
def MOVZ_I_D32 : CondMovIntFP<CPURegs, AFGR64, 17, 18, "movz.d">;
def MOVN_I_D32 : CondMovIntFP<CPURegs, AFGR64, 17, 19, "movn.d">;
}
-let Predicates = [IsFP64bit] in {
+let Predicates = [IsFP64bit],DecoderNamespace = "Mips64" in {
def MOVZ_I_D64 : CondMovIntFP<CPURegs, FGR64, 17, 18, "movz.d">;
- def MOVZ_I64_D64 : CondMovIntFP<CPU64Regs, FGR64, 17, 18, "movz.d">;
+ def MOVZ_I64_D64 : CondMovIntFP<CPU64Regs, FGR64, 17, 18, "movz.d"> {
+ let isCodeGenOnly = 1;
+ }
def MOVN_I_D64 : CondMovIntFP<CPURegs, FGR64, 17, 19, "movn.d">;
- def MOVN_I64_D64 : CondMovIntFP<CPU64Regs, FGR64, 17, 19, "movn.d">;
+ def MOVN_I64_D64 : CondMovIntFP<CPU64Regs, FGR64, 17, 19, "movn.d"> {
+ let isCodeGenOnly = 1;
+ }
}
def MOVT_I : CondMovFPInt<CPURegs, MipsCMovFP_T, 1, "movt">;
def MOVT_I64 : CondMovFPInt<CPU64Regs, MipsCMovFP_T, 1, "movt">,
- Requires<[HasMips64]>;
+ Requires<[HasMips64]> {
+ let DecoderNamespace = "Mips64";
+}
def MOVF_I : CondMovFPInt<CPURegs, MipsCMovFP_F, 0, "movf">;
def MOVF_I64 : CondMovFPInt<CPU64Regs, MipsCMovFP_F, 0, "movf">,
- Requires<[HasMips64]>;
+ Requires<[HasMips64]> {
+ let DecoderNamespace = "Mips64";
+}
def MOVT_S : CondMovFPFP<FGR32, MipsCMovFP_T, 16, 1, "movt.s">;
def MOVF_S : CondMovFPFP<FGR32, MipsCMovFP_F, 16, 0, "movf.s">;
def MOVT_D32 : CondMovFPFP<AFGR64, MipsCMovFP_T, 17, 1, "movt.d">;
def MOVF_D32 : CondMovFPFP<AFGR64, MipsCMovFP_F, 17, 0, "movf.d">;
}
-let Predicates = [IsFP64bit] in {
+let Predicates = [IsFP64bit], DecoderNamespace = "Mips64" in {
def MOVT_D64 : CondMovFPFP<FGR64, MipsCMovFP_T, 17, 1, "movt.d">;
def MOVF_D64 : CondMovFPFP<FGR64, MipsCMovFP_F, 17, 0, "movf.d">;
}
SDT_MipsExtractElementF64>;
// Operand for printing out a condition code.
-let PrintMethod = "printFCCOperand" in
+let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in
def condcode : Operand<i32>;
//===----------------------------------------------------------------------===//
// Feature predicates.
//===----------------------------------------------------------------------===//
-def IsFP64bit : Predicate<"Subtarget.isFP64bit()">;
-def NotFP64bit : Predicate<"!Subtarget.isFP64bit()">;
-def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">;
-def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">;
+def IsFP64bit : Predicate<"Subtarget.isFP64bit()">, AssemblerPredicate<"FeatureFP64Bit">;
+def NotFP64bit : Predicate<"!Subtarget.isFP64bit()">, AssemblerPredicate<"!FeatureFP64Bit">;
+def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">, AssemblerPredicate<"FeatureSingleFloat">;
+def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">, AssemblerPredicate<"!FeatureSingleFloat">;
// FP immediate patterns.
def fpimm0 : PatLeaf<(fpimm), [{
//===----------------------------------------------------------------------===//
// FP load.
+let DecoderMethod = "DecodeFMem" in {
class FPLoad<bits<6> op, string opstr, RegisterClass RC, Operand MemOpnd>:
FMem<op, (outs RC:$ft), (ins MemOpnd:$addr),
!strconcat(opstr, "\t$ft, $addr"), [(set RC:$ft, (load_a addr:$addr))],
FMem<op, (outs), (ins RC:$ft, MemOpnd:$addr),
!strconcat(opstr, "\t$ft, $addr"), [(store_a RC:$ft, addr:$addr)],
IIStore>;
-
+}
// FP indexed load.
class FPIdxLoad<bits<6> funct, string opstr, RegisterClass DRC,
RegisterClass PRC, PatFrag FOp>:
def _D32 : FFR1<funct, 17, opstr, "w.d", FGR32, AFGR64>,
Requires<[NotFP64bit]>;
def _D64 : FFR1<funct, 17, opstr, "w.d", FGR32, FGR64>,
- Requires<[IsFP64bit]>;
+ Requires<[IsFP64bit]> {
+ let DecoderNamespace = "Mips64";
+ }
}
// Instructions that convert an FP value to 64-bit fixed point.
-let Predicates = [IsFP64bit] in
+let Predicates = [IsFP64bit], DecoderNamespace = "Mips64" in
multiclass FFR1_L_M<bits<6> funct, string opstr> {
def _S : FFR1<funct, 16, opstr, "l.s", FGR64, FGR32>;
def _D64 : FFR1<funct, 17, opstr, "l.d", FGR64, FGR64>;
def _D32 : FFR1P<funct, 17, opstr, "d", AFGR64, AFGR64, OpNode>,
Requires<[NotFP64bit]>;
def _D64 : FFR1P<funct, 17, opstr, "d", FGR64, FGR64, OpNode>,
- Requires<[IsFP64bit]>;
+ Requires<[IsFP64bit]> {
+ let DecoderNamespace = "Mips64";
+ }
}
multiclass FFR2P_M<bits<6> funct, string opstr, SDNode OpNode, bit isComm = 0> {
def _D32 : FFR2P<funct, 17, opstr, "d", AFGR64, OpNode>,
Requires<[NotFP64bit]>;
def _D64 : FFR2P<funct, 17, opstr, "d", FGR64, OpNode>,
- Requires<[IsFP64bit]>;
+ Requires<[IsFP64bit]> {
+ let DecoderNamespace = "Mips64";
}
}
+}
// FP madd/msub/nmadd/nmsub instruction classes.
class FMADDSUB<bits<3> funct, bits<3> fmt, string opstr, string fmtstr,
defm FLOOR_W : FFR1_W_M<0xf, "floor">;
defm FLOOR_L : FFR1_L_M<0xb, "floor">;
defm CVT_W : FFR1_W_M<0x24, "cvt">;
-defm CVT_L : FFR1_L_M<0x25, "cvt">;
+//defm CVT_L : FFR1_L_M<0x25, "cvt">;
def CVT_S_W : FFR1<0x20, 20, "cvt", "s.w", FGR32, FGR32>;
+def CVT_L_S : FFR1<0x25, 16, "cvt", "l.s", FGR64, FGR32>;
+def CVT_L_D64: FFR1<0x25, 17, "cvt", "l.d", FGR64, FGR64>;
let Predicates = [NotFP64bit] in {
def CVT_S_D32 : FFR1<0x20, 17, "cvt", "s.d", FGR32, AFGR64>;
def CVT_D32_S : FFR1<0x21, 16, "cvt", "d.s", AFGR64, FGR32>;
}
-let Predicates = [IsFP64bit] in {
+let Predicates = [IsFP64bit], DecoderNamespace = "Mips64" in {
def CVT_S_D64 : FFR1<0x20, 17, "cvt", "s.d", FGR32, FGR64>;
def CVT_S_L : FFR1<0x20, 21, "cvt", "s.l", FGR32, FGR64>;
def CVT_D64_W : FFR1<0x21, 20, "cvt", "d.w", FGR64, FGR32>;
def FMOV_D32 : FFR1<0x6, 17, "mov", "d", AFGR64, AFGR64>,
Requires<[NotFP64bit]>;
def FMOV_D64 : FFR1<0x6, 17, "mov", "d", FGR64, FGR64>,
- Requires<[IsFP64bit]>;
+ Requires<[IsFP64bit]> {
+ let DecoderNamespace = "Mips64";
+}
/// Floating Point Memory Instructions
-let Predicates = [IsN64] in {
+let Predicates = [IsN64], DecoderNamespace = "Mips64" in {
def LWC1_P8 : FPLoad<0x31, "lwc1", FGR32, mem64>;
def SWC1_P8 : FPStore<0x39, "swc1", FGR32, mem64>;
- def LDC164_P8 : FPLoad<0x35, "ldc1", FGR64, mem64>;
- def SDC164_P8 : FPStore<0x3d, "sdc1", FGR64, mem64>;
+ def LDC164_P8 : FPLoad<0x35, "ldc1", FGR64, mem64> {
+ let isCodeGenOnly =1;
+ }
+ def SDC164_P8 : FPStore<0x3d, "sdc1", FGR64, mem64> {
+ let isCodeGenOnly =1;
+ }
}
let Predicates = [NotN64] in {
def SWC1 : FPStore<0x39, "swc1", FGR32, mem>;
}
-let Predicates = [NotN64, HasMips64] in {
+let Predicates = [NotN64, HasMips64], DecoderNamespace = "Mips64" in {
def LDC164 : FPLoad<0x35, "ldc1", FGR64, mem>;
def SDC164 : FPStore<0x3d, "sdc1", FGR64, mem>;
}
def SDXC1 : FPIdxStore<0x9, "sdxc1", AFGR64, CPURegs, store_a>;
}
-let Predicates = [HasMips64, NotN64] in {
+let Predicates = [HasMips64, NotN64], DecoderNamespace="Mips64" in {
def LDXC164 : FPIdxLoad<0x1, "ldxc1", FGR64, CPURegs, load_a>;
def SDXC164 : FPIdxStore<0x9, "sdxc1", FGR64, CPURegs, store_a>;
}
// n64
-let Predicates = [IsN64] in {
+let Predicates = [IsN64], isCodeGenOnly=1 in {
def LWXC1_P8 : FPIdxLoad<0x0, "lwxc1", FGR32, CPU64Regs, load_a>;
def LUXC1_P8 : FPIdxLoad<0x5, "luxc1", FGR32, CPU64Regs, load_u>;
def LDXC164_P8 : FPIdxLoad<0x1, "ldxc1", FGR64, CPU64Regs, load_a>;
def NMSUB_D32 : FNMADDSUB<0x7, 1, "nmsub", "d", fsub, AFGR64>;
}
-let Predicates = [HasMips32r2, IsFP64bit] in {
+let Predicates = [HasMips32r2, IsFP64bit], isCodeGenOnly=1 in {
def MADD_D64 : FMADDSUB<0x4, 1, "madd", "d", fadd, FGR64>;
def MSUB_D64 : FMADDSUB<0x5, 1, "msub", "d", fsub, FGR64>;
}
-let Predicates = [HasMips32r2, IsFP64bit, NoNaNsFPMath] in {
+let Predicates = [HasMips32r2, IsFP64bit, NoNaNsFPMath], isCodeGenOnly=1 in {
def NMADD_D64 : FNMADDSUB<0x6, 1, "nmadd", "d", fadd, FGR64>;
def NMSUB_D64 : FNMADDSUB<0x7, 1, "nmsub", "d", fsub, FGR64>;
}
let Inst{16} = tf;
}
+let DecoderMethod = "DecodeBC1" in {
def BC1F : FBRANCH<0, 0, MIPS_BRANCH_F, "bc1f">;
def BC1T : FBRANCH<0, 1, MIPS_BRANCH_T, "bc1t">;
-
+}
//===----------------------------------------------------------------------===//
// Floating Point Flag Conditions
//===----------------------------------------------------------------------===//
let Defs=[FCR31] in {
def FCMP_S32 : FCMP<0x10, FGR32, "s">;
def FCMP_D32 : FCMP<0x11, AFGR64, "d">, Requires<[NotFP64bit]>;
- def FCMP_D64 : FCMP<0x11, FGR64, "d">, Requires<[IsFP64bit]>;
+ def FCMP_D64 : FCMP<0x11, FGR64, "d">, Requires<[IsFP64bit]> {
+ let DecoderNamespace = "Mips64";
+ }
}
//===----------------------------------------------------------------------===//
// Patterns for unaligned floating point loads and stores.
let Predicates = [HasMips32r2Or64, NotN64] in {
- def : Pat<(f32 (load_u CPURegs:$addr)), (LUXC1 CPURegs:$addr, ZERO)>;
+ def : Pat<(f32 (load_u CPURegs:$addr)), (LUXC1 CPURegs:$addr, ZERO)>;
def : Pat<(store_u FGR32:$src, CPURegs:$addr),
(SUXC1 FGR32:$src, CPURegs:$addr, ZERO)>;
}
let Predicates = [IsN64] in {
- def : Pat<(f32 (load_u CPU64Regs:$addr)), (LUXC1_P8 CPU64Regs:$addr, ZERO_64)>;
+ def : Pat<(f32 (load_u CPU64Regs:$addr)), (LUXC1_P8 CPU64Regs:$addr, ZERO_64)>;
def : Pat<(store_u FGR32:$src, CPU64Regs:$addr),
(SUXC1_P8 FGR32:$src, CPU64Regs:$addr, ZERO_64)>;
}
let Namespace = "Mips";
+ let Size = 4;
+
bits<6> Opcode = 0;
// Top 6 bits are the 'opcode' field
// TSFlags layout should be kept in sync with MipsInstrInfo.h.
let TSFlags{3-0} = FormBits;
+
+ let DecoderNamespace = "Mips";
+
+ field bits<32> SoftFail = 0;
}
// Mips Pseudo Instructions Format
//===----------------------------------------------------------------------===//
// Mips Instruction Predicate Definitions.
//===----------------------------------------------------------------------===//
-def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">;
-def HasBitCount : Predicate<"Subtarget.hasBitCount()">;
-def HasSwap : Predicate<"Subtarget.hasSwap()">;
-def HasCondMov : Predicate<"Subtarget.hasCondMov()">;
-def HasMips32 : Predicate<"Subtarget.hasMips32()">;
-def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">;
-def HasMips64 : Predicate<"Subtarget.hasMips64()">;
-def HasMips32r2Or64 : Predicate<"Subtarget.hasMips32r2Or64()">;
-def NotMips64 : Predicate<"!Subtarget.hasMips64()">;
-def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">;
-def IsN64 : Predicate<"Subtarget.isABI_N64()">;
-def NotN64 : Predicate<"!Subtarget.isABI_N64()">;
-def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
-def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">;
-def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
+def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
+ AssemblerPredicate<"FeatureSEInReg">;
+def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
+ AssemblerPredicate<"FeatureBitCount">;
+def HasSwap : Predicate<"Subtarget.hasSwap()">,
+ AssemblerPredicate<"FeatureSwap">;
+def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
+ AssemblerPredicate<"FeatureCondMov">;
+def HasMips32 : Predicate<"Subtarget.hasMips32()">,
+ AssemblerPredicate<"FeatureMips32">;
+def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
+ AssemblerPredicate<"FeatureMips32r2">;
+def HasMips64 : Predicate<"Subtarget.hasMips64()">,
+ AssemblerPredicate<"FeatureMips64">;
+def HasMips32r2Or64 : Predicate<"Subtarget.hasMips32r2Or64()">,
+ AssemblerPredicate<"FeatureMips32r2,FeatureMips64">;
+def NotMips64 : Predicate<"!Subtarget.hasMips64()">,
+ AssemblerPredicate<"!FeatureMips64">;
+def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
+ AssemblerPredicate<"FeatureMips64r2">;
+def IsN64 : Predicate<"Subtarget.isABI_N64()">,
+ AssemblerPredicate<"FeatureN64">;
+def NotN64 : Predicate<"!Subtarget.isABI_N64()">,
+ AssemblerPredicate<"!FeatureN64">;
+def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
+ AssemblerPredicate<"FeatureMips32">;
+def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
+ AssemblerPredicate<"FeatureMips32">;
+def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
+ AssemblerPredicate<"FeatureMips32">;
//===----------------------------------------------------------------------===//
// Mips Operand, Complex Patterns and Transformations Definitions.
def brtarget : Operand<OtherVT> {
let EncoderMethod = "getBranchTargetOpValue";
let OperandType = "OPERAND_PCREL";
+ let DecoderMethod = "DecodeBranchTarget";
}
def calltarget : Operand<iPTR> {
let EncoderMethod = "getJumpTargetOpValue";
}
def calltarget64: Operand<i64>;
-def simm16 : Operand<i32>;
+def simm16 : Operand<i32> {
+ let DecoderMethod= "DecodeSimm16";
+}
def simm16_64 : Operand<i64>;
def shamt : Operand<i32>;
// size operand of ext instruction
def size_ext : Operand<i32> {
let EncoderMethod = "getSizeExtEncoding";
+ let DecoderMethod = "DecodeExtSize";
}
// size operand of ins instruction
def size_ins : Operand<i32> {
let EncoderMethod = "getSizeInsEncoding";
+ let DecoderMethod = "DecodeInsSize";
}
// Transformation Function - get the lower 16 bits.
FI<op, (outs RC:$rt), (ins Imm:$imm16),
!strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu> {
let rs = 0;
- let neverHasSideEffects = 1;
}
class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
bits<21> addr;
let Inst{25-21} = addr{20-16};
let Inst{15-0} = addr{15-0};
+ let DecoderMethod = "DecodeMem";
}
// Memory Load/Store
def #NAME# : LoadM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
Requires<[NotN64]>;
def _P8 : LoadM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
- Requires<[IsN64]>;
+ Requires<[IsN64]> {
+ let DecoderNamespace = "Mips64";
+ let isCodeGenOnly = 1;
+ }
}
// 64-bit load.
def #NAME# : LoadM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
Requires<[NotN64]>;
def _P8 : LoadM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
- Requires<[IsN64]>;
+ Requires<[IsN64]> {
+ let DecoderNamespace = "Mips64";
+ let isCodeGenOnly = 1;
+ }
}
// 32-bit load.
def #NAME# : LoadUnAlign<op, CPURegs, mem>,
Requires<[NotN64]>;
def _P8 : LoadUnAlign<op, CPURegs, mem64>,
- Requires<[IsN64]>;
+ Requires<[IsN64]> {
+ let DecoderNamespace = "Mips64";
+ let isCodeGenOnly = 1;
+ }
}
// 32-bit store.
multiclass StoreM32<bits<6> op, string instr_asm, PatFrag OpNode,
def #NAME# : StoreM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
Requires<[NotN64]>;
def _P8 : StoreM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
- Requires<[IsN64]>;
+ Requires<[IsN64]> {
+ let DecoderNamespace = "Mips64";
+ let isCodeGenOnly = 1;
+ }
}
// 64-bit store.
def #NAME# : StoreM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
Requires<[NotN64]>;
def _P8 : StoreM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
- Requires<[IsN64]>;
+ Requires<[IsN64]> {
+ let DecoderNamespace = "Mips64";
+ let isCodeGenOnly = 1;
+ }
}
// 32-bit store.
def #NAME# : StoreUnAlign<op, CPURegs, mem>,
Requires<[NotN64]>;
def _P8 : StoreUnAlign<op, CPURegs, mem64>,
- Requires<[IsN64]>;
+ Requires<[IsN64]> {
+ let DecoderNamespace = "Mips64";
+ let isCodeGenOnly = 1;
+ }
}
// Conditional Branch
let isBarrier=1;
let hasDelaySlot = 1;
let Predicates = [RelocStatic];
+ let DecoderMethod = "DecodeJumpTarget";
}
// Unconditional branch
class JumpLink<bits<6> op, string instr_asm>:
FJ<op, (outs), (ins calltarget:$target, variable_ops),
!strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)],
- IIBranch>;
+ IIBranch> {
+ let DecoderMethod = "DecodeJumpTarget";
+ }
class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm,
RegisterClass RC>:
let shamt = 0;
let isCommutable = 1;
let Defs = DefRegs;
- let neverHasSideEffects = 1;
}
class Mult32<bits<6> func, string instr_asm, InstrItinClass itin>:
let rt = 0;
let shamt = 0;
let Uses = UseRegs;
- let neverHasSideEffects = 1;
}
class MoveToLOHI<bits<6> func, string instr_asm, RegisterClass RC,
let rd = 0;
let shamt = 0;
let Defs = DefRegs;
- let neverHasSideEffects = 1;
}
class EffectiveAddress<string instr_asm, RegisterClass RC, Operand Mem> :
let rs = 0;
let shamt = sa;
let Predicates = [HasSwap];
- let neverHasSideEffects = 1;
}
// Read Hardware
multiclass Atomic2Ops32<PatFrag Op, string Opstr> {
def #NAME# : Atomic2Ops<Op, Opstr, CPURegs, CPURegs>, Requires<[NotN64]>;
- def _P8 : Atomic2Ops<Op, Opstr, CPURegs, CPU64Regs>, Requires<[IsN64]>;
+ def _P8 : Atomic2Ops<Op, Opstr, CPURegs, CPU64Regs>, Requires<[IsN64]> {
+ let DecoderNamespace = "Mips64";
+ }
}
// Atomic Compare & Swap.
multiclass AtomicCmpSwap32<PatFrag Op, string Width> {
def #NAME# : AtomicCmpSwap<Op, Width, CPURegs, CPURegs>, Requires<[NotN64]>;
- def _P8 : AtomicCmpSwap<Op, Width, CPURegs, CPU64Regs>, Requires<[IsN64]>;
+ def _P8 : AtomicCmpSwap<Op, Width, CPURegs, CPU64Regs>, Requires<[IsN64]> {
+ let DecoderNamespace = "Mips64";
+ }
}
class LLBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> :
[(callseq_end timm:$amt1, timm:$amt2)]>;
}
+// Some assembly macros need to avoid pseudoinstructions and assembler
+// automatic reodering, we should reorder ourselves.
+def MACRO : MipsPseudo<(outs), (ins), ".set\tmacro", []>;
+def REORDER : MipsPseudo<(outs), (ins), ".set\treorder", []>;
+def NOMACRO : MipsPseudo<(outs), (ins), ".set\tnomacro", []>;
+def NOREORDER : MipsPseudo<(outs), (ins), ".set\tnoreorder", []>;
+
+// These macros are inserted to prevent GAS from complaining
+// when using the AT register.
+def NOAT : MipsPseudo<(outs), (ins), ".set\tnoat", []>;
+def ATMACRO : MipsPseudo<(outs), (ins), ".set\tat", []>;
+
// When handling PIC code the assembler needs .cpload and .cprestore
// directives. If the real instructions corresponding these directives
// are used, we have the same behavior, but get also a bunch of warnings
// from the assembler.
-let neverHasSideEffects = 1 in
-def CPRESTORE : MipsPseudo<(outs), (ins i32imm:$loc, CPURegs:$gp),
- ".cprestore\t$loc", []>;
+def CPLOAD : MipsPseudo<(outs), (ins CPURegs:$picreg), ".cpload\t$picreg", []>;
+def CPRESTORE : MipsPseudo<(outs), (ins i32imm:$loc), ".cprestore\t$loc", []>;
// For O32 ABI & PIC & non-fixed global base register, the following instruction
// seqeunce is emitted to set the global base register:
// before or between instructions 0 and 1, which is a limitation imposed by
// GNU linker.
-let isTerminator = 1, isBarrier = 1 in
def SETGP01 : MipsPseudo<(outs CPURegs:$dst), (ins), "", []>;
-
-let neverHasSideEffects = 1 in
def SETGP2 : MipsPseudo<(outs CPURegs:$globalreg), (ins CPURegs:$picreg), "",
[]>;
/// Load-linked, Store-conditional
def LL : LLBase<0x30, "ll", CPURegs, mem>, Requires<[NotN64]>;
-def LL_P8 : LLBase<0x30, "ll", CPURegs, mem64>, Requires<[IsN64]>;
+def LL_P8 : LLBase<0x30, "ll", CPURegs, mem64>, Requires<[IsN64]> {
+ let DecoderNamespace = "Mips64";
+}
+
def SC : SCBase<0x38, "sc", CPURegs, mem>, Requires<[NotN64]>;
-def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>, Requires<[IsN64]>;
+def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>, Requires<[IsN64]> {
+ let DecoderNamespace = "Mips64";
+}
/// Jump and Branch Instructions
def J : JumpFJ<0x02, "j">;
def BGEZAL : BranchLink<"bgezal", 0x11, CPURegs>;
def BLTZAL : BranchLink<"bltzal", 0x10, CPURegs>;
-let isReturn=1, isTerminator=1, hasDelaySlot=1,
+let isReturn=1, isTerminator=1, hasDelaySlot=1, isCodeGenOnly=1,
isBarrier=1, hasCtrlDep=1, rd=0, rt=0, shamt=0 in
def RET : FR <0x00, 0x08, (outs), (ins CPURegs:$target),
"jr\t$target", [(MipsRet CPURegs:$target)], IIBranch>;
// instructions. The same not happens for stack address copies, so an
// add op with mem ComplexPattern is used and the stack address copy
// can be matched. It's similar to Sparc LEA_ADDRi
-def LEA_ADDiu : EffectiveAddress<"addiu\t$rt, $addr", CPURegs, mem_ea>;
+def LEA_ADDiu : EffectiveAddress<"addiu\t$rt, $addr", CPURegs, mem_ea> {
+ let isCodeGenOnly = 1;
+}
// DynAlloc node points to dynamically allocated stack space.
// $sp is added to the list of implicitly used registers to prevent dead code
// elimination from removing instructions that modify $sp.
let Uses = [SP] in
-def DynAlloc : EffectiveAddress<"addiu\t$rt, $addr", CPURegs, mem_ea>;
+def DynAlloc : EffectiveAddress<"addiu\t$rt, $addr", CPURegs, mem_ea> {
+ let isCodeGenOnly = 1;
+}
// MADD*/MSUB*
def MADD : MArithR<0, "madd", MipsMAdd, 1>;
--- /dev/null
+# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux
+
+# CHECK: abs.d $f12,$f14
+0x46 0x20 0x39 0x85
+
+# CHECK: abs.s $f6,$f7
+0x46 0x00 0x39 0x85
+
+# CHECK: add t1,a2,a3
+0x00 0xc7 0x48 0x20
+
+# CHECK: add.d $f18,$f12,$f14
+0x46 0x27 0x32 0x40
+
+# CHECK: add.s $f9,$f6,$f7
+0x46 0x07 0x32 0x40
+
+# CHECK: addi t1,a2,17767
+0x20 0xc9 0x45 0x67
+
+# CHECK: addiu t1,a2,-15001
+0x24 0xc9 0xc5 0x67
+
+# CHECK: addu t1,a2,a3
+0x00 0xc7 0x48 0x21
+
+# CHECK: and t1,a2,a3
+0x00 0xc7 0x48 0x24
+
+# CHECK: andi t1,a2,0x4567
+0x30 0xc9 0x45 0x67
+
+# CHECK: b 00000534
+0x10 0x00 0x01 0x4c
+
+# CHECK: bal 00000534
+0x04 0x11 0x01 0x4c
+
+# CHECK: bc1f 00000534
+0x45 0x00 0x01 0x4c
+
+# CHECK: bc1t 00000534
+0x45 0x01 0x01 0x4c
+
+# CHECK: beq t1,a2,00000534
+0x11 0x26 0x01 0x4c
+
+# CHECK: bgez a2,00000534
+0x04 0xc1 0x01 0x4c
+
+# CHECK: bgezal a2,00000534
+0x04 0xd1 0x01 0x4c
+
+# CHECK: bgtz a2,00000534
+0x1c 0xc0 0x01 0x4c
+
+# CHECK: blez a2,00000534
+0x18 0xc0 0x01 0x4c
+
+# CHECK: bne t1,a2,00000534
+0x15 0x26 0x01 0x4c
+
+# CHECK: c.eq.d $f12,$f14
+0x46 0x27 0x30 0x32
+
+# CHECK: c.eq.s $f6,$f7
+0x46 0x07 0x30 0x32
+
+# CHECK: c.f.d $f12,$f14
+0x46 0x27 0x30 0x30
+
+# CHECK: c.f.s $f6,$f7
+0x46 0x07 0x30 0x30
+
+# CHECK: c.le.d $f12,$f14
+0x46 0x27 0x30 0x3e
+
+# CHECK: c.le.s $f6,$f7
+0x46 0x07 0x30 0x3e
+
+# CHECK: c.lt.d $f12,$f14
+0x46 0x27 0x30 0x3c
+
+# CHECK: c.lt.s $f6,$f7
+0x46 0x07 0x30 0x3c
+
+# CHECK: c.nge.d $f12,$f14
+0x46 0x27 0x30 0x3d
+
+# CHECK: c.nge.s $f6,$f7
+0x46 0x07 0x30 0x3d
+
+# CHECK: c.ngl.d $f12,$f14
+0x46 0x27 0x30 0x3b
+
+# CHECK: c.ngl.s $f6,$f7
+0x46 0x07 0x30 0x3b
+
+# CHECK: c.ngle.d $f12,$f14
+0x46 0x27 0x30 0x39
+
+# CHECK: c.ngle.s $f6,$f7
+0x46 0x07 0x30 0x39
+
+# CHECK: c.ngt.d $f12,$f14
+0x46 0x27 0x30 0x3f
+
+# CHECK: c.ngt.s $f6,$f7
+0x46 0x07 0x30 0x3f
+
+# CHECK: c.ole.d $f12,$f14
+0x46 0x27 0x30 0x36
+
+# CHECK: c.ole.s $f6,$f7
+0x46 0x07 0x30 0x36
+
+# CHECK: c.olt.d $f12,$f14
+0x46 0x27 0x30 0x34
+
+# CHECK: c.olt.s $f6,$f7
+0x46 0x07 0x30 0x34
+
+# CHECK: c.seq.d $f12,$f14
+0x46 0x27 0x30 0x3a
+
+# CHECK: c.seq.s $f6,$f7
+0x46 0x07 0x30 0x3a
+
+# CHECK: c.sf.d $f12,$f14
+0x46 0x27 0x30 0x38
+
+# CHECK: c.sf.s $f6,$f7
+0x46 0x07 0x30 0x38
+
+# CHECK: c.ueq.d $f12,$f14
+0x46 0x27 0x30 0x33
+
+# CHECK: c.ueq.s $f28,$f18
+0x46 0x12 0xe0 0x33
+
+# CHECK: c.ule.d $f12,$f14
+0x46 0x27 0x30 0x37
+
+# CHECK: c.ule.s $f6,$f7
+0x46 0x07 0x30 0x37
+
+# CHECK: c.ult.d $f12,$f14
+0x46 0x27 0x30 0x35
+
+# CHECK: c.ult.s $f6,$f7
+0x46 0x07 0x30 0x35
+
+# CHECK: c.un.d $f12,$f14
+0x46 0x27 0x30 0x31
+
+# CHECK: c.un.s $f6,$f7
+0x46 0x07 0x30 0x31
+
+# CHECK: ceil.w.d $f12,$f14
+0x46 0x20 0x39 0x8e
+
+# CHECK: ceil.w.s $f6,$f7
+0x46 0x00 0x39 0x8e
+
+# CHECK: cfc1 a2,$7
+0x44 0x46 0x38 0x00
+
+# CHECK: clo a2,a3
+0x70 0xe6 0x30 0x21
+
+# CHECK: clz a2,a3
+0x70 0xe6 0x30 0x20
+
+# CHECK: ctc1 a2,$7
+0x44 0xc6 0x38 0x00
+
+# CHECK: cvt.d.s $f6,$f7
+0x46 0x00 0x38 0xa1
+
+# CHECK: cvt.d.w $f12,$f14
+0x46 0x80 0x38 0xa1
+
+# CHECK: cvt.l.d $f12,$f14
+0x46 0x20 0x39 0xa5
+
+# CHECK: cvt.l.s $f6,$f7
+0x46 0x00 0x39 0xa5
+
+# CHECK: cvt.s.d $f12,$f14
+0x46 0x20 0x39 0xa0
+
+# CHECK: cvt.s.w $f6,$f7
+0x46 0x80 0x39 0xa0
+
+# CHECK: cvt.w.d $f12,$f14
+0x46 0x20 0x39 0xa4
+
+# CHECK: cvt.w.s $f6,$f7
+0x46 0x00 0x39 0xa4
+
+# CHECK: floor.w.d $f12,$f14
+0x46 0x20 0x39 0x8f
+
+# CHECK: floor.w.s $f6,$f7
+0x46 0x00 0x39 0x8f
+
+# CHECK: j 00000530
+0x08 0x00 0x01 0x4c
+
+# CHECK: jal 00000530
+0x0c 0x00 0x01 0x4c
+
+# CHECK: jalr a2,a3
+0x00 0xe0 0xf8 0x09
+
+# CHECK: jr a3
+0x00 0xe0 0x00 0x08
+
+# CHECK: lb a0,9158(a1)
+0x80 0xa4 0x23 0xc6
+
+# CHECK: lbu a0,6(a1)
+0x90 0xa4 0x00 0x06
+
+# CHECK: ldc1 $f9,9158(a3)
+0xd4 0xe9 0x23 0xc6
+
+# CHECK: lh a0,12(a1)
+0x84 0xa4 0x00 0x0c
+
+# CHECK: lh a0,12(a1)
+0x84 0xa4 0x00 0x0c
+
+# CHECK: li v1,17767
+0x24 0x03 0x45 0x67
+
+# CHECK: ll t1,9158(a3)
+0xc0 0xe9 0x23 0xc6
+
+# CHECK: lui a2,0x4567
+0x3c 0x06 0x45 0x67
+
+# CHECK: lw a0,24(a1)
+0x8c 0xa4 0x00 0x18
+
+# CHECK: lwc1 $f9,9158(a3)
+0xc4 0xe9 0x23 0xc6
+
+# CHECK: madd a2,a3
+0x70 0xc7 0x00 0x00
+
+# CHECK: maddu a2,a3
+0x70 0xc7 0x00 0x01
+
+# CHECK: mfc1 a2,$f7
+0x44 0x06 0x38 0x00
+
+# CHECK: mfhi a1
+0x00 0x00 0x28 0x10
+
+# CHECK: mflo a1
+0x00 0x00 0x28 0x12
+
+# CHECK: mov.d $f6,$f7
+0x46 0x20 0x39 0x86
+
+# CHECK: mov.s $f6,$f7
+0x46 0x00 0x39 0x86
+
+# CHECK: move a2,a1
+0x00 0xa0 0x30 0x21
+
+# CHECK: msub a2,a3
+0x70 0xc7 0x00 0x04
+
+# CHECK: msubu a2,a3
+0x70 0xc7 0x00 0x05
+
+# CHECK: mtc1 a2,$f7
+0x44 0x86 0x38 0x00
+
+# CHECK: mthi a3
+0x00 0xe0 0x00 0x11
+
+# CHECK: mtlo a3
+0x00 0xe0 0x00 0x13
+
+# CHECK: mul.d $f9,$f12,$f14
+0x46 0x27 0x32 0x42
+
+# CHECK: mul.s $f9,$f6,$f7
+0x46 0x07 0x32 0x42
+
+# CHECK: mul t1,a2,a3
+0x70 0xc7 0x48 0x02
+
+# CHECK: mult v1,a1
+0x00 0x65 0x00 0x18
+
+# CHECK: multu v1,a1
+0x00 0x65 0x00 0x19
+
+# CHECK: neg.d $f12,$f14
+0x46 0x20 0x39 0x87
+
+# CHECK: neg.s $f6,$f7
+0x46 0x00 0x39 0x87
+
+# CHECK: neg v1,a1
+0x00 0x05 0x18 0x22
+
+# CHECK: nop
+0x00 0x00 0x00 0x00
+
+# CHECK: nor t1,a2,a3
+0x00 0xc7 0x48 0x27
+
+# CHECK: not v1,a1
+0x00 0xa0 0x18 0x27
+
+# CHECK: or v1,v1,a1
+0x00 0x65 0x18 0x25
+
+# CHECK: ori t1,a2,0x4567
+0x34 0xc9 0x45 0x67
+
+# CHECK: rdhwr a2,$29
+0x7c 0x06 0xe8 0x3b
+
+# CHECK: round.w.d $f12,$f14
+0x46 0x20 0x39 0x8c
+
+# CHECK: round.w.s $f6,$f7
+0x46 0x00 0x39 0x8c
+
+# CHECK: sb a0,9158(a1)
+0xa0 0xa4 0x23 0xc6
+
+# CHECK: sb a0,6(a1)
+0xa0 0xa4 0x00 0x06
+
+# CHECK: sc t1,9158(a3)
+0xe0 0xe9 0x23 0xc6
+
+# CHECK: sdc1 $f9,9158(a3)
+0xf4 0xe9 0x23 0xc6
+
+# CHECK: sh a0,9158(a1)
+0xa4 0xa4 0x23 0xc6
+
+# CHECK: sll a0,v1,0x7
+0x00 0x03 0x21 0xc0
+
+# CHECK: sllv v0,v1,a1
+0x00 0xa3 0x10 0x04
+
+# CHECK: slt v1,v1,a1
+0x00 0x65 0x18 0x2a
+
+# CHECK: slti v1,v1,103
+0x28 0x63 0x00 0x67
+
+# CHECK: sltiu v1,v1,103
+0x2c 0x63 0x00 0x67
+
+# CHECK: sltu v1,v1,a1
+0x00 0x65 0x18 0x2b
+
+# CHECK: sqrt.d $f12,$f14
+0x46 0x20 0x39 0x84
+
+# CHECK: sqrt.s $f6,$f7
+0x46 0x00 0x39 0x84
+
+# CHECK: sra a0,v1,0x7
+0x00 0x03 0x21 0xc3
+
+# CHECK: sra a0,v1,0x7
+0x00 0x03 0x21 0xc3
+
+# CHECK: srav v0,v1,a1
+0x00 0xa3 0x10 0x07
+
+# CHECK: srl a0,v1,0x7
+0x00 0x03 0x21 0xc2
+
+# CHECK: srlv v0,v1,a1
+0x00 0xa3 0x10 0x06
+
+# CHECK: sub.d $f9,$f12,$f14
+0x46 0x27 0x32 0x41
+
+# CHECK: sub.s $f9,$f6,$f7
+0x46 0x07 0x32 0x41
+
+# CHECK: sub t1,a2,a3
+0x00 0xc7 0x48 0x22
+
+# CHECK: subu a0,v1,a1
+0x00 0x65 0x20 0x23
+
+# CHECK: sw a0,24(a1)
+0xac 0xa4 0x00 0x18
+
+# CHECK: swc1 $f9,9158(a3)
+0xe4 0xe9 0x23 0xc6
+
+# CHECK: sync 0x7
+0x00 0x00 0x01 0xcf
+
+# CHECK: trunc.w.d $f12,$f14
+0x46 0x20 0x39 0x8d
+
+# CHECK: trunc.w.s $f6,$f7
+0x46 0x00 0x39 0x8d
+
+# CHECK: xor v1,v1,a1
+0x00 0x65 0x18 0x26
+
+# CHECK: xori t1,a2,0x4567
+0x38 0xc9 0x45 0x67
--- /dev/null
+# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux
+
+# CHECK: abs.d $f12,$f14
+0x85 0x39 0x20 0x46
+
+# CHECK: abs.s $f6,$f7
+0x85 0x39 0x00 0x46
+
+# CHECK: add t1,a2,a3
+0x20 0x48 0xc7 0x00
+
+# CHECK: add.d $f18,$f12,$f14
+0x40 0x32 0x27 0x46
+
+# CHECK: add.s $f9,$f6,$f7
+0x40 0x32 0x07 0x46
+
+# CHECK: addi t1,a2,17767
+0x67 0x45 0xc9 0x20
+
+# CHECK: addiu t1,a2,-15001
+0x67 0xc5 0xc9 0x24
+
+# CHECK: addu t1,a2,a3
+0x21 0x48 0xc7 0x00
+
+# CHECK: and t1,a2,a3
+0x24 0x48 0xc7 0x00
+
+# CHECK: andi t1,a2,0x4567
+0x67 0x45 0xc9 0x30
+
+# CHECK: b 00000534
+0x4c 0x01 0x00 0x10
+
+# CHECK: bal 00000534
+0x4c 0x01 0x11 0x04
+
+# CHECK: bc1f 00000534
+0x4c 0x01 0x00 0x45
+
+# CHECK: bc1t 00000534
+0x4c 0x01 0x01 0x45
+
+# CHECK: beq t1,a2,00000534
+0x4c 0x01 0x26 0x11
+
+# CHECK: bgez a2,00000534
+0x4c 0x01 0xc1 0x04
+
+# CHECK: bgezal a2,00000534
+0x4c 0x01 0xd1 0x04
+
+# CHECK: bgtz a2,00000534
+0x4c 0x01 0xc0 0x1c
+
+# CHECK: blez a2,00000534
+0x4c 0x01 0xc0 0x18
+
+# CHECK: bne t1,a2,00000534
+0x4c 0x01 0x26 0x15
+
+# CHECK: c.eq.d $f12,$f14
+0x32 0x30 0x27 0x46
+
+# CHECK: c.eq.s $f6,$f7
+0x32 0x30 0x07 0x46
+
+# CHECK: c.f.d $f12,$f14
+0x30 0x30 0x27 0x46
+
+# CHECK: c.f.s $f6,$f7
+0x30 0x30 0x07 0x46
+
+# CHECK: c.le.d $f12,$f14
+0x3e 0x30 0x27 0x46
+
+# CHECK: c.le.s $f6,$f7
+0x3e 0x30 0x07 0x46
+
+# CHECK: c.lt.d $f12,$f14
+0x3c 0x30 0x27 0x46
+
+# CHECK: c.lt.s $f6,$f7
+0x3c 0x30 0x07 0x46
+
+# CHECK: c.nge.d $f12,$f14
+0x3d 0x30 0x27 0x46
+
+# CHECK: c.nge.s $f6,$f7
+0x3d 0x30 0x07 0x46
+
+# CHECK: c.ngl.d $f12,$f14
+0x3b 0x30 0x27 0x46
+
+# CHECK: c.ngl.s $f6,$f7
+0x3b 0x30 0x07 0x46
+
+# CHECK: c.ngle.d $f12,$f14
+0x39 0x30 0x27 0x46
+
+# CHECK: c.ngle.s $f6,$f7
+0x39 0x30 0x07 0x46
+
+# CHECK: c.ngt.d $f12,$f14
+0x3f 0x30 0x27 0x46
+
+# CHECK: c.ngt.s $f6,$f7
+0x3f 0x30 0x07 0x46
+
+# CHECK: c.ole.d $f12,$f14
+0x36 0x30 0x27 0x46
+
+# CHECK: c.ole.s $f6,$f7
+0x36 0x30 0x07 0x46
+
+# CHECK: c.olt.d $f12,$f14
+0x34 0x30 0x27 0x46
+
+# CHECK: c.olt.s $f6,$f7
+0x34 0x30 0x07 0x46
+
+# CHECK: c.seq.d $f12,$f14
+0x3a 0x30 0x27 0x46
+
+# CHECK: c.seq.s $f6,$f7
+0x3a 0x30 0x07 0x46
+
+# CHECK: c.sf.d $f12,$f14
+0x38 0x30 0x27 0x46
+
+# CHECK: c.sf.s $f6,$f7
+0x38 0x30 0x07 0x46
+
+# CHECK: c.ueq.d $f12,$f14
+0x33 0x30 0x27 0x46
+
+# CHECK: c.ueq.s $f28,$f18
+0x33 0xe0 0x12 0x46
+
+# CHECK: c.ule.d $f12,$f14
+0x37 0x30 0x27 0x46
+
+# CHECK: c.ule.s $f6,$f7
+0x37 0x30 0x07 0x46
+
+# CHECK: c.ult.d $f12,$f14
+0x35 0x30 0x27 0x46
+
+# CHECK: c.ult.s $f6,$f7
+0x35 0x30 0x07 0x46
+
+# CHECK: c.un.d $f12,$f14
+0x31 0x30 0x27 0x46
+
+# CHECK: c.un.s $f6,$f7
+0x31 0x30 0x07 0x46
+
+# CHECK: ceil.w.d $f12,$f14
+0x8e 0x38 0x20 0x46
+
+# CHECK: ceil.w.s $f6,$f7
+0x8e 0x38 0x00 0x46
+
+# CHECK: cfc1 a2,$7
+0x00 0x38 0x46 0x44
+
+# CHECK: clo a2,a3
+0x21 0x30 0xe6 0x70
+
+# CHECK: clz a2,a3
+0x20 0x30 0xe6 0x70
+
+# CHECK: ctc1 a2,$7
+0x00 0x38 0xc6 0x44
+
+# CHECK: cvt.d.s $f6,$f7
+0xa1 0x39 0x00 0x46
+
+# CHECK: cvt.d.w $f12,$f14
+0xa1 0x39 0x80 0x46
+
+# CHECK: cvt.l.d $f12,$f14
+0xa5 0x39 0x20 0x46
+
+# CHECK: cvt.l.s $f6,$f7
+0xa5 0x39 0x00 0x46
+
+# CHECK: cvt.s.d $f12,$f14
+0xa0 0x39 0x20 0x46
+
+# CHECK: cvt.s.w $f6,$f7
+0xa0 0x39 0x80 0x46
+
+# CHECK: cvt.w.d $f12,$f14
+0xa4 0x39 0x20 0x46
+
+# CHECK: cvt.w.s $f6,$f7
+0xa4 0x39 0x00 0x46
+
+# CHECK: floor.w.d $f12,$f14
+0x8f 0x39 0x20 0x46
+
+# CHECK: floor.w.s $f6,$f7
+0x8f 0x39 0x00 0x46
+
+# CHECK: j 00000530
+0x4c 0x01 0x00 0x08
+
+# CHECK: jal 00000530
+0x4c 0x01 0x00 0x0c
+
+# CHECK: jalr a2,a3
+0x09 0xf8 0xe0 0x00
+
+# CHECK: jr a3
+0x08 0x00 0xe0 0x00
+
+# CHECK: lb a0,9158(a1)
+0xc6 0x23 0xa4 0x80
+
+# CHECK: lbu a0,6(a1)
+0x06 0x00 0xa4 0x90
+
+# CHECK: ldc1 $f9,9158(a3)
+0xc6 0x23 0xe9 0xd4
+
+# CHECK: lh a0,12(a1)
+0x0c 0x00 0xa4 0x84
+
+# CHECK: lh a0,12(a1)
+0x0c 0x00 0xa4 0x84
+
+# CHECK: li v1,17767
+0x67 0x45 0x03 0x24
+
+# CHECK: ll t1,9158(a3)
+0xc6 0x23 0xe9 0xc0
+
+# CHECK: lui a2,0x4567
+0x67 0x45 0x06 0x3c
+
+# CHECK: lw a0,24(a1)
+0x18 0x00 0xa4 0x8c
+
+# CHECK lw at,-18316(v0)
+0x74 0xb8 0x41 0x8c
+
+# CHECK: lwc1 $f9,9158(a3)
+0xc6 0x23 0xe9 0xc4
+
+# CHECK: madd a2,a3
+0x00 0x00 0xc7 0x70
+
+# CHECK: maddu a2,a3
+0x01 0x00 0xc7 0x70
+
+# CHECK: mfc1 a2,$f7
+0x00 0x38 0x06 0x44
+
+# CHECK: mfhi a1
+0x10 0x28 0x00 0x00
+
+# CHECK: mflo a1
+0x12 0x28 0x00 0x00
+
+# CHECK: mov.d $f12,$f14
+0x86 0x39 0x20 0x46
+
+# CHECK: mov.s $f6,$f7
+0x86 0x39 0x00 0x46
+
+# CHECK: move a2,a1
+0x21 0x30 0xa0 0x00
+
+# CHECK: msub a2,a3
+0x04 0x00 0xc7 0x70
+
+# CHECK: msubu a2,a3
+0x05 0x00 0xc7 0x70
+
+# CHECK: mtc1 a2,$f7
+0x00 0x38 0x86 0x44
+
+# CHECK: mthi a3
+0x11 0x00 0xe0 0x00
+
+# CHECK: mtlo a3
+0x13 0x00 0xe0 0x00
+
+# CHECK: mul.d $f9,$f12,$f14
+0x42 0x32 0x27 0x46
+
+# CHECK: mul.s $f9,$f6,$f7
+0x42 0x32 0x07 0x46
+
+# CHECK: mul t1,a2,a3
+0x02 0x48 0xc7 0x70
+
+# CHECK: mult v1,a1
+0x18 0x00 0x65 0x00
+
+# CHECK: multu v1,a1
+0x19 0x00 0x65 0x00
+
+# CHECK: neg.d $f12,$f14
+0x87 0x39 0x20 0x46
+
+# CHECK: neg.s $f6,$f7
+0x87 0x39 0x00 0x46
+
+# CHECK: neg v1,a1
+0x22 0x18 0x05 0x00
+
+# CHECK: nop
+0x00 0x00 0x00 0x00
+
+# CHECK: nor t1,a2,a3
+0x27 0x48 0xc7 0x00
+
+# CHECK: not v1,a1
+0x27 0x18 0xa0 0x00
+
+# CHECK: or v1,v1,a1
+0x25 0x18 0x65 0x00
+
+# CHECK: ori t1,a2,0x4567
+0x67 0x45 0xc9 0x34
+
+# CHECK: rdhwr a2,$29
+0x3b 0xe8 0x06 0x7c
+
+# CHECK: round.w.d $f12,$f14
+0x8c 0x39 0x20 0x46
+
+# CHECK: round.w.s $f6,$f7
+0x8c 0x39 0x00 0x46
+
+# CHECK: sb a0,9158(a1)
+0xc6 0x23 0xa4 0xa0
+
+# CHECK: sb a0,6(a1)
+0x06 0x00 0xa4 0xa0
+
+# CHECK: sc t1,9158(a3)
+0xc6 0x23 0xe9 0xe0
+
+# CHECK: sdc1 $f9,9158(a3)
+0xc6 0x23 0xe9 0xf4
+
+# CHECK: sh a0,9158(a1)
+0xc6 0x23 0xa4 0xa4
+
+# CHECK: sll a0,v1,0x7
+0xc0 0x21 0x03 0x00
+
+# CHECK: sllv v0,v1,a1
+0x04 0x10 0xa3 0x00
+
+# CHECK: slt v1,v1,a1
+0x2a 0x18 0x65 0x00
+
+# CHECK: slti v1,v1,103
+0x67 0x00 0x63 0x28
+
+# CHECK: sltiu v1,v1,103
+0x67 0x00 0x63 0x2c
+
+# CHECK: sltu v1,v1,a1
+0x2b 0x18 0x65 0x00
+
+# CHECK: sqrt.d $f12,$f14
+0x84 0x39 0x20 0x46
+
+# CHECK: sqrt.s $f6,$f7
+0x84 0x39 0x00 0x46
+
+# CHECK: sra a0,v1,0x7
+0xc3 0x21 0x03 0x00
+
+# CHECK: sra a0,v1,0x7
+0xc3 0x21 0x03 0x00
+
+# CHECK: srav v0,v1,a1
+0x07 0x10 0xa3 0x00
+
+# CHECK: srl a0,v1,0x7
+0xc2 0x21 0x03 0x00
+
+# CHECK: srlv v0,v1,a1
+0x06 0x10 0xa3 0x00
+
+# CHECK: sub.d $f9,$f12,$f14
+0x41 0x32 0x27 0x46
+
+# CHECK: sub.s $f9,$f6,$f7
+0x41 0x32 0x07 0x46
+
+# CHECK: sub t1,a2,a3
+0x22 0x48 0xc7 0x00
+
+# CHECK: subu a0,v1,a1
+0x23 0x20 0x65 0x00
+
+# CHECK: sw a0,24(a1)
+0x18 0x00 0xa4 0xac
+
+# CHECK: swc1 $f9,9158(a3)
+0xc6 0x23 0xe9 0xe4
+
+# CHECK: sync 0x7
+0xcf 0x01 0x00 0x00
+
+# CHECK: trunc.w.d $f12,$f14
+0x8d 0x39 0x20 0x46
+
+# CHECK: trunc.w.s $f6,$f7
+0x8d 0x39 0x00 0x46
+
+# CHECK: xor v1,v1,a1
+0x26 0x18 0x65 0x00
+
+# CHECK: xori t1,a2,0x4567
+0x67 0x45 0xc9 0x38
--- /dev/null
+# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2
+
+# CHECK: abs.d $f12,$f14
+0x46 0x20 0x39 0x85
+
+# CHECK: abs.s $f6,$f7
+0x46 0x00 0x39 0x85
+
+# CHECK: add t1,a2,a3
+0x00 0xc7 0x48 0x20
+
+# CHECK: add.d $f18,$f12,$f14
+0x46 0x27 0x32 0x40
+
+# CHECK: add.s $f9,$f6,$f7
+0x46 0x07 0x32 0x40
+
+# CHECK: addi t1,a2,17767
+0x20 0xc9 0x45 0x67
+
+# CHECK: addiu t1,a2,-15001
+0x24 0xc9 0xc5 0x67
+
+# CHECK: addu t1,a2,a3
+0x00 0xc7 0x48 0x21
+
+# CHECK: and t1,a2,a3
+0x00 0xc7 0x48 0x24
+
+# CHECK: andi t1,a2,0x4567
+0x30 0xc9 0x45 0x67
+
+# CHECK: b 00000534
+0x10 0x00 0x01 0x4c
+
+# CHECK: bal 00000534
+0x04 0x11 0x01 0x4c
+
+# CHECK: bc1f 00000534
+0x45 0x00 0x01 0x4c
+
+# CHECK: bc1t 00000534
+0x45 0x01 0x01 0x4c
+
+# CHECK: beq t1,a2,00000534
+0x11 0x26 0x01 0x4c
+
+# CHECK: bgez a2,00000534
+0x04 0xc1 0x01 0x4c
+
+# CHECK: bgezal a2,00000534
+0x04 0xd1 0x01 0x4c
+
+# CHECK: bgtz a2,00000534
+0x1c 0xc0 0x01 0x4c
+
+# CHECK: blez a2,00000534
+0x18 0xc0 0x01 0x4c
+
+# CHECK: bne t1,a2,00000534
+0x15 0x26 0x01 0x4c
+
+# CHECK: c.eq.d $f12,$f14
+0x46 0x27 0x30 0x32
+
+# CHECK: c.eq.s $f6,$f7
+0x46 0x07 0x30 0x32
+
+# CHECK: c.f.d $f12,$f14
+0x46 0x27 0x30 0x30
+
+# CHECK: c.f.s $f6,$f7
+0x46 0x07 0x30 0x30
+
+# CHECK: c.le.d $f12,$f14
+0x46 0x27 0x30 0x3e
+
+# CHECK: c.le.s $f6,$f7
+0x46 0x07 0x30 0x3e
+
+# CHECK: c.lt.d $f12,$f14
+0x46 0x27 0x30 0x3c
+
+# CHECK: c.lt.s $f6,$f7
+0x46 0x07 0x30 0x3c
+
+# CHECK: c.nge.d $f12,$f14
+0x46 0x27 0x30 0x3d
+
+# CHECK: c.nge.s $f6,$f7
+0x46 0x07 0x30 0x3d
+
+# CHECK: c.ngl.d $f12,$f14
+0x46 0x27 0x30 0x3b
+
+# CHECK: c.ngl.s $f6,$f7
+0x46 0x07 0x30 0x3b
+
+# CHECK: c.ngle.d $f12,$f14
+0x46 0x27 0x30 0x39
+
+# CHECK: c.ngle.s $f6,$f7
+0x46 0x07 0x30 0x39
+
+# CHECK: c.ngt.d $f12,$f14
+0x46 0x27 0x30 0x3f
+
+# CHECK: c.ngt.s $f6,$f7
+0x46 0x07 0x30 0x3f
+
+# CHECK: c.ole.d $f12,$f14
+0x46 0x27 0x30 0x36
+
+# CHECK: c.ole.s $f6,$f7
+0x46 0x07 0x30 0x36
+
+# CHECK: c.olt.d $f12,$f14
+0x46 0x27 0x30 0x34
+
+# CHECK: c.olt.s $f6,$f7
+0x46 0x07 0x30 0x34
+
+# CHECK: c.seq.d $f12,$f14
+0x46 0x27 0x30 0x3a
+
+# CHECK: c.seq.s $f6,$f7
+0x46 0x07 0x30 0x3a
+
+# CHECK: c.sf.d $f12,$f14
+0x46 0x27 0x30 0x38
+
+# CHECK: c.sf.s $f6,$f7
+0x46 0x07 0x30 0x38
+
+# CHECK: c.ueq.d $f12,$f14
+0x46 0x27 0x30 0x33
+
+# CHECK: c.ueq.s $f28,$f18
+0x46 0x12 0xe0 0x33
+
+# CHECK: c.ule.d $f12,$f14
+0x46 0x27 0x30 0x37
+
+# CHECK: c.ule.s $f6,$f7
+0x46 0x07 0x30 0x37
+
+# CHECK: c.ult.d $f12,$f14
+0x46 0x27 0x30 0x35
+
+# CHECK: c.ult.s $f6,$f7
+0x46 0x07 0x30 0x35
+
+# CHECK: c.un.d $f12,$f14
+0x46 0x27 0x30 0x31
+
+# CHECK: c.un.s $f6,$f7
+0x46 0x07 0x30 0x31
+
+# CHECK: ceil.w.d $f12,$f14
+0x46 0x20 0x39 0x8e
+
+# CHECK: ceil.w.s $f6,$f7
+0x46 0x00 0x39 0x8e
+
+# CHECK: cfc1 a2,$7
+0x44 0x46 0x38 0x00
+
+# CHECK: clo a2,a3
+0x70 0xe6 0x30 0x21
+
+# CHECK: clz a2,a3
+0x70 0xe6 0x30 0x20
+
+# CHECK: ctc1 a2,$7
+0x44 0xc6 0x38 0x00
+
+# CHECK: cvt.d.s $f6,$f7
+0x46 0x00 0x38 0xa1
+
+# CHECK: cvt.d.w $f12,$f14
+0x46 0x80 0x38 0xa1
+
+# CHECK: cvt.l.d $f12,$f14
+0x46 0x20 0x39 0xa5
+
+# CHECK: cvt.l.s $f6,$f7
+0x46 0x00 0x39 0xa5
+
+# CHECK: cvt.s.d $f12,$f14
+0x46 0x20 0x39 0xa0
+
+# CHECK: cvt.s.w $f6,$f7
+0x46 0x80 0x39 0xa0
+
+# CHECK: cvt.w.d $f12,$f14
+0x46 0x20 0x39 0xa4
+
+# CHECK: cvt.w.s $f6,$f7
+0x46 0x00 0x39 0xa4
+
+# CHECK: floor.w.d $f12,$f14
+0x46 0x20 0x39 0x8f
+
+# CHECK: floor.w.s $f6,$f7
+0x46 0x00 0x39 0x8f
+
+# CHECK: ins s3,t1,0x6,0x7
+0x7d 0x33 0x61 0x84
+
+# CHECK: j 00000530
+0x08 0x00 0x01 0x4c
+
+# CHECK: jal 00000530
+0x0c 0x00 0x01 0x4c
+
+# CHECK: jalr a2,a3
+0x00 0xe0 0xf8 0x09
+
+# CHECK: jr a3
+0x00 0xe0 0x00 0x08
+
+# CHECK: lb a0,9158(a1)
+0x80 0xa4 0x23 0xc6
+
+# CHECK: lbu a0,6(a1)
+0x90 0xa4 0x00 0x06
+
+# CHECK: ldc1 $f9,9158(a3)
+0xd4 0xe9 0x23 0xc6
+
+# CHECK: lh a0,12(a1)
+0x84 0xa4 0x00 0x0c
+
+# CHECK: lh a0,12(a1)
+0x84 0xa4 0x00 0x0c
+
+# CHECK: li v1,17767
+0x24 0x03 0x45 0x67
+
+# CHECK: ll t1,9158(a3)
+0xc0 0xe9 0x23 0xc6
+
+# CHECK: lui a2,0x4567
+0x3c 0x06 0x45 0x67
+
+# CHECK: lw a0,24(a1)
+0x8c 0xa4 0x00 0x18
+
+# CHECK: lwc1 $f9,9158(a3)
+0xc4 0xe9 0x23 0xc6
+
+# CHECK: madd a2,a3
+0x70 0xc7 0x00 0x00
+
+# CHECK: maddu a2,a3
+0x70 0xc7 0x00 0x01
+
+# CHECK: mfc1 a2,$f7
+0x44 0x06 0x38 0x00
+
+# CHECK: mfhi a1
+0x00 0x00 0x28 0x10
+
+# CHECK: mflo a1
+0x00 0x00 0x28 0x12
+
+# CHECK: mov.d $f6,$f7
+0x46 0x20 0x39 0x86
+
+# CHECK: mov.s $f6,$f7
+0x46 0x00 0x39 0x86
+
+# CHECK: move a2,a1
+0x00 0xa0 0x30 0x21
+
+# CHECK: msub a2,a3
+0x70 0xc7 0x00 0x04
+
+# CHECK: msubu a2,a3
+0x70 0xc7 0x00 0x05
+
+# CHECK: mtc1 a2,$f7
+0x44 0x86 0x38 0x00
+
+# CHECK: mthi a3
+0x00 0xe0 0x00 0x11
+
+# CHECK: mtlo a3
+0x00 0xe0 0x00 0x13
+
+# CHECK: mul.d $f9,$f12,$f14
+0x46 0x27 0x32 0x42
+
+# CHECK: mul.s $f9,$f6,$f7
+0x46 0x07 0x32 0x42
+
+# CHECK: mul t1,a2,a3
+0x70 0xc7 0x48 0x02
+
+# CHECK: mult v1,a1
+0x00 0x65 0x00 0x18
+
+# CHECK: multu v1,a1
+0x00 0x65 0x00 0x19
+
+# CHECK: neg.d $f12,$f14
+0x46 0x20 0x39 0x87
+
+# CHECK: neg.s $f6,$f7
+0x46 0x00 0x39 0x87
+
+# CHECK: neg v1,a1
+0x00 0x05 0x18 0x22
+
+# CHECK: nop
+0x00 0x00 0x00 0x00
+
+# CHECK: nor t1,a2,a3
+0x00 0xc7 0x48 0x27
+
+# CHECK: not v1,a1
+0x00 0xa0 0x18 0x27
+
+# CHECK: or v1,v1,a1
+0x00 0x65 0x18 0x25
+
+# CHECK: ori t1,a2,0x4567
+0x34 0xc9 0x45 0x67
+
+# CHECK: rdhwr a2,$29
+0x7c 0x06 0xe8 0x3b
+
+# CHECK: ror t1,a2,0x7
+0x00 0x26 0x49 0xc2
+
+# CHECK: rorv t1,a2,a3
+0x00 0xe6 0x48 0x46
+
+# CHECK: round.w.d $f12,$f14
+0x46 0x20 0x39 0x8c
+
+# CHECK: round.w.s $f6,$f7
+0x46 0x00 0x39 0x8c
+
+# CHECK: sb a0,9158(a1)
+0xa0 0xa4 0x23 0xc6
+
+# CHECK: sb a0,6(a1)
+0xa0 0xa4 0x00 0x06
+
+# CHECK: sc t1,9158(a3)
+0xe0 0xe9 0x23 0xc6
+
+# CHECK: sdc1 $f9,9158(a3)
+0xf4 0xe9 0x23 0xc6
+
+# CHECK: seb a2,a3
+0x7c 0x07 0x34 0x20
+
+# CHECK: seh a2,a3
+0x7c 0x07 0x36 0x20
+
+# CHECK: sh a0,9158(a1)
+0xa4 0xa4 0x23 0xc6
+
+# CHECK: sll a0,v1,0x7
+0x00 0x03 0x21 0xc0
+
+# CHECK: sllv v0,v1,a1
+0x00 0xa3 0x10 0x04
+
+# CHECK: slt v1,v1,a1
+0x00 0x65 0x18 0x2a
+
+# CHECK: slti v1,v1,103
+0x28 0x63 0x00 0x67
+
+# CHECK: sltiu v1,v1,103
+0x2c 0x63 0x00 0x67
+
+# CHECK: sltu v1,v1,a1
+0x00 0x65 0x18 0x2b
+
+# CHECK: sqrt.d $f12,$f14
+0x46 0x20 0x39 0x84
+
+# CHECK: sqrt.s $f6,$f7
+0x46 0x00 0x39 0x84
+
+# CHECK: sra a0,v1,0x7
+0x00 0x03 0x21 0xc3
+
+# CHECK: sra a0,v1,0x7
+0x00 0x03 0x21 0xc3
+
+# CHECK: srav v0,v1,a1
+0x00 0xa3 0x10 0x07
+
+# CHECK: srl a0,v1,0x7
+0x00 0x03 0x21 0xc2
+
+# CHECK: srlv v0,v1,a1
+0x00 0xa3 0x10 0x06
+
+# CHECK: sub.d $f9,$f12,$f14
+0x46 0x27 0x32 0x41
+
+# CHECK: sub.s $f9,$f6,$f7
+0x46 0x07 0x32 0x41
+
+# CHECK: sub t1,a2,a3
+0x00 0xc7 0x48 0x22
+
+# CHECK: subu a0,v1,a1
+0x00 0x65 0x20 0x23
+
+# CHECK: sw a0,24(a1)
+0xac 0xa4 0x00 0x18
+
+# CHECK: swc1 $f9,9158(a3)
+0xe4 0xe9 0x23 0xc6
+
+# CHECK: sync 0x7
+0x00 0x00 0x01 0xcf
+
+# CHECK: trunc.w.d $f12,$f14
+0x46 0x20 0x39 0x8d
+
+# CHECK: trunc.w.s $f6,$f7
+0x46 0x00 0x39 0x8d
+
+# CHECK: wsbh a2,a3
+0x7c 0x07 0x30 0xa0
+
+# CHECK: xor v1,v1,a1
+0x00 0x65 0x18 0x26
+
+# CHECK: xori t1,a2,0x4567
+0x38 0xc9 0x45 0x67
--- /dev/null
+# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r2
+
+# CHECK: abs.d $f12,$f14
+0x85 0x39 0x20 0x46
+
+# CHECK: abs.s $f6,$f7
+0x85 0x39 0x00 0x46
+
+# CHECK: add t1,a2,a3
+0x20 0x48 0xc7 0x00
+
+# CHECK: add.d $f18,$f12,$f14
+0x40 0x32 0x27 0x46
+
+# CHECK: add.s $f9,$f6,$f7
+0x40 0x32 0x07 0x46
+
+# CHECK: addi t1,a2,17767
+0x67 0x45 0xc9 0x20
+
+# CHECK: addiu t1,a2,-15001
+0x67 0xc5 0xc9 0x24
+
+# CHECK: addu t1,a2,a3
+0x21 0x48 0xc7 0x00
+
+# CHECK: and t1,a2,a3
+0x24 0x48 0xc7 0x00
+
+# CHECK: andi t1,a2,0x4567
+0x67 0x45 0xc9 0x30
+
+# CHECK: b 00000534
+0x4c 0x01 0x00 0x10
+
+# CHECK: bal 00000534
+0x4c 0x01 0x11 0x04
+
+# CHECK: bc1f 00000534
+0x4c 0x01 0x00 0x45
+
+# CHECK: bc1t 00000534
+0x4c 0x01 0x01 0x45
+
+# CHECK: beq t1,a2,00000534
+0x4c 0x01 0x26 0x11
+
+# CHECK: bgez a2,00000534
+0x4c 0x01 0xc1 0x04
+
+# CHECK: bgezal a2,00000534
+0x4c 0x01 0xd1 0x04
+
+# CHECK: bgtz a2,00000534
+0x4c 0x01 0xc0 0x1c
+
+# CHECK: blez a2,00000534
+0x4c 0x01 0xc0 0x18
+
+# CHECK: bne t1,a2,00000534
+0x4c 0x01 0x26 0x15
+
+# CHECK: c.eq.d $f12,$f14
+0x32 0x30 0x27 0x46
+
+# CHECK: c.eq.s $f6,$f7
+0x32 0x30 0x07 0x46
+
+# CHECK: c.f.d $f12,$f14
+0x30 0x30 0x27 0x46
+
+# CHECK: c.f.s $f6,$f7
+0x30 0x30 0x07 0x46
+
+# CHECK: c.le.d $f12,$f14
+0x3e 0x30 0x27 0x46
+
+# CHECK: c.le.s $f6,$f7
+0x3e 0x30 0x07 0x46
+
+# CHECK: c.lt.d $f12,$f14
+0x3c 0x30 0x27 0x46
+
+# CHECK: c.lt.s $f6,$f7
+0x3c 0x30 0x07 0x46
+
+# CHECK: c.nge.d $f12,$f14
+0x3d 0x30 0x27 0x46
+
+# CHECK: c.nge.s $f6,$f7
+0x3d 0x30 0x07 0x46
+
+# CHECK: c.ngl.d $f12,$f14
+0x3b 0x30 0x27 0x46
+
+# CHECK: c.ngl.s $f6,$f7
+0x3b 0x30 0x07 0x46
+
+# CHECK: c.ngle.d $f12,$f14
+0x39 0x30 0x27 0x46
+
+# CHECK: c.ngle.s $f6,$f7
+0x39 0x30 0x07 0x46
+
+# CHECK: c.ngt.d $f12,$f14
+0x3f 0x30 0x27 0x46
+
+# CHECK: c.ngt.s $f6,$f7
+0x3f 0x30 0x07 0x46
+
+# CHECK: c.ole.d $f12,$f14
+0x36 0x30 0x27 0x46
+
+# CHECK: c.ole.s $f6,$f7
+0x36 0x30 0x07 0x46
+
+# CHECK: c.olt.d $f12,$f14
+0x34 0x30 0x27 0x46
+
+# CHECK: c.olt.s $f6,$f7
+0x34 0x30 0x07 0x46
+
+# CHECK: c.seq.d $f12,$f14
+0x3a 0x30 0x27 0x46
+
+# CHECK: c.seq.s $f6,$f7
+0x3a 0x30 0x07 0x46
+
+# CHECK: c.sf.d $f12,$f14
+0x38 0x30 0x27 0x46
+
+# CHECK: c.sf.s $f6,$f7
+0x38 0x30 0x07 0x46
+
+# CHECK: c.ueq.d $f12,$f14
+0x33 0x30 0x27 0x46
+
+# CHECK: c.ueq.s $f28,$f18
+0x33 0xe0 0x12 0x46
+
+# CHECK: c.ule.d $f12,$f14
+0x37 0x30 0x27 0x46
+
+# CHECK: c.ule.s $f6,$f7
+0x37 0x30 0x07 0x46
+
+# CHECK: c.ult.d $f12,$f14
+0x35 0x30 0x27 0x46
+
+# CHECK: c.ult.s $f6,$f7
+0x35 0x30 0x07 0x46
+
+# CHECK: c.un.d $f12,$f14
+0x31 0x30 0x27 0x46
+
+# CHECK: c.un.s $f6,$f7
+0x31 0x30 0x07 0x46
+
+# CHECK: ceil.w.d $f12,$f14
+0x8e 0x38 0x20 0x46
+
+# CHECK: ceil.w.s $f6,$f7
+0x8e 0x38 0x00 0x46
+
+# CHECK: cfc1 a2,$7
+0x00 0x38 0x46 0x44
+
+# CHECK: clo a2,a3
+0x21 0x30 0xe6 0x70
+
+# CHECK: clz a2,a3
+0x20 0x30 0xe6 0x70
+
+# CHECK: ctc1 a2,$7
+0x00 0x38 0xc6 0x44
+
+# CHECK: cvt.d.s $f6,$f7
+0xa1 0x39 0x00 0x46
+
+# CHECK: cvt.d.w $f12,$f14
+0xa1 0x39 0x80 0x46
+
+# CHECK: cvt.l.d $f12,$f14
+0xa5 0x39 0x20 0x46
+
+# CHECK: cvt.l.s $f6,$f7
+0xa5 0x39 0x00 0x46
+
+# CHECK: cvt.s.d $f12,$f14
+0xa0 0x39 0x20 0x46
+
+# CHECK: cvt.s.w $f6,$f7
+0xa0 0x39 0x80 0x46
+
+# CHECK: cvt.w.d $f12,$f14
+0xa4 0x39 0x20 0x46
+
+# CHECK: cvt.w.s $f6,$f7
+0xa4 0x39 0x00 0x46
+
+# CHECK: floor.w.d $f12,$f14
+0x8f 0x39 0x20 0x46
+
+# CHECK: floor.w.s $f6,$f7
+0x8f 0x39 0x00 0x46
+
+# CHECK: ins s3,t1,0x6,0x7
+0x84 0x61 0x33 0x7d
+
+# CHECK: j 00000530
+0x4c 0x01 0x00 0x08
+
+# CHECK: jal 00000530
+0x4c 0x01 0x00 0x0c
+
+# CHECK: jalr a2,a3
+0x09 0xf8 0xe0 0x00
+
+# CHECK: jr a3
+0x08 0x00 0xe0 0x00
+
+# CHECK: lb a0,9158(a1)
+0xc6 0x23 0xa4 0x80
+
+# CHECK: lbu a0,6(a1)
+0x06 0x00 0xa4 0x90
+
+# CHECK: ldc1 $f9,9158(a3)
+0xc6 0x23 0xe9 0xd4
+
+# CHECK: lh a0,12(a1)
+0x0c 0x00 0xa4 0x84
+
+# CHECK: lh a0,12(a1)
+0x0c 0x00 0xa4 0x84
+
+# CHECK: li v1,17767
+0x67 0x45 0x03 0x24
+
+# CHECK: ll t1,9158(a3)
+0xc6 0x23 0xe9 0xc0
+
+# CHECK: lui a2,0x4567
+0x67 0x45 0x06 0x3c
+
+# CHECK: lw a0,24(a1)
+0x18 0x00 0xa4 0x8c
+
+# CHECK lw at,-18316(v0)
+0x74 0xb8 0x41 0x8c
+
+# CHECK: lwc1 $f9,9158(a3)
+0xc6 0x23 0xe9 0xc4
+
+# CHECK: madd a2,a3
+0x00 0x00 0xc7 0x70
+
+# CHECK: maddu a2,a3
+0x01 0x00 0xc7 0x70
+
+# CHECK: mfc1 a2,$f7
+0x00 0x38 0x06 0x44
+
+# CHECK: mfhi a1
+0x10 0x28 0x00 0x00
+
+# CHECK: mflo a1
+0x12 0x28 0x00 0x00
+
+# CHECK: mov.d $f12,$f14
+0x86 0x39 0x20 0x46
+
+# CHECK: mov.s $f6,$f7
+0x86 0x39 0x00 0x46
+
+# CHECK: move a2,a1
+0x21 0x30 0xa0 0x00
+
+# CHECK: msub a2,a3
+0x04 0x00 0xc7 0x70
+
+# CHECK: msubu a2,a3
+0x05 0x00 0xc7 0x70
+
+# CHECK: mtc1 a2,$f7
+0x00 0x38 0x86 0x44
+
+# CHECK: mthi a3
+0x11 0x00 0xe0 0x00
+
+# CHECK: mtlo a3
+0x13 0x00 0xe0 0x00
+
+# CHECK: mul.d $f9,$f12,$f14
+0x42 0x32 0x27 0x46
+
+# CHECK: mul.s $f9,$f6,$f7
+0x42 0x32 0x07 0x46
+
+# CHECK: mul t1,a2,a3
+0x02 0x48 0xc7 0x70
+
+# CHECK: mult v1,a1
+0x18 0x00 0x65 0x00
+
+# CHECK: multu v1,a1
+0x19 0x00 0x65 0x00
+
+# CHECK: neg.d $f12,$f14
+0x87 0x39 0x20 0x46
+
+# CHECK: neg.s $f6,$f7
+0x87 0x39 0x00 0x46
+
+# CHECK: neg v1,a1
+0x22 0x18 0x05 0x00
+
+# CHECK: nop
+0x00 0x00 0x00 0x00
+
+# CHECK: nor t1,a2,a3
+0x27 0x48 0xc7 0x00
+
+# CHECK: not v1,a1
+0x27 0x18 0xa0 0x00
+
+# CHECK: or v1,v1,a1
+0x25 0x18 0x65 0x00
+
+# CHECK: ori t1,a2,0x4567
+0x67 0x45 0xc9 0x34
+
+# CHECK: rdhwr a2,$29
+0x3b 0xe8 0x06 0x7c
+
+# CHECK: ror t1,a2,0x7
+0xc2 0x49 0x26 0x00
+
+# CHECK: rorv t1,a2,a3
+0x46 0x48 0xe6 0x00
+
+# CHECK: round.w.d $f12,$f14
+0x8c 0x39 0x20 0x46
+
+# CHECK: round.w.s $f6,$f7
+0x8c 0x39 0x00 0x46
+
+# CHECK: sb a0,9158(a1)
+0xc6 0x23 0xa4 0xa0
+
+# CHECK: sb a0,6(a1)
+0x06 0x00 0xa4 0xa0
+
+# CHECK: sc t1,9158(a3)
+0xc6 0x23 0xe9 0xe0
+
+# CHECK: sdc1 $f9,9158(a3)
+0xc6 0x23 0xe9 0xf4
+
+# CHECK: seb a2,a3
+0x20 0x34 0x07 0x7c
+
+# CHECK: seh a2,a3
+0x20 0x36 0x07 0x7c
+
+# CHECK: sh a0,9158(a1)
+0xc6 0x23 0xa4 0xa4
+
+# CHECK: sll a0,v1,0x7
+0xc0 0x21 0x03 0x00
+
+# CHECK: sllv v0,v1,a1
+0x04 0x10 0xa3 0x00
+
+# CHECK: slt v1,v1,a1
+0x2a 0x18 0x65 0x00
+
+# CHECK: slti v1,v1,103
+0x67 0x00 0x63 0x28
+
+# CHECK: sltiu v1,v1,103
+0x67 0x00 0x63 0x2c
+
+# CHECK: sltu v1,v1,a1
+0x2b 0x18 0x65 0x00
+
+# CHECK: sqrt.d $f12,$f14
+0x84 0x39 0x20 0x46
+
+# CHECK: sqrt.s $f6,$f7
+0x84 0x39 0x00 0x46
+
+# CHECK: sra a0,v1,0x7
+0xc3 0x21 0x03 0x00
+
+# CHECK: sra a0,v1,0x7
+0xc3 0x21 0x03 0x00
+
+# CHECK: srav v0,v1,a1
+0x07 0x10 0xa3 0x00
+
+# CHECK: srl a0,v1,0x7
+0xc2 0x21 0x03 0x00
+
+# CHECK: srlv v0,v1,a1
+0x06 0x10 0xa3 0x00
+
+# CHECK: sub.d $f9,$f12,$f14
+0x41 0x32 0x27 0x46
+
+# CHECK: sub.s $f9,$f6,$f7
+0x41 0x32 0x07 0x46
+
+# CHECK: sub t1,a2,a3
+0x22 0x48 0xc7 0x00
+
+# CHECK: subu a0,v1,a1
+0x23 0x20 0x65 0x00
+
+# CHECK: sw a0,24(a1)
+0x18 0x00 0xa4 0xac
+
+# CHECK: swc1 $f9,9158(a3)
+0xc6 0x23 0xe9 0xe4
+
+# CHECK: sync 0x7
+0xcf 0x01 0x00 0x00
+
+# CHECK: trunc.w.d $f12,$f14
+0x8d 0x39 0x20 0x46
+
+# CHECK: trunc.w.s $f6,$f7
+0x8d 0x39 0x00 0x46
+
+# CHECK: wsbh a2,a3
+0xa0 0x30 0x07 0x7c
+
+# CHECK: xor v1,v1,a1
+0x26 0x18 0x65 0x00
+
+# CHECK: xori t1,a2,0x4567
+0x67 0x45 0xc9 0x38
--- /dev/null
+# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux\r
+\r
+# CHECK: daddiu t3,k0,31949\r
+0x67 0x4b 0x7c 0xcd\r
+\r
+# CHECK: daddu k0,at,t3\r
+0x00 0x2b 0xd0 0x2d\r
+\r
+# CHECK: ddiv zero,k0,s6\r
+0x03 0x56 0x00 0x1e\r
+\r
+# CHECK: ddivu zero,t1,t8\r
+0x01 0x38 0x00 0x1f\r
+\r
+# CHECK: dmfc1 v0,$f14\r
+0x44 0x22 0x70 0x00\r
+\r
+# CHECK: dmtc1 s7,$f5\r
+0x44 0xb7 0x28 0x00\r
+\r
+# CHECK: dmult t3,k0\r
+0x01 0x7a 0x00 0x1c\r
+\r
+# CHECK: dmultu s7,t5\r
+0x02 0xed 0x00 0x1d\r
+\r
+# CHECK: dsll v1,t8,0x11\r
+0x00 0x18 0x1c 0x78\r
+\r
+# CHECK: dsllv gp,k1,t8\r
+0x03 0x1b 0xe0 0x14\r
+\r
+# CHECK: dsra at,at,0x1e\r
+0x00 0x01 0x0f 0xbb\r
+\r
+# CHECK: dsrav at,at,s8\r
+0x03 0xc1 0x08 0x17\r
+\r
+# CHECK: dsrl t2,gp,0x18\r
+0x00 0x1c 0x56 0x3a\r
+\r
+# CHECK: dsrlv gp,t2,s7\r
+0x02 0xea 0xe0 0x16\r
+\r
+# CHECK: dsubu gp,k1,t8\r
+0x03 0x78 0xe0 0x2f\r
+\r
+# CHECK: lw k1,-15155(at)\r
+0x8c 0x3b 0xc4 0xcd\r
+\r
+# CHECK: lui at,0x1\r
+0x3c 0x01 0x00 0x01\r
+\r
+# CHECK: lwu v1,-1746(v1)\r
+0x9c 0x63 0xf9 0x2e\r
+\r
+# CHECK: lui ra,0x1\r
+0x3c 0x1f 0x00 0x01\r
+\r
+# CHECK: sw k0,-15159(at)\r
+0xac 0x3a 0xc4 0xc9\r
+\r
+# CHECK: ld k0,3958(zero)\r
+0xdc 0x1a 0x0f 0x76\r
+\r
+# CHECK: sd a2,17767(zero)\r
+0xfc 0x06 0x45 0x67\r
--- /dev/null
+# RUN: llvm-mc --disassemble %s -triple=mips64el-unknown-linux\r
+\r
+# CHECK: daddiu t3,k0,31949\r
+0xcd 0x7c 0x4b 0x67\r
+\r
+# CHECK: daddu k0,at,t3\r
+0x2d 0xd0 0x2b 0x00\r
+\r
+# CHECK: ddiv zero,k0,s6\r
+0x1e 0x00 0x56 0x03\r
+\r
+# CHECK: ddivu zero,t1,t8\r
+0x1f 0x00 0x38 0x01\r
+\r
+# CHECK: dmfc1 v0,$f14\r
+0x00 0x70 0x22 0x44\r
+\r
+# CHECK: dmtc1 s7,$f5\r
+0x00 0x28 0xb7 0x44\r
+\r
+# CHECK: dmult t3,k0\r
+0x1c 0x00 0x7a 0x01\r
+\r
+# CHECK: dmultu s7,t5\r
+0x1d 0x00 0xed 0x02\r
+\r
+# CHECK: dsll v1,t8,0x11\r
+0x78 0x1c 0x18 0x00\r
+\r
+# CHECK: dsllv gp,k1,t8\r
+0x14 0xe0 0x1b 0x03\r
+\r
+# CHECK: dsra at,at,0x1e\r
+0xbb 0x0f 0x01 0x00\r
+\r
+# CHECK: dsrav at,at,s8\r
+0x17 0x08 0xc1 0x03\r
+\r
+# CHECK: dsrl t2,gp,0x18\r
+0x3a 0x56 0x1c 0x00\r
+\r
+# CHECK: dsrlv gp,t2,s7\r
+0x16 0xe0 0xea 0x02\r
+\r
+# CHECK: dsubu gp,k1,t8\r
+0x2f 0xe0 0x78 0x03\r
+\r
+# CHECK: lw k1,-15155(at)\r
+0xcd 0xc4 0x3b 0x8c\r
+\r
+# CHECK: lui at,0x1\r
+0x01 0x00 0x01 0x3c\r
+\r
+# CHECK: lwu v1,-1746(v1)\r
+0x2e 0xf9 0x63 0x9c\r
+\r
+# CHECK: lui ra,0x1\r
+0x01 0x00 0x1f 0x3c\r
+\r
+# CHECK: sw k0,-15159(at)\r
+0xc9 0xc4 0x3a 0xac\r
+\r
+# CHECK: ld k0,3958(zero)\r
+0x76 0x0f 0x1a 0xdc\r
+\r
+# CHECK: sd a2,17767(zero)\r
+0x67 0x45 0x06 0xfc\r
--- /dev/null
+# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mattr +mips64r2\r
+\r
+# CHECK: daddiu t3,k0,31949\r
+0x67 0x4b 0x7c 0xcd\r
+\r
+# CHECK: daddu k0,at,t3\r
+0x00 0x2b 0xd0 0x2d\r
+\r
+# CHECK: ddiv zero,k0,s6\r
+0x03 0x56 0x00 0x1e\r
+\r
+# CHECK: ddivu zero,t1,t8\r
+0x01 0x38 0x00 0x1f\r
+\r
+# CHECK: dmfc1 v0,$f14\r
+0x44 0x22 0x70 0x00\r
+\r
+# CHECK: dmtc1 s7,$f5\r
+0x44 0xb7 0x28 0x00\r
+\r
+# CHECK: dmult t3,k0\r
+0x01 0x7a 0x00 0x1c\r
+\r
+# CHECK: dmultu s7,t5\r
+0x02 0xed 0x00 0x1d\r
+\r
+# CHECK: dsll v1,t8,0x11\r
+0x00 0x18 0x1c 0x78\r
+\r
+# CHECK: dsllv gp,k1,t8\r
+0x03 0x1b 0xe0 0x14\r
+\r
+# CHECK: dsra at,at,0x1e\r
+0x00 0x01 0x0f 0xbb\r
+\r
+# CHECK: dsrav at,at,s8\r
+0x03 0xc1 0x08 0x17\r
+\r
+# CHECK: dsrl t2,gp,0x18\r
+0x00 0x1c 0x56 0x3a\r
+\r
+# CHECK: dsrlv gp,t2,s7\r
+0x02 0xea 0xe0 0x16\r
+\r
+# CHECK: dsubu gp,k1,t8\r
+0x03 0x78 0xe0 0x2f\r
+\r
+# CHECK: lw k1,-15155(at)\r
+0x8c 0x3b 0xc4 0xcd\r
+\r
+# CHECK: lui at,0x1\r
+0x3c 0x01 0x00 0x01\r
+\r
+# CHECK: lwu v1,-1746(v1)\r
+0x9c 0x63 0xf9 0x2e\r
+\r
+# CHECK: lui ra,0x1\r
+0x3c 0x1f 0x00 0x01\r
+\r
+# CHECK: sw k0,-15159(at)\r
+0xac 0x3a 0xc4 0xc9\r
+\r
+# CHECK: ld k0,3958(zero)\r
+0xdc 0x1a 0x0f 0x76\r
+\r
+# CHECK: sd a2,17767(zero)\r
+0xfc 0x06 0x45 0x67\r
+\r
+# CHECK: dclo t1,t8\r
+0x73 0x09 0x48 0x25\r
+\r
+# CHECK: dclz k0,t1\r
+0x71 0x3a 0xd0 0x24\r
+\r
+# CHECK: dext a3,gp,0x1d,0x1f\r
+0x7f 0x87 0xf7 0x43\r
+\r
+# CHECK: dins s4,gp,0xf,0x1\r
+0x7f 0x94 0x7b 0xc7\r
+\r
+# CHECK: dsbh a3,gp\r
+0x7c 0x1c 0x38 0xa4\r
+\r
+# CHECK: dshd v1,t6\r
+0x7c 0x0e 0x19 0x64\r
+\r
+# CHECK: drotr s4,k1,0x6\r
+0x00 0x3b 0xa1 0xba\r
+\r
+# CHECK: drotrv t8,s7,a1\r
+0x00 0xb7 0xc0 0x56\r
--- /dev/null
+# RUN: llvm-mc --disassemble %s -triple=mips64el-unknown-linux -mattr +mips64r2\r
+\r
+# CHECK: daddiu t3,k0,31949\r
+0xcd 0x7c 0x4b 0x67\r
+\r
+# CHECK: daddu k0,at,t3\r
+0x2d 0xd0 0x2b 0x00\r
+\r
+# CHECK: ddiv zero,k0,s6\r
+0x1e 0x00 0x56 0x03\r
+\r
+# CHECK: ddivu zero,t1,t8\r
+0x1f 0x00 0x38 0x01\r
+\r
+# CHECK: dmfc1 v0,$f14\r
+0x00 0x70 0x22 0x44\r
+\r
+# CHECK: dmtc1 s7,$f5\r
+0x00 0x28 0xb7 0x44\r
+\r
+# CHECK: dmult t3,k0\r
+0x1c 0x00 0x7a 0x01\r
+\r
+# CHECK: dmultu s7,t5\r
+0x1d 0x00 0xed 0x02\r
+\r
+# CHECK: dsll v1,t8,0x11\r
+0x78 0x1c 0x18 0x00\r
+\r
+# CHECK: dsllv gp,k1,t8\r
+0x14 0xe0 0x1b 0x03\r
+\r
+# CHECK: dsra at,at,0x1e\r
+0xbb 0x0f 0x01 0x00\r
+\r
+# CHECK: dsrav at,at,s8\r
+0x17 0x08 0xc1 0x03\r
+\r
+# CHECK: dsrl t2,gp,0x18\r
+0x3a 0x56 0x1c 0x00\r
+\r
+# CHECK: dsrlv gp,t2,s7\r
+0x16 0xe0 0xea 0x02\r
+\r
+# CHECK: dsubu gp,k1,t8\r
+0x2f 0xe0 0x78 0x03\r
+\r
+# CHECK: lw k1,-15155(at)\r
+0xcd 0xc4 0x3b 0x8c\r
+\r
+# CHECK: lui at,0x1\r
+0x01 0x00 0x01 0x3c\r
+\r
+# CHECK: lwu v1,-1746(v1)\r
+0x2e 0xf9 0x63 0x9c\r
+\r
+# CHECK: lui ra,0x1\r
+0x01 0x00 0x1f 0x3c\r
+\r
+# CHECK: sw k0,-15159(at)\r
+0xc9 0xc4 0x3a 0xac\r
+\r
+# CHECK: ld k0,3958(zero)\r
+0x76 0x0f 0x1a 0xdc\r
+\r
+# CHECK: sd a2,17767(zero)\r
+0x67 0x45 0x06 0xfc\r
+\r
+# CHECK: dclo t1,t8\r
+0x25 0x48 0x09 0x73\r
+\r
+# CHECK: dclz k0,t1\r
+0x24 0xd0 0x3a 0x71\r
+\r
+# CHECK: dext a3,gp,0x1d,0x1f\r
+0x43 0xf7 0x87 0x7f\r
+\r
+# CHECK: dins s4,gp,0xf,0x1\r
+0xc7 0x7b 0x94 0x7f\r
+\r
+# CHECK: dsbh a3,gp\r
+0xa4 0x38 0x1c 0x7c\r
+\r
+# CHECK: dshd v1,t6\r
+0x64 0x19 0x0e 0x7c\r
+\r
+# CHECK: drotr s4,k1,0x6\r
+0xba 0xa1 0x3b 0x00\r
+\r
+# CHECK: drotrv t8,s7,a1\r
+0x56 0xc0 0xb7 0x00\r
projects / oota-llvm.git / commitdiff