Silencing an MSVC warning about signed vs unsigned comparison mismatches.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186529 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
index f5d5e5a5cc6d7f273990eb250ef3c7d852448f51..bf341b36c1ef56030e6b88af224a4a0a7b6681ce 100644 (file)
--- a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
+++ b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
@@ -781,7 +781,7 @@ SDNode *SystemZDAGToDAGISel::tryRISBGZero(SDNode *N) {
   // all cases and are sometimes shorter.  Prefer to use RISBG for ANDs though,
   // since it is effectively a three-operand instruction in this case,
   // and since it can handle some masks that AND IMMEDIATE can't.
-  if (Count < (N->getOpcode() == ISD::AND ? 1 : 2))
+  if (Count < (N->getOpcode() == ISD::AND ? 1U : 2U))
     return 0;
 
   // Prefer register extensions like LLC over RISBG.