Oops. Didn't mean to check in a quick hack.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36227 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/MRegisterInfo.cpp b/lib/Target/MRegisterInfo.cpp
index ae9f20372fc80e42c3e3cf0086862d114942d40e..3af611da485d0ef0ba0f5da20c17da2e788e47f3 100644 (file)
--- a/lib/Target/MRegisterInfo.cpp
+++ b/lib/Target/MRegisterInfo.cpp
@@ -34,18 +34,26 @@ MRegisterInfo::MRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
 
 MRegisterInfo::~MRegisterInfo() {}
 
+/// getAllocatableSetForRC - Toggle the bits that represent allocatable
+/// registers for the specific register class.
+static void getAllocatableSetForRC(MachineFunction &MF,
+                                   const TargetRegisterClass *RC, BitVector &R){  
+  for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
+         E = RC->allocation_order_end(MF); I != E; ++I)
+    R.set(*I);
+}
+
 BitVector MRegisterInfo::getAllocatableSet(MachineFunction &MF,
                                            const TargetRegisterClass *RC) const {
   BitVector Allocatable(NumRegs);
-  for (MRegisterInfo::regclass_iterator I = regclass_begin(),
-         E = regclass_end(); I != E; ++I) {
-    const TargetRegisterClass *TRC = *I;
-    if (RC && TRC != RC)
-      continue;
-    for (TargetRegisterClass::iterator I = TRC->allocation_order_begin(MF),
-           E = TRC->allocation_order_end(MF); I != E; ++I)
-      Allocatable.set(*I);
+  if (RC) {
+    getAllocatableSetForRC(MF, RC, Allocatable);
+    return Allocatable;
   }
+
+  for (MRegisterInfo::regclass_iterator I = regclass_begin(),
+         E = regclass_end(); I != E; ++I)
+    getAllocatableSetForRC(MF, *I, Allocatable);
   return Allocatable;
 }