Instruction formats of SWP/SWPB were changed from LdStExFrm to MiscFrm. Modify the...

rdar://problem/9184053

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128285 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
index ff19a385cf439b3a934c22f03462b869b34970e1..3c48879eb3614da297fc76d297f2deead539805b 100644 (file)
--- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
@@ -2951,6 +2951,11 @@ static bool DisassembleMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
   case ARM::WFI:
   case ARM::SEV:
     return true;
+  case ARM::SWP:
+  case ARM::SWPB:
+    // SWP, SWPB: Rd Rm Rn
+    // Delegate to DisassembleLdStExFrm()....
+    return DisassembleLdStExFrm(MI, Opcode, insn, NumOps, NumOpsAdded, B);
   default:
     break;
   }

diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt
index 16e6981382ea4fac41ebc327f21f7936cf302f85..f4836772d5d44e5e4e560c0aeaaa7b1d4c0c7e8f 100644 (file)
--- a/test/MC/Disassembler/ARM/arm-tests.txt
+++ b/test/MC/Disassembler/ARM/arm-tests.txt
@@ -184,3 +184,6 @@
 
 # CHECK:       ldmdb   sp, {r0, r4, r8, r11, r12, pc}
 0x11 0x99 0x1d 0xe9
+
+# CHECK:       swpge   r3, r2, [r6]
+0x92 0x30 0x06 0xa1