[AArch64] Use the correct register class for ORR.

While fixing up the register classes in the machine combiner in a previous
commit I missed one.

This fixes the last one and adds a test case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221308 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AArch64/AArch64InstrInfo.cpp b/lib/Target/AArch64/AArch64InstrInfo.cpp
index c8592bd1c8834353d14bb726892d4e3b2b95ae50..c5bf3c79477f40dae7cb27a08cd66dbdd0f45b7a 100644 (file)
--- a/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -2805,7 +2805,7 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
       RC = &AArch64::GPR32RegClass;
     } else {
       OrrOpc = AArch64::ORRXri;
-      OrrRC = &AArch64::GPR64RegClass;
+      OrrRC = &AArch64::GPR64spRegClass;
       BitSize = 64;
       ZeroReg = AArch64::XZR;
       Opc = AArch64::MADDXrrr;

diff --git a/test/CodeGen/AArch64/madd-combiner.ll b/test/CodeGen/AArch64/madd-combiner.ll
index e7f171b9048742551c666e396d790fbb170c01c9..7c9787a7281aadd68d60832ebb036cc6b72024e7 100644 (file)
--- a/test/CodeGen/AArch64/madd-combiner.ll
+++ b/test/CodeGen/AArch64/madd-combiner.ll
@@ -1,4 +1,5 @@
-; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-apple-darwin            -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -verify-machineinstrs < %s | FileCheck %s
 
 ; Test that we use the correct register class.
 define i32 @mul_add_imm(i32 %a, i32 %b) {
@@ -18,3 +19,19 @@ define i32 @mul_sub_imm1(i32 %a, i32 %b) {
   %2 = sub i32 4, %1
   ret i32 %2
 }
+
+; bugpoint reduced test case. This only tests that we pass the MI verifier.
+define void @mul_add_imm2() {
+entry:
+  br label %for.body
+for.body:
+  br i1 undef, label %for.body, label %for.body8
+for.body8:
+  %0 = mul i64 undef, -3
+  %mul1971 = add i64 %0, -3
+  %cmp7 = icmp slt i64 %mul1971, 1390451930000
+  br i1 %cmp7, label %for.body8, label %for.end20
+for.end20:
+  ret void
+}
+