Replace SDT_PPCShiftOp in favor of SDTIntBinOps. This allows it to work

with 32 or 64-bit operands/results.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48026 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index a0b2512c6dfe8deb99bd0423b74b6df94a669a26..a0f6ccc2b4c470111f95127138539cbeaae691cd 100644 (file)
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -20,9 +20,6 @@ include "PPCInstrFormats.td"
 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
   SDTCisVT<0, f64>, SDTCisPtrTy<1>
 ]>;
-def SDT_PPCShiftOp : SDTypeProfile<1, 2, [   // PPCshl, PPCsra, PPCsrl
-  SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>
-]>;
 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
 def SDT_PPCCallSeqEnd   : SDCallSeqEnd<[ SDTCisVT<0, i32>,
                                          SDTCisVT<1, i32> ]>;
@@ -84,9 +81,9 @@ def PPCvperm    : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
 
 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
 // amounts.  These nodes are generated by the multi-precision shift code.
-def PPCsrl        : SDNode<"PPCISD::SRL"       , SDT_PPCShiftOp>;
-def PPCsra        : SDNode<"PPCISD::SRA"       , SDT_PPCShiftOp>;
-def PPCshl        : SDNode<"PPCISD::SHL"       , SDT_PPCShiftOp>;
+def PPCsrl        : SDNode<"PPCISD::SRL"       , SDTIntBinOp>;
+def PPCsra        : SDNode<"PPCISD::SRA"       , SDTIntBinOp>;
+def PPCshl        : SDNode<"PPCISD::SHL"       , SDTIntBinOp>;
 
 def PPCextsw_32   : SDNode<"PPCISD::EXTSW_32"  , SDTIntUnaryOp>;
 def PPCstd_32     : SDNode<"PPCISD::STD_32"    , SDTStore,