let Predicates = [HasNEON, HasFullFP16] in {
def v1i16_indexed : BaseSIMDIndexed<1, U, 1, 0b00, opc,
- FPR16Op, FPR16Op, V128, VectorIndexH,
+ FPR16Op, FPR16Op, V128_lo, VectorIndexH,
asm, ".h", "", "", ".h",
[(set (f16 FPR16Op:$Rd),
(OpNode (f16 FPR16Op:$Rn),
- (f16 (vector_extract (v8f16 V128:$Rm),
+ (f16 (vector_extract (v8f16 V128_lo:$Rm),
VectorIndexH:$idx))))]> {
bits<3> idx;
let Inst{11} = idx{2};
let Predicates = [HasNEON, HasFullFP16] in {
def v1i16_indexed : BaseSIMDIndexedTied<1, U, 1, 0b00, opc,
- FPR16Op, FPR16Op, V128, VectorIndexH,
+ FPR16Op, FPR16Op, V128_lo, VectorIndexH,
asm, ".h", "", "", ".h", []> {
bits<3> idx;
let Inst{11} = idx{2};
// CHECK: error: invalid operand for instruction
// CHECK-NEXT: fmulx v2.8h, v3.8h, v17.h[6]
// CHECK-NEXT: ^
+
+ fmla h0, h1, v16.h[3]
+ fmla h2, h3, v17.h[6]
+
+// CHECK: error: invalid operand for instruction
+// CHECK-NEXT: fmla h0, h1, v16.h[3]
+// CHECK-NEXT: ^
+// CHECK: error: invalid operand for instruction
+// CHECK-NEXT: fmla h2, h3, v17.h[6]
+// CHECK-NEXT: ^
+
+ fmls h0, h1, v16.h[3]
+ fmls h2, h3, v17.h[6]
+
+// CHECK: error: invalid operand for instruction
+// CHECK-NEXT: fmls h0, h1, v16.h[3]
+// CHECK-NEXT: ^
+// CHECK: error: invalid operand for instruction
+// CHECK-NEXT: fmls h2, h3, v17.h[6]
+// CHECK-NEXT: ^
+
+ fmul h0, h1, v16.h[3]
+ fmul h2, h3, v17.h[6]
+
+// CHECK: error: invalid operand for instruction
+// CHECK-NEXT: fmul h0, h1, v16.h[3]
+// CHECK-NEXT: ^
+// CHECK: error: invalid operand for instruction
+// CHECK-NEXT: fmul h2, h3, v17.h[6]
+// CHECK-NEXT: ^
+
+ fmulx h0, h1, v16.h[3]
+ fmulx h2, h3, v17.h[6]
+
+// CHECK: error: invalid operand for instruction
+// CHECK-NEXT: fmulx h0, h1, v16.h[3]
+// CHECK-NEXT: ^
+// CHECK: error: invalid operand for instruction
+// CHECK-NEXT: fmulx h2, h3, v17.h[6]
+// CHECK-NEXT: ^