[X86][AVX] Tidied up BROADCASTPD/BROADCASTPS tests

Regenerate tests using update_llc_test_checks.py

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254886 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/X86/avx-vbroadcast.ll b/test/CodeGen/X86/avx-vbroadcast.ll
index 8b8c11b858755afa3081fedfdbd4bfdc1f0f8365..bfc9149b107df2fd977c3be7d3c190b6d0644f8f 100644 (file)
--- a/test/CodeGen/X86/avx-vbroadcast.ll
+++ b/test/CodeGen/X86/avx-vbroadcast.ll
@@ -1,7 +1,11 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py

 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
 
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
 

-; CHECK: vbroadcastsd (%

 define <4 x i64> @A(i64* %ptr) nounwind uwtable readnone ssp {
 define <4 x i64> @A(i64* %ptr) nounwind uwtable readnone ssp {

+; CHECK-LABEL: A:
+; CHECK:       ## BB#0: ## %entry
+; CHECK-NEXT:    vbroadcastsd (%rdi), %ymm0
+; CHECK-NEXT:    retq

 entry:
   %q = load i64, i64* %ptr, align 8
   %vecinit.i = insertelement <4 x i64> undef, i64 %q, i32 0
 entry:
   %q = load i64, i64* %ptr, align 8
   %vecinit.i = insertelement <4 x i64> undef, i64 %q, i32 0


@@ -11,8 +15,11 @@ entry:
   ret <4 x i64> %vecinit6.i
 }
 
   ret <4 x i64> %vecinit6.i
 }
 

-; CHECK: vbroadcastss (%

 define <8 x i32> @B(i32* %ptr) nounwind uwtable readnone ssp {
 define <8 x i32> @B(i32* %ptr) nounwind uwtable readnone ssp {

+; CHECK-LABEL: B:
+; CHECK:       ## BB#0: ## %entry
+; CHECK-NEXT:    vbroadcastss (%rdi), %ymm0
+; CHECK-NEXT:    retq

 entry:
   %q = load i32, i32* %ptr, align 4
   %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
 entry:
   %q = load i32, i32* %ptr, align 4
   %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0


@@ -22,8 +29,11 @@ entry:
   ret <8 x i32> %vecinit6.i
 }
 
   ret <8 x i32> %vecinit6.i
 }
 

-; CHECK: vbroadcastsd (%

 define <4 x double> @C(double* %ptr) nounwind uwtable readnone ssp {
 define <4 x double> @C(double* %ptr) nounwind uwtable readnone ssp {

+; CHECK-LABEL: C:
+; CHECK:       ## BB#0: ## %entry
+; CHECK-NEXT:    vbroadcastsd (%rdi), %ymm0
+; CHECK-NEXT:    retq

 entry:
   %q = load double, double* %ptr, align 8
   %vecinit.i = insertelement <4 x double> undef, double %q, i32 0
 entry:
   %q = load double, double* %ptr, align 8
   %vecinit.i = insertelement <4 x double> undef, double %q, i32 0


@@ -33,8 +43,11 @@ entry:
   ret <4 x double> %vecinit6.i
 }
 
   ret <4 x double> %vecinit6.i
 }
 

-; CHECK: vbroadcastss (%

 define <8 x float> @D(float* %ptr) nounwind uwtable readnone ssp {
 define <8 x float> @D(float* %ptr) nounwind uwtable readnone ssp {

+; CHECK-LABEL: D:
+; CHECK:       ## BB#0: ## %entry
+; CHECK-NEXT:    vbroadcastss (%rdi), %ymm0
+; CHECK-NEXT:    retq

 entry:
   %q = load float, float* %ptr, align 4
   %vecinit.i = insertelement <8 x float> undef, float %q, i32 0
 entry:
   %q = load float, float* %ptr, align 4
   %vecinit.i = insertelement <8 x float> undef, float %q, i32 0


@@ -46,8 +59,11 @@ entry:
 
 ;;;; 128-bit versions
 
 
 ;;;; 128-bit versions
 

-; CHECK: vbroadcastss (%

 define <4 x float> @e(float* %ptr) nounwind uwtable readnone ssp {
 define <4 x float> @e(float* %ptr) nounwind uwtable readnone ssp {

+; CHECK-LABEL: e:
+; CHECK:       ## BB#0: ## %entry
+; CHECK-NEXT:    vbroadcastss (%rdi), %xmm0
+; CHECK-NEXT:    retq

 entry:
   %q = load float, float* %ptr, align 4
   %vecinit.i = insertelement <4 x float> undef, float %q, i32 0
 entry:
   %q = load float, float* %ptr, align 4
   %vecinit.i = insertelement <4 x float> undef, float %q, i32 0


@@ -57,12 +73,14 @@ entry:
   ret <4 x float> %vecinit6.i
 }
 
   ret <4 x float> %vecinit6.i
 }
 

-
-; CHECK: _e2
-; CHECK-NOT: vbroadcastss
-; CHECK: ret
+; Don't broadcast constants on pre-AVX2 hardware.

 define <4 x float> @_e2(float* %ptr) nounwind uwtable readnone ssp {
 define <4 x float> @_e2(float* %ptr) nounwind uwtable readnone ssp {

-    %vecinit.i = insertelement <4 x float> undef, float      0xbf80000000000000, i32 0
+; CHECK-LABEL: _e2:
+; CHECK:       ## BB#0: ## %entry
+; CHECK-NEXT:    vmovaps {{.*#+}} xmm0 = [-7.812500e-03,-7.812500e-03,-7.812500e-03,-7.812500e-03]
+; CHECK-NEXT:    retq
+entry:
+   %vecinit.i = insertelement <4 x float> undef, float       0xbf80000000000000, i32 0

   %vecinit2.i = insertelement <4 x float> %vecinit.i, float  0xbf80000000000000, i32 1
   %vecinit4.i = insertelement <4 x float> %vecinit2.i, float 0xbf80000000000000, i32 2
   %vecinit6.i = insertelement <4 x float> %vecinit4.i, float 0xbf80000000000000, i32 3
   %vecinit2.i = insertelement <4 x float> %vecinit.i, float  0xbf80000000000000, i32 1
   %vecinit4.i = insertelement <4 x float> %vecinit2.i, float 0xbf80000000000000, i32 2
   %vecinit6.i = insertelement <4 x float> %vecinit4.i, float 0xbf80000000000000, i32 3


@@ -70,8 +88,11 @@ define <4 x float> @_e2(float* %ptr) nounwind uwtable readnone ssp {
 }
 
 
 }
 
 

-; CHECK: vbroadcastss (%

 define <4 x i32> @F(i32* %ptr) nounwind uwtable readnone ssp {
 define <4 x i32> @F(i32* %ptr) nounwind uwtable readnone ssp {

+; CHECK-LABEL: F:
+; CHECK:       ## BB#0: ## %entry
+; CHECK-NEXT:    vbroadcastss (%rdi), %xmm0
+; CHECK-NEXT:    retq

 entry:
   %q = load i32, i32* %ptr, align 4
   %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
 entry:
   %q = load i32, i32* %ptr, align 4
   %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0


@@ -83,10 +104,12 @@ entry:
 
 ; Unsupported vbroadcasts
 
 
 ; Unsupported vbroadcasts
 

-; CHECK: _G
-; CHECK-NOT: broadcast (%
-; CHECK: ret

 define <2 x i64> @G(i64* %ptr) nounwind uwtable readnone ssp {
 define <2 x i64> @G(i64* %ptr) nounwind uwtable readnone ssp {

+; CHECK-LABEL: G:
+; CHECK:       ## BB#0: ## %entry
+; CHECK-NEXT:    vmovq {{.*#+}} xmm0 = mem[0],zero
+; CHECK-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
+; CHECK-NEXT:    retq

 entry:
   %q = load i64, i64* %ptr, align 8
   %vecinit.i = insertelement <2 x i64> undef, i64 %q, i32 0
 entry:
   %q = load i64, i64* %ptr, align 8
   %vecinit.i = insertelement <2 x i64> undef, i64 %q, i32 0


@@ -94,18 +117,21 @@ entry:
   ret <2 x i64> %vecinit2.i
 }
 
   ret <2 x i64> %vecinit2.i
 }
 

-; CHECK: _H
-; CHECK-NOT: broadcast
-; CHECK: ret

 define <4 x i32> @H(<4 x i32> %a) {
 define <4 x i32> @H(<4 x i32> %a) {

+; CHECK-LABEL: H:
+; CHECK:       ## BB#0: ## %entry
+; CHECK-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
+; CHECK-NEXT:    retq
+entry:

   %x = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
   ret <4 x i32> %x
 }
 
   %x = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
   ret <4 x i32> %x
 }
 

-; CHECK: _I
-; CHECK-NOT: broadcast (%
-; CHECK: ret

 define <2 x double> @I(double* %ptr) nounwind uwtable readnone ssp {
 define <2 x double> @I(double* %ptr) nounwind uwtable readnone ssp {

+; CHECK-LABEL: I:
+; CHECK:       ## BB#0: ## %entry
+; CHECK-NEXT:    vmovddup {{.*#+}} xmm0 = mem[0,0]
+; CHECK-NEXT:    retq

 entry:
   %q = load double, double* %ptr, align 4
   %vecinit.i = insertelement <2 x double> undef, double %q, i32 0
 entry:
   %q = load double, double* %ptr, align 4
   %vecinit.i = insertelement <2 x double> undef, double %q, i32 0


@@ -113,10 +139,13 @@ entry:
   ret <2 x double> %vecinit2.i
 }
 
   ret <2 x double> %vecinit2.i
 }
 

-; CHECK: _RR
-; CHECK: vbroadcastss (%
-; CHECK: ret

 define <4 x float> @_RR(float* %ptr, i32* %k) nounwind uwtable readnone ssp {
 define <4 x float> @_RR(float* %ptr, i32* %k) nounwind uwtable readnone ssp {

+; CHECK-LABEL: _RR:
+; CHECK:       ## BB#0: ## %entry
+; CHECK-NEXT:    vbroadcastss (%rdi), %xmm0
+; CHECK-NEXT:    movl (%rsi), %eax
+; CHECK-NEXT:    movl %eax, (%rax)
+; CHECK-NEXT:    retq

 entry:
   %q = load float, float* %ptr, align 4
   %vecinit.i = insertelement <4 x float> undef, float %q, i32 0
 entry:
   %q = load float, float* %ptr, align 4
   %vecinit.i = insertelement <4 x float> undef, float %q, i32 0


@@ -129,11 +158,11 @@ entry:
   ret <4 x float> %vecinit6.i
 }
 
   ret <4 x float> %vecinit6.i
 }
 

-
-; CHECK: _RR2
-; CHECK: vbroadcastss (%
-; CHECK: ret

 define <4 x float> @_RR2(float* %ptr, i32* %k) nounwind uwtable readnone ssp {
 define <4 x float> @_RR2(float* %ptr, i32* %k) nounwind uwtable readnone ssp {

+; CHECK-LABEL: _RR2:
+; CHECK:       ## BB#0: ## %entry
+; CHECK-NEXT:    vbroadcastss (%rdi), %xmm0
+; CHECK-NEXT:    retq

 entry:
   %q = load float, float* %ptr, align 4
   %v = insertelement <4 x float> undef, float %q, i32 0
 entry:
   %q = load float, float* %ptr, align 4
   %v = insertelement <4 x float> undef, float %q, i32 0


@@ -141,16 +170,15 @@ entry:
   ret <4 x float> %t
 }
 
   ret <4 x float> %t
 }
 

-

 ; These tests check that a vbroadcast instruction is used when we have a splat
 ; formed from a concat_vectors (via the shufflevector) of two BUILD_VECTORs
 ; (via the insertelements).
 
 ; These tests check that a vbroadcast instruction is used when we have a splat
 ; formed from a concat_vectors (via the shufflevector) of two BUILD_VECTORs
 ; (via the insertelements).
 

-; CHECK-LABEL: splat_concat1
-; CHECK-NOT: vinsertf128
-; CHECK: vbroadcastss (%
-; CHECK-NEXT: ret

 define <8 x float> @splat_concat1(float* %p) {
 define <8 x float> @splat_concat1(float* %p) {

+; CHECK-LABEL: splat_concat1:
+; CHECK:       ## BB#0:
+; CHECK-NEXT:    vbroadcastss (%rdi), %ymm0
+; CHECK-NEXT:    retq

   %1 = load float, float* %p, align 4
   %2 = insertelement <4 x float> undef, float %1, i32 0
   %3 = insertelement <4 x float> %2, float %1, i32 1
   %1 = load float, float* %p, align 4
   %2 = insertelement <4 x float> undef, float %1, i32 0
   %3 = insertelement <4 x float> %2, float %1, i32 1


@@ -160,11 +188,11 @@ define <8 x float> @splat_concat1(float* %p) {
   ret <8 x float> %6
 }
 
   ret <8 x float> %6
 }
 

-; CHECK-LABEL: splat_concat2
-; CHECK-NOT: vinsertf128
-; CHECK: vbroadcastss (%
-; CHECK-NEXT: ret

 define <8 x float> @splat_concat2(float* %p) {
 define <8 x float> @splat_concat2(float* %p) {

+; CHECK-LABEL: splat_concat2:
+; CHECK:       ## BB#0:
+; CHECK-NEXT:    vbroadcastss (%rdi), %ymm0
+; CHECK-NEXT:    retq

   %1 = load float, float* %p, align 4
   %2 = insertelement <4 x float> undef, float %1, i32 0
   %3 = insertelement <4 x float> %2, float %1, i32 1
   %1 = load float, float* %p, align 4
   %2 = insertelement <4 x float> undef, float %1, i32 0
   %3 = insertelement <4 x float> %2, float %1, i32 1


@@ -178,11 +206,11 @@ define <8 x float> @splat_concat2(float* %p) {
   ret <8 x float> %10
 }
 
   ret <8 x float> %10
 }
 

-; CHECK-LABEL: splat_concat3
-; CHECK-NOT: vinsertf128
-; CHECK: vbroadcastsd (%
-; CHECK-NEXT: ret

 define <4 x double> @splat_concat3(double* %p) {
 define <4 x double> @splat_concat3(double* %p) {

+; CHECK-LABEL: splat_concat3:
+; CHECK:       ## BB#0:
+; CHECK-NEXT:    vbroadcastsd (%rdi), %ymm0
+; CHECK-NEXT:    retq

   %1 = load double, double* %p, align 8
   %2 = insertelement <2 x double> undef, double %1, i32 0
   %3 = insertelement <2 x double> %2, double %1, i32 1
   %1 = load double, double* %p, align 8
   %2 = insertelement <2 x double> undef, double %1, i32 0
   %3 = insertelement <2 x double> %2, double %1, i32 1


@@ -190,11 +218,11 @@ define <4 x double> @splat_concat3(double* %p) {
   ret <4 x double> %4
 }
 
   ret <4 x double> %4
 }
 

-; CHECK-LABEL: splat_concat4
-; CHECK-NOT: vinsertf128
-; CHECK: vbroadcastsd (%
-; CHECK-NEXT: ret

 define <4 x double> @splat_concat4(double* %p) {
 define <4 x double> @splat_concat4(double* %p) {

+; CHECK-LABEL: splat_concat4:
+; CHECK:       ## BB#0:
+; CHECK-NEXT:    vbroadcastsd (%rdi), %ymm0
+; CHECK-NEXT:    retq

   %1 = load double, double* %p, align 8
   %2 = insertelement <2 x double> undef, double %1, i32 0
   %3 = insertelement <2 x double> %2, double %1, i32 1
   %1 = load double, double* %p, align 8
   %2 = insertelement <2 x double> undef, double %1, i32 0
   %3 = insertelement <2 x double> %2, double %1, i32 1


@@ -203,4 +231,3 @@ define <4 x double> @splat_concat4(double* %p) {
   %6 = shufflevector <2 x double> %3, <2 x double> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   ret <4 x double> %6
 }
   %6 = shufflevector <2 x double> %3, <2 x double> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   ret <4 x double> %6
 }

-