Thumb2 assembly parsing and encoding for SXTB/SXTB16/SXTH.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140047 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
index cef8bbe17ad130761ca5cd27ce9e78aca7911cd8..ae988eec40e926878a0439ff3343131503448300 100644 (file)
--- a/lib/Target/ARM/ARMInstrThumb2.td
+++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -1785,8 +1785,6 @@ def t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
                         BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
 def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">;
 
-// TODO: SXT(A){B|H}16
-
 // Zero extenders
 
 let AddedComplexity = 16 in {
@@ -3931,3 +3929,17 @@ def : t2InstAlias<"sxtah${p} $Rd, $Rn, $Rm",
                 (t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
 def : t2InstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
                 (t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
+def : t2InstAlias<"sxtb${p} $Rd, $Rm",
+                (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
+def : t2InstAlias<"sxtb16${p} $Rd, $Rm",
+                (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
+def : t2InstAlias<"sxth${p} $Rd, $Rm",
+                (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
+
+// Extend instruction w/o the ".w" optional width specifier.
+def : t2InstAlias<"sxtb${p} $Rd, $Rm$rot",
+                  (t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
+def : t2InstAlias<"sxtb16${p} $Rd, $Rm$rot",
+                  (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
+def : t2InstAlias<"sxth${p} $Rd, $Rm$rot",
+                  (t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;

diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 7646c5c31ca7b6a36c74002e439933519d749bdb..46b0589cc59718d9dafca634850f9b04eb0d2df5 100644 (file)
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -2254,15 +2254,11 @@ ARMAsmParser::OperandMatchResultTy ARMAsmParser::
 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
   const AsmToken &Tok = Parser.getTok();
   SMLoc S = Tok.getLoc();
-  if (Tok.isNot(AsmToken::Identifier)) {
-    Error(S, "rotate operator 'ror' expected");
-    return MatchOperand_ParseFail;
-  }
+  if (Tok.isNot(AsmToken::Identifier))
+    return MatchOperand_NoMatch;
   StringRef ShiftName = Tok.getString();
-  if (ShiftName != "ror" && ShiftName != "ROR") {
-    Error(S, "rotate operator 'ror' expected");
-    return MatchOperand_ParseFail;
-  }
+  if (ShiftName != "ror" && ShiftName != "ROR")
+    return MatchOperand_NoMatch;
   Parser.Lex(); // Eat the operator.
 
   // A '#' and a rotate amount.
@@ -3867,6 +3863,28 @@ processInstruction(MCInst &Inst,
     }
     break;
   }
+  case ARM::t2SXTH:
+  case ARM::t2SXTB: {
+    // If we can use the 16-bit encoding and the user didn't explicitly
+    // request the 32-bit variant, transform it here.
+    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
+        isARMLowRegister(Inst.getOperand(1).getReg()) &&
+        Inst.getOperand(2).getImm() == 0 &&
+        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
+         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
+      unsigned NewOpc = (Inst.getOpcode() == ARM::t2SXTH) ?
+        ARM::tSXTH : ARM::tSXTB;
+      // The operands aren't the same for thumb1 (no rotate operand).
+      MCInst TmpInst;
+      TmpInst.setOpcode(NewOpc);
+      TmpInst.addOperand(Inst.getOperand(0));
+      TmpInst.addOperand(Inst.getOperand(1));
+      TmpInst.addOperand(Inst.getOperand(3));
+      TmpInst.addOperand(Inst.getOperand(4));
+      Inst = TmpInst;
+    }
+    break;
+  }
   case ARM::t2IT: {
     // The mask bits for all but the first condition are represented as
     // the low bit of the condition code value implies 't'. We currently

diff --git a/test/MC/ARM/basic-thumb2-instructions.s b/test/MC/ARM/basic-thumb2-instructions.s
index 8be979be9811c78a2a120bdaf67612719e11ed53..56fd7c4b18edd70888fb64677697c8b6d75f74d5 100644 (file)
--- a/test/MC/ARM/basic-thumb2-instructions.s
+++ b/test/MC/ARM/basic-thumb2-instructions.s
@@ -2504,3 +2504,111 @@ _func:
 @ CHECK: ite   hi                      @ encoding: [0x8c,0xbf]
 @ CHECK: sxtahhi r6, r1, r6             @ encoding: [0x01,0xfa,0x86,0xf6]
 @ CHECK: sxtahls r2, r2, r4, ror #16    @ encoding: [0x02,0xfa,0xa4,0xf2]
+
+
+@------------------------------------------------------------------------------
+@ SXTB
+@------------------------------------------------------------------------------
+        sxtb r5, r6, ror #0
+        sxtb r6, r9, ror #8
+        sxtb r8, r3, ror #24
+        ite ge
+        sxtbge r2, r4
+        sxtblt r5, r1, ror #16
+
+@ CHECK: sxtb  r5, r6                  @ encoding: [0x75,0xb2]
+@ CHECK: sxtb.w        r6, r9, ror #8          @ encoding: [0x4f,0xfa,0x99,0xf6]
+@ CHECK: sxtb.w        r8, r3, ror #24         @ encoding: [0x4f,0xfa,0xb3,0xf8]
+@ CHECK: ite   ge                      @ encoding: [0xac,0xbf]
+@ CHECK: sxtbge        r2, r4                  @ encoding: [0x62,0xb2]
+@ CHECK: sxtblt.w      r5, r1, ror #16 @ encoding: [0x4f,0xfa,0xa1,0xf5]
+
+
+@------------------------------------------------------------------------------
+@ SXTB16
+@------------------------------------------------------------------------------
+        sxtb16 r1, r4
+        sxtb16 r6, r7, ror #0
+        sxtb16 r3, r1, ror #16
+        ite cs
+        sxtb16cs r3, r5, ror #8
+        sxtb16lo r2, r3, ror #24
+
+@ CHECK: sxtb16        r1, r4                  @ encoding: [0x2f,0xfa,0x84,0xf1]
+@ CHECK: sxtb16        r6, r7                  @ encoding: [0x2f,0xfa,0x87,0xf6]
+@ CHECK: sxtb16        r3, r1, ror #16         @ encoding: [0x2f,0xfa,0xa1,0xf3]
+@ CHECK: ite   hs                      @ encoding: [0x2c,0xbf]
+@ CHECK: sxtb16hs      r3, r5, ror #8  @ encoding: [0x2f,0xfa,0x95,0xf3]
+@ CHECK: sxtb16lo      r2, r3, ror #24 @ encoding: [0x2f,0xfa,0xb3,0xf2]
+
+
+@------------------------------------------------------------------------------
+@ SXTH
+@------------------------------------------------------------------------------
+        sxth r1, r6, ror #0
+        sxth r3, r8, ror #8
+        sxth r9, r3, ror #24
+        itt ne
+        sxthne r3, r9
+        sxthne r2, r2, ror #16
+
+@ CHECK: sxth  r1, r6                  @ encoding: [0x31,0xb2]
+@ CHECK: sxth.w        r3, r8, ror #8          @ encoding: [0x0f,0xfa,0x98,0xf3]
+@ CHECK: sxth.w        r9, r3, ror #24         @ encoding: [0x0f,0xfa,0xb3,0xf9]
+@ CHECK: itt   ne                      @ encoding: [0x1c,0xbf]
+@ CHECK: sxthne.w      r3, r9          @ encoding: [0x0f,0xfa,0x89,0xf3]
+@ CHECK: sxthne.w      r2, r2, ror #16 @ encoding: [0x0f,0xfa,0xa2,0xf2]
+
+
+@------------------------------------------------------------------------------
+@ SXTB
+@------------------------------------------------------------------------------
+        sxtb r5, r6, ror #0
+        sxtb.w r6, r9, ror #8
+        sxtb r8, r3, ror #24
+        ite ge
+        sxtbge r2, r4
+        sxtblt r5, r1, ror #16
+
+@ CHECK: sxtb  r5, r6                  @ encoding: [0x75,0xb2]
+@ CHECK: sxtb.w        r6, r9, ror #8          @ encoding: [0x4f,0xfa,0x99,0xf6]
+@ CHECK: sxtb.w        r8, r3, ror #24         @ encoding: [0x4f,0xfa,0xb3,0xf8]
+@ CHECK: ite   ge                      @ encoding: [0xac,0xbf]
+@ CHECK: sxtbge        r2, r4                  @ encoding: [0x62,0xb2]
+@ CHECK: sxtblt.w      r5, r1, ror #16 @ encoding: [0x4f,0xfa,0xa1,0xf5]
+
+
+@------------------------------------------------------------------------------
+@ SXTB16
+@------------------------------------------------------------------------------
+        sxtb16 r1, r4
+        sxtb16 r6, r7, ror #0
+        sxtb16 r3, r1, ror #16
+        ite cs
+        sxtb16cs r3, r5, ror #8
+        sxtb16lo r2, r3, ror #24
+
+@ CHECK: sxtb16        r1, r4                  @ encoding: [0x2f,0xfa,0x84,0xf1]
+@ CHECK: sxtb16        r6, r7                  @ encoding: [0x2f,0xfa,0x87,0xf6]
+@ CHECK: sxtb16        r3, r1, ror #16         @ encoding: [0x2f,0xfa,0xa1,0xf3]
+@ CHECK: ite   hs                      @ encoding: [0x2c,0xbf]
+@ CHECK: sxtb16hs      r3, r5, ror #8  @ encoding: [0x2f,0xfa,0x95,0xf3]
+@ CHECK: sxtb16lo      r2, r3, ror #24 @ encoding: [0x2f,0xfa,0xb3,0xf2]
+
+
+@------------------------------------------------------------------------------
+@ SXTH
+@------------------------------------------------------------------------------
+        sxth r1, r6, ror #0
+        sxth.w r3, r8, ror #8
+        sxth r9, r3, ror #24
+        itt ne
+        sxthne r3, r9
+        sxthne r2, r2, ror #16
+
+@ CHECK: sxth  r1, r6                  @ encoding: [0x31,0xb2]
+@ CHECK: sxth.w        r3, r8, ror #8          @ encoding: [0x0f,0xfa,0x98,0xf3]
+@ CHECK: sxth.w        r9, r3, ror #24         @ encoding: [0x0f,0xfa,0xb3,0xf9]
+@ CHECK: itt   ne                      @ encoding: [0x1c,0xbf]
+@ CHECK: sxthne.w      r3, r9          @ encoding: [0x0f,0xfa,0x89,0xf3]
+@ CHECK: sxthne.w      r2, r2, ror #16 @ encoding: [0x0f,0xfa,0xa2,0xf2]

diff --git a/test/MC/ARM/diagnostics.s b/test/MC/ARM/diagnostics.s
index 8b26328c21421823de6805018103a5b12d4ced30..41dde080522d7a73400ff07c22ff3b30ff5e8554 100644 (file)
--- a/test/MC/ARM/diagnostics.s
+++ b/test/MC/ARM/diagnostics.s
@@ -248,7 +248,7 @@
         sxtah r9, r3, r3, ror #-8
         sxtb16ge r2, r3, lsr #24
 
-@ CHECK-ERRORS: error: rotate operator 'ror' expected
+@ CHECK-ERRORS: error: invalid operand for instruction
 @ CHECK-ERRORS:         sxtb r8, r3, #8
 @ CHECK-ERRORS:                      ^
 @ CHECK-ERRORS: error: '#' expected
@@ -269,7 +269,7 @@
 @ CHECK-ERRORS: error: 'ror' rotate amount must be 8, 16, or 24
 @ CHECK-ERRORS:         sxtah r9, r3, r3, ror #-8
 @ CHECK-ERRORS:                                ^
-@ CHECK-ERRORS: error: rotate operator 'ror' expected
+@ CHECK-ERRORS: error: invalid operand for instruction
 @ CHECK-ERRORS:         sxtb16ge r2, r3, lsr #24
 @ CHECK-ERRORS:                          ^