[Hexagon] Adding basic disassembler.

Marking all instructions as CodeGenOnly since encoding bits are not set yet.
http://reviews.llvm.org/D5829?vs=on&id=15023&whitespace=ignore-all#toc

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220393 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Hexagon/CMakeLists.txt b/lib/Target/Hexagon/CMakeLists.txt
index 3627905a3e620f3a7283cbde4f223b6133fc4ec6..a7f0f49dcb908c9786d49ded5a0e40a69141930f 100644 (file)
--- a/lib/Target/Hexagon/CMakeLists.txt
+++ b/lib/Target/Hexagon/CMakeLists.txt
@@ -1,8 +1,9 @@
-set(LLVM_TARGET_DEFINITIONS Hexagon.td)
-
-tablegen(LLVM HexagonGenRegisterInfo.inc -gen-register-info)
-tablegen(LLVM HexagonGenInstrInfo.inc -gen-instr-info)
-tablegen(LLVM HexagonGenMCCodeEmitter.inc -gen-emitter)
+set(LLVM_TARGET_DEFINITIONS Hexagon.td)\r
+\r
+tablegen(LLVM HexagonGenDisassemblerTables.inc -gen-disassembler)\r
+tablegen(LLVM HexagonGenRegisterInfo.inc -gen-register-info)\r
+tablegen(LLVM HexagonGenInstrInfo.inc -gen-instr-info)\r
+tablegen(LLVM HexagonGenMCCodeEmitter.inc -gen-emitter)\r

 tablegen(LLVM HexagonGenAsmWriter.inc -gen-asm-writer)
 tablegen(LLVM HexagonGenDAGISel.inc -gen-dag-isel)
 tablegen(LLVM HexagonGenCallingConv.inc -gen-callingconv)
 tablegen(LLVM HexagonGenAsmWriter.inc -gen-asm-writer)
 tablegen(LLVM HexagonGenDAGISel.inc -gen-dag-isel)
 tablegen(LLVM HexagonGenCallingConv.inc -gen-callingconv)


@@ -38,7 +39,8 @@ add_llvm_target(HexagonCodeGen
   HexagonCopyToCombine.cpp
 )
 
   HexagonCopyToCombine.cpp
 )
 

-add_subdirectory(TargetInfo)
-add_subdirectory(InstPrinter)
-add_subdirectory(MCTargetDesc)
-
+add_subdirectory(TargetInfo)\r
+add_subdirectory(InstPrinter)\r
+add_subdirectory(MCTargetDesc)\r
+add_subdirectory(Disassembler)\r
+\r

diff --git a/lib/Target/Hexagon/Disassembler/CMakeLists.txt b/lib/Target/Hexagon/Disassembler/CMakeLists.txt
new file mode 100644 (file)
index 0000000..9862974
--- /dev/null
+++ b/lib/Target/Hexagon/Disassembler/CMakeLists.txt
@@ -0,0 +1,3 @@
+add_llvm_library(LLVMHexagonDisassembler\r
+  HexagonDisassembler.cpp\r
+  )\r

diff --git a/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp b/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
new file mode 100644 (file)
index 0000000..688b8e6
--- /dev/null
+++ b/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
@@ -0,0 +1,131 @@
+//===-- HexagonDisassembler.cpp - Disassembler for Hexagon ISA ------------===//\r
+//\r
+//                     The LLVM Compiler Infrastructure\r
+//\r
+// This file is distributed under the University of Illinois Open Source\r
+// License. See LICENSE.TXT for details.\r
+//\r
+//===----------------------------------------------------------------------===//\r
+\r
+#include "MCTargetDesc/HexagonBaseInfo.h"\r
+#include "MCTargetDesc/HexagonMCTargetDesc.h"\r
+\r
+#include "llvm/MC/MCContext.h"\r
+#include "llvm/MC/MCDisassembler.h"\r
+#include "llvm/MC/MCExpr.h"\r
+#include "llvm/MC/MCFixedLenDisassembler.h"\r
+#include "llvm/MC/MCInst.h"\r
+#include "llvm/MC/MCInstrDesc.h"\r
+#include "llvm/MC/MCSubtargetInfo.h"\r
+#include "llvm/Support/Debug.h"\r
+#include "llvm/Support/ErrorHandling.h"\r
+#include "llvm/Support/LEB128.h"\r
+#include "llvm/Support/MemoryObject.h"\r
+#include "llvm/Support/raw_ostream.h"\r
+#include "llvm/Support/TargetRegistry.h"\r
+#include "llvm/Support/Endian.h"\r
+\r
+#include <vector>\r
+#include <array>\r
+\r
+using namespace llvm;\r
+\r
+#define DEBUG_TYPE "hexagon-disassembler"\r
+\r
+using DecodeStatus = MCDisassembler::DecodeStatus;\r
+\r
+namespace {\r
+/// \brief Hexagon disassembler for all Hexagon platforms.\r
+class HexagonDisassembler : public MCDisassembler {\r
+public:\r
+  HexagonDisassembler(MCSubtargetInfo const &STI, MCContext &Ctx)\r
+      : MCDisassembler(STI, Ctx) {}\r
+\r
+  DecodeStatus getInstruction(MCInst &instr, uint64_t &size,\r
+                              MemoryObject const &region, uint64_t address,\r
+                              raw_ostream &vStream, raw_ostream &cStream) const override;\r
+};\r
+}\r
+\r
+static const uint16_t IntRegDecoderTable[] = {\r
+    Hexagon::R0,  Hexagon::R1,  Hexagon::R2,  Hexagon::R3,  Hexagon::R4,\r
+    Hexagon::R5,  Hexagon::R6,  Hexagon::R7,  Hexagon::R8,  Hexagon::R9,\r
+    Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,\r
+    Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,\r
+    Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24,\r
+    Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29,\r
+    Hexagon::R30, Hexagon::R31};\r
+\r
+static const uint16_t DoubleRegDecoderTable[] = {\r
+    Hexagon::D0,  Hexagon::D1,  Hexagon::D2,  Hexagon::D3,\r
+    Hexagon::D4,  Hexagon::D5,  Hexagon::D6,  Hexagon::D7,\r
+    Hexagon::D8,  Hexagon::D9,  Hexagon::D10, Hexagon::D11,\r
+    Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15};\r
+\r
+static const uint16_t PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1,\r
+                                               Hexagon::P2, Hexagon::P3};\r
+\r
+static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,\r
+                                               uint64_t /*Address*/,\r
+                                               void const *Decoder) {\r
+  if (RegNo > 31)\r
+    return MCDisassembler::Fail;\r
+\r
+  unsigned Register = IntRegDecoderTable[RegNo];\r
+  Inst.addOperand(MCOperand::CreateReg(Register));\r
+  return MCDisassembler::Success;\r
+}\r
+\r
+static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,\r
+                                                  uint64_t /*Address*/,\r
+                                                  void const *Decoder) {\r
+  if (RegNo > 15)\r
+    return MCDisassembler::Fail;\r
+\r
+  unsigned Register = DoubleRegDecoderTable[RegNo];\r
+  Inst.addOperand(MCOperand::CreateReg(Register));\r
+  return MCDisassembler::Success;\r
+}\r
+\r
+static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,\r
+                                                uint64_t /*Address*/,\r
+                                                void const *Decoder) {\r
+  if (RegNo > 3)\r
+    return MCDisassembler::Fail;\r
+\r
+  unsigned Register = PredRegDecoderTable[RegNo];\r
+  Inst.addOperand(MCOperand::CreateReg(Register));\r
+  return MCDisassembler::Success;\r
+}\r
+\r
+#include "HexagonGenDisassemblerTables.inc"\r
+\r
+static MCDisassembler *createHexagonDisassembler(Target const &T,\r
+                                                 MCSubtargetInfo const &STI,\r
+                                                 MCContext &Ctx) {\r
+  return new HexagonDisassembler(STI, Ctx);\r
+}\r
+\r
+extern "C" void LLVMInitializeHexagonDisassembler() {\r
+  TargetRegistry::RegisterMCDisassembler(TheHexagonTarget,\r
+                                         createHexagonDisassembler);\r
+}\r
+\r
+DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size,\r
+                                                 MemoryObject const &Region,\r
+                                                 uint64_t Address,\r
+                                                 raw_ostream &os,\r
+                                                 raw_ostream &cs) const {\r
+  std::array<uint8_t, 4> Bytes;\r
+  Size = 4;\r
+  if (Region.readBytes(Address, Bytes.size(), Bytes.data()) == -1) {\r
+    return MCDisassembler::Fail;\r
+  }\r
+  uint32_t insn =\r
+      llvm::support::endian::read<uint32_t, llvm::support::little,\r
+                                  llvm::support::unaligned>(Bytes.data());\r
+\r
+  // Remove parse bits.\r
+  insn &= ~static_cast<uint32_t>(HexagonII::InstParseBits::INST_PARSE_MASK);\r
+  return decodeInstruction(DecoderTable32, MI, insn, Address, this, STI);\r
+}\r

diff --git a/lib/Target/Hexagon/Disassembler/LLVMBuild.txt b/lib/Target/Hexagon/Disassembler/LLVMBuild.txt
new file mode 100644 (file)
index 0000000..eef09e3
--- /dev/null
+++ b/lib/Target/Hexagon/Disassembler/LLVMBuild.txt
@@ -0,0 +1,23 @@
+;===-- ./lib/Target/Hexagon/Disassembler/LLVMBuild.txt ---------*- Conf -*--===;\r
+;\r
+;                     The LLVM Compiler Infrastructure\r
+;\r
+; This file is distributed under the University of Illinois Open Source\r
+; License. See LICENSE.TXT for details.\r
+;\r
+;===------------------------------------------------------------------------===;\r
+;\r
+; This is an LLVMBuild description file for the components in this subdirectory.\r
+;\r
+; For more information on the LLVMBuild system, please see:\r
+;\r
+;   http://llvm.org/docs/LLVMBuild.html\r
+;\r
+;===------------------------------------------------------------------------===;\r
+\r
+[component_0]\r
+type = Library\r
+name = HexagonDisassembler\r
+parent = Hexagon\r
+required_libraries = HexagonDesc MCDisassembler HexagonInfo Support\r
+add_to_library_groups = Hexagon\r

diff --git a/lib/Target/Hexagon/Disassembler/Makefile b/lib/Target/Hexagon/Disassembler/Makefile
new file mode 100644 (file)
index 0000000..e55fd58
--- /dev/null
+++ b/lib/Target/Hexagon/Disassembler/Makefile
@@ -0,0 +1,16 @@
+##===-- lib/Target/Hexagon/Disassembler/Makefile -----------*- Makefile -*-===##\r
+#\r
+#                     The LLVM Compiler Infrastructure\r
+#\r
+# This file is distributed under the University of Illinois Open Source\r
+# License. See LICENSE.TXT for details.\r
+#\r
+##===----------------------------------------------------------------------===##\r
+\r
+LEVEL = ../../../..\r
+LIBRARYNAME = LLVMHexagonDisassembler\r
+\r
+# Hack: we need to include 'main' target directory to grab private headers\r
+CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..\r
+\r
+include $(LEVEL)/Makefile.common\r

diff --git a/lib/Target/Hexagon/HexagonInstrFormats.td b/lib/Target/Hexagon/HexagonInstrFormats.td
index 105734349321986e2370dd5ed7939363f82453ea..cc27c4c8ed8526f3ddff9784eca94c5d3b514760 100644 (file)
--- a/lib/Target/Hexagon/HexagonInstrFormats.td
+++ b/lib/Target/Hexagon/HexagonInstrFormats.td
@@ -92,12 +92,18 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
   let AsmString = asmstr;
   let Pattern = pattern;
   let Constraints = cstr;
   let AsmString = asmstr;
   let Pattern = pattern;
   let Constraints = cstr;

-  let Itinerary = itin;
-  let Size = 4;
-
-  // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
-
-  // Instruction type according to the ISA.
+  let Itinerary = itin;\r
+  let Size = 4;\r
+\r
+  // SoftFail is a field the disassembler can use to provide a way for\r
+  // instructions to not match without killing the whole decode process. It is\r
+  // mainly used for ARM, but Tablegen expects this field to exist or it fails\r
+  // to build the decode table.\r
+  field bits<32> SoftFail = 0;\r
+\r
+  // *** Must match MCTargetDesc/HexagonBaseInfo.h ***\r
+\r
+  // Instruction type according to the ISA.\r

   IType Type = type;
   let TSFlags{4-0} = Type.Value;
 
   IType Type = type;
   let TSFlags{4-0} = Type.Value;
 


@@ -186,6 +192,7 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
                                     "");
   let PNewValue = !if(isPredicatedNew, "new", "");
   let NValueST = !if(isNVStore, "true", "false");
                                     "");
   let PNewValue = !if(isPredicatedNew, "new", "");
   let NValueST = !if(isNVStore, "true", "false");

+  let isCodeGenOnly = 1;

 
   // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
 }
 
   // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
 }

diff --git a/lib/Target/Hexagon/HexagonInstrInfo.td b/lib/Target/Hexagon/HexagonInstrInfo.td
index 4dcf101ea3ad1fdc434173e5926da6484b016325..42ecab9538a116c0a64773ca41f5333129330457 100644 (file)
--- a/lib/Target/Hexagon/HexagonInstrInfo.td
+++ b/lib/Target/Hexagon/HexagonInstrInfo.td
@@ -225,7 +225,7 @@ def AND_ri : ALU32_ri<(outs IntRegs:$dst),
                                            s10ExtPred:$src2))]>, ImmRegRel;
 
 // Nop.
                                            s10ExtPred:$src2))]>, ImmRegRel;
 
 // Nop.

-let neverHasSideEffects = 1 in
+let neverHasSideEffects = 1, isCodeGenOnly = 0 in

 def NOP : ALU32_rr<(outs), (ins),
           "nop",
           []>;
 def NOP : ALU32_rr<(outs), (ins),
           "nop",
           []>;


@@ -753,7 +753,7 @@ def HexagonBR_JT: SDNode<"HexagonISD::BR_JT", SDHexagonBR_JT, [SDNPHasChain]>;
 
 let InputType = "imm", isBarrier = 1, isPredicable = 1,
 Defs = [PC], isExtendable = 1, opExtendable = 0, isExtentSigned = 1,
 
 let InputType = "imm", isBarrier = 1, isPredicable = 1,
 Defs = [PC], isExtendable = 1, opExtendable = 0, isExtentSigned = 1,

-opExtentBits = 24 in
+opExtentBits = 24, isCodeGenOnly = 0 in

 class T_JMP <dag InsDag, list<dag> JumpList = []>
             : JInst<(outs), InsDag,
             "jump $dst" , JumpList> {
 class T_JMP <dag InsDag, list<dag> JumpList = []>
             : JInst<(outs), InsDag,
             "jump $dst" , JumpList> {

diff --git a/lib/Target/Hexagon/LLVMBuild.txt b/lib/Target/Hexagon/LLVMBuild.txt
index a436b6e0454ea67fad39d704c3a8cb935107ac59..2cacdca0b3059765684e8d66066e4e42366c38fe 100644 (file)
--- a/lib/Target/Hexagon/LLVMBuild.txt
+++ b/lib/Target/Hexagon/LLVMBuild.txt
@@ -13,13 +13,13 @@
 ;
 ;   http://llvm.org/docs/LLVMBuild.html
 ;
 ;
 ;   http://llvm.org/docs/LLVMBuild.html
 ;

-;===------------------------------------------------------------------------===;
-
-[common]
-subdirectories = InstPrinter MCTargetDesc TargetInfo
-
-[component_0]
-type = TargetGroup
+;===------------------------------------------------------------------------===;\r
+\r
+[common]\r
+subdirectories = Disassembler InstPrinter MCTargetDesc TargetInfo\r
+\r
+[component_0]\r
+type = TargetGroup\r

 name = Hexagon
 parent = Target
 has_asmprinter = 1
 name = Hexagon
 parent = Target
 has_asmprinter = 1

diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h b/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h
index 01044f0fa8cef0f3054af282038719101a7abd26..c8e2d965ccfac921fdcc9462bb4f03a61972cdcc 100644 (file)
--- a/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h
+++ b/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h
@@ -17,12 +17,14 @@
 #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H
 #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H
 
 #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H
 #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H
 

-#include "HexagonMCTargetDesc.h"
-#include "llvm/Support/ErrorHandling.h"
-
-namespace llvm {
-
-/// HexagonII - This namespace holds all of the target specific flags that
+#include "HexagonMCTargetDesc.h"\r
+#include "llvm/Support/ErrorHandling.h"\r
+\r
+#include <stdint.h>\r
+\r
+namespace llvm {\r
+\r
+/// HexagonII - This namespace holds all of the target specific flags that\r

 /// instruction info tracks.
 ///
 namespace HexagonII {
 /// instruction info tracks.
 ///
 namespace HexagonII {


@@ -186,11 +188,20 @@ namespace HexagonII {
     MO_LO16, MO_HI16,
 
     // Offset from the base of the SDA.
     MO_LO16, MO_HI16,
 
     // Offset from the base of the SDA.

-    MO_GPREL
-  };
-
-} // End namespace HexagonII.
-
-} // End namespace llvm.
+    MO_GPREL\r
+  };\r
+\r
+  enum class InstParseBits : uint32_t {\r
+    INST_PARSE_MASK       = 0x0000c000,\r
+    INST_PARSE_PACKET_END = 0x0000c000,\r
+    INST_PARSE_LOOP_END   = 0x00008000,\r
+    INST_PARSE_NOT_END    = 0x00004000,\r
+    INST_PARSE_DUPLEX     = 0x00000000,\r
+    INST_PARSE_EXTENDER   = 0x00000000\r
+  };\r
+\r
+} // End namespace HexagonII.\r
+\r
+} // End namespace llvm.\r

 
 #endif
 
 #endif

diff --git a/lib/Target/Hexagon/Makefile b/lib/Target/Hexagon/Makefile
index d4c93ca8731ecef764a483364688119586cef95c..ccc0bbac588f090e37d1429eda2f1225a9e2b2b9 100644 (file)
--- a/lib/Target/Hexagon/Makefile
+++ b/lib/Target/Hexagon/Makefile
@@ -14,11 +14,12 @@ TARGET = Hexagon
 BUILT_SOURCES = HexagonGenRegisterInfo.inc \
                 HexagonGenInstrInfo.inc  \
                 HexagonGenAsmWriter.inc \
 BUILT_SOURCES = HexagonGenRegisterInfo.inc \
                 HexagonGenInstrInfo.inc  \
                 HexagonGenAsmWriter.inc \

-                HexagonGenDAGISel.inc HexagonGenSubtargetInfo.inc \
-                HexagonGenCallingConv.inc \
-                HexagonGenDFAPacketizer.inc \
-                HexagonGenMCCodeEmitter.inc
-
-DIRS = InstPrinter TargetInfo MCTargetDesc
-
-include $(LEVEL)/Makefile.common
+                HexagonGenDAGISel.inc HexagonGenSubtargetInfo.inc \\r
+                HexagonGenCallingConv.inc \\r
+                HexagonGenDFAPacketizer.inc \\r
+                HexagonGenMCCodeEmitter.inc \\r
+                HexagonGenDisassemblerTables.inc\r
+\r
+DIRS = InstPrinter TargetInfo MCTargetDesc Disassembler\r
+\r
+include $(LEVEL)/Makefile.common\r