AArch64/ARM64: move ARM64 into AArch64's place
authorTim Northover <tnorthover@apple.com>
Sat, 24 May 2014 12:50:23 +0000 (12:50 +0000)
committerTim Northover <tnorthover@apple.com>
Sat, 24 May 2014 12:50:23 +0000 (12:50 +0000)
This commit starts with a "git mv ARM64 AArch64" and continues out
from there, renaming the C++ classes, intrinsics, and other
target-local objects for consistency.

"ARM64" test directories are also moved, and tests that began their
life in ARM64 use an arm64 triple, those from AArch64 use an aarch64
triple. Both should be equivalent though.

This finishes the AArch64 merge, and everyone should feel free to
continue committing as normal now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209577 91177308-0d34-0410-b5e6-96231b3b80d8

1063 files changed:
CMakeLists.txt
autoconf/configure.ac
cmake/config-ix.cmake
configure
docs/LangRef.rst
include/llvm/IR/Intrinsics.td
include/llvm/IR/IntrinsicsAArch64.td [new file with mode: 0644]
include/llvm/IR/IntrinsicsARM64.td [deleted file]
lib/ExecutionEngine/RuntimeDyld/RuntimeDyldMachO.cpp
lib/ExecutionEngine/RuntimeDyld/RuntimeDyldMachO.h
lib/LTO/LTOCodeGenerator.cpp
lib/LTO/LTOModule.cpp
lib/MC/MCObjectFileInfo.cpp
lib/Target/AArch64/AArch64.h [new file with mode: 0644]
lib/Target/AArch64/AArch64.td [new file with mode: 0644]
lib/Target/AArch64/AArch64AddressTypePromotion.cpp [new file with mode: 0644]
lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp [new file with mode: 0644]
lib/Target/AArch64/AArch64AsmPrinter.cpp [new file with mode: 0644]
lib/Target/AArch64/AArch64BranchRelaxation.cpp [new file with mode: 0644]
lib/Target/AArch64/AArch64CallingConv.h [new file with mode: 0644]
lib/Target/AArch64/AArch64CallingConvention.td [new file with mode: 0644]
lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp [new file with mode: 0644]
lib/Target/AArch64/AArch64CollectLOH.cpp [new file with mode: 0644]
lib/Target/AArch64/AArch64ConditionalCompares.cpp [new file with mode: 0644]
lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp [new file with mode: 0644]
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp [new file with mode: 0644]
lib/Target/AArch64/AArch64FastISel.cpp [new file with mode: 0644]
lib/Target/AArch64/AArch64FrameLowering.cpp [new file with mode: 0644]
lib/Target/AArch64/AArch64FrameLowering.h [new file with mode: 0644]
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp [new file with mode: 0644]
lib/Target/AArch64/AArch64ISelLowering.cpp [new file with mode: 0644]
lib/Target/AArch64/AArch64ISelLowering.h [new file with mode: 0644]
lib/Target/AArch64/AArch64InstrAtomics.td [new file with mode: 0644]
lib/Target/AArch64/AArch64InstrFormats.td [new file with mode: 0644]
lib/Target/AArch64/AArch64InstrInfo.cpp [new file with mode: 0644]
lib/Target/AArch64/AArch64InstrInfo.h [new file with mode: 0644]
lib/Target/AArch64/AArch64InstrInfo.td [new file with mode: 0644]
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp [new file with mode: 0644]
lib/Target/AArch64/AArch64MCInstLower.cpp [new file with mode: 0644]
lib/Target/AArch64/AArch64MCInstLower.h [new file with mode: 0644]
lib/Target/AArch64/AArch64MachineFunctionInfo.h [new file with mode: 0644]
lib/Target/AArch64/AArch64PerfectShuffle.h [new file with mode: 0644]
lib/Target/AArch64/AArch64PromoteConstant.cpp [new file with mode: 0644]
lib/Target/AArch64/AArch64RegisterInfo.cpp [new file with mode: 0644]
lib/Target/AArch64/AArch64RegisterInfo.h [new file with mode: 0644]
lib/Target/AArch64/AArch64RegisterInfo.td [new file with mode: 0644]
lib/Target/AArch64/AArch64SchedA53.td [new file with mode: 0644]
lib/Target/AArch64/AArch64SchedCyclone.td [new file with mode: 0644]
lib/Target/AArch64/AArch64Schedule.td [new file with mode: 0644]
lib/Target/AArch64/AArch64SelectionDAGInfo.cpp [new file with mode: 0644]
lib/Target/AArch64/AArch64SelectionDAGInfo.h [new file with mode: 0644]
lib/Target/AArch64/AArch64StorePairSuppress.cpp [new file with mode: 0644]
lib/Target/AArch64/AArch64Subtarget.cpp [new file with mode: 0644]
lib/Target/AArch64/AArch64Subtarget.h [new file with mode: 0644]
lib/Target/AArch64/AArch64TargetMachine.cpp [new file with mode: 0644]
lib/Target/AArch64/AArch64TargetMachine.h [new file with mode: 0644]
lib/Target/AArch64/AArch64TargetObjectFile.cpp [new file with mode: 0644]
lib/Target/AArch64/AArch64TargetObjectFile.h [new file with mode: 0644]
lib/Target/AArch64/AArch64TargetTransformInfo.cpp [new file with mode: 0644]
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp [new file with mode: 0644]
lib/Target/AArch64/AsmParser/CMakeLists.txt [new file with mode: 0644]
lib/Target/AArch64/AsmParser/LLVMBuild.txt [new file with mode: 0644]
lib/Target/AArch64/AsmParser/Makefile [new file with mode: 0644]
lib/Target/AArch64/CMakeLists.txt [new file with mode: 0644]
lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp [new file with mode: 0644]
lib/Target/AArch64/Disassembler/AArch64Disassembler.h [new file with mode: 0644]
lib/Target/AArch64/Disassembler/AArch64ExternalSymbolizer.cpp [new file with mode: 0644]
lib/Target/AArch64/Disassembler/AArch64ExternalSymbolizer.h [new file with mode: 0644]
lib/Target/AArch64/Disassembler/CMakeLists.txt [new file with mode: 0644]
lib/Target/AArch64/Disassembler/LLVMBuild.txt [new file with mode: 0644]
lib/Target/AArch64/Disassembler/Makefile [new file with mode: 0644]
lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp [new file with mode: 0644]
lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h [new file with mode: 0644]
lib/Target/AArch64/InstPrinter/CMakeLists.txt [new file with mode: 0644]
lib/Target/AArch64/InstPrinter/LLVMBuild.txt [new file with mode: 0644]
lib/Target/AArch64/InstPrinter/Makefile [new file with mode: 0644]
lib/Target/AArch64/LLVMBuild.txt [new file with mode: 0644]
lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h [new file with mode: 0644]
lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp [new file with mode: 0644]
lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp [new file with mode: 0644]
lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp [new file with mode: 0644]
lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.h [new file with mode: 0644]
lib/Target/AArch64/MCTargetDesc/AArch64FixupKinds.h [new file with mode: 0644]
lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp [new file with mode: 0644]
lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h [new file with mode: 0644]
lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp [new file with mode: 0644]
lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.cpp [new file with mode: 0644]
lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.h [new file with mode: 0644]
lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp [new file with mode: 0644]
lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h [new file with mode: 0644]
lib/Target/AArch64/MCTargetDesc/AArch64MachObjectWriter.cpp [new file with mode: 0644]
lib/Target/AArch64/MCTargetDesc/CMakeLists.txt [new file with mode: 0644]
lib/Target/AArch64/MCTargetDesc/LLVMBuild.txt [new file with mode: 0644]
lib/Target/AArch64/MCTargetDesc/Makefile [new file with mode: 0644]
lib/Target/AArch64/Makefile [new file with mode: 0644]
lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp [new file with mode: 0644]
lib/Target/AArch64/TargetInfo/CMakeLists.txt [new file with mode: 0644]
lib/Target/AArch64/TargetInfo/LLVMBuild.txt [new file with mode: 0644]
lib/Target/AArch64/TargetInfo/Makefile [new file with mode: 0644]
lib/Target/AArch64/Utils/AArch64BaseInfo.cpp [new file with mode: 0644]
lib/Target/AArch64/Utils/AArch64BaseInfo.h [new file with mode: 0644]
lib/Target/AArch64/Utils/CMakeLists.txt [new file with mode: 0644]
lib/Target/AArch64/Utils/LLVMBuild.txt [new file with mode: 0644]
lib/Target/AArch64/Utils/Makefile [new file with mode: 0644]
lib/Target/ARM64/ARM64.h [deleted file]
lib/Target/ARM64/ARM64.td [deleted file]
lib/Target/ARM64/ARM64AddressTypePromotion.cpp [deleted file]
lib/Target/ARM64/ARM64AdvSIMDScalarPass.cpp [deleted file]
lib/Target/ARM64/ARM64AsmPrinter.cpp [deleted file]
lib/Target/ARM64/ARM64BranchRelaxation.cpp [deleted file]
lib/Target/ARM64/ARM64CallingConv.h [deleted file]
lib/Target/ARM64/ARM64CallingConvention.td [deleted file]
lib/Target/ARM64/ARM64CleanupLocalDynamicTLSPass.cpp [deleted file]
lib/Target/ARM64/ARM64CollectLOH.cpp [deleted file]
lib/Target/ARM64/ARM64ConditionalCompares.cpp [deleted file]
lib/Target/ARM64/ARM64DeadRegisterDefinitionsPass.cpp [deleted file]
lib/Target/ARM64/ARM64ExpandPseudoInsts.cpp [deleted file]
lib/Target/ARM64/ARM64FastISel.cpp [deleted file]
lib/Target/ARM64/ARM64FrameLowering.cpp [deleted file]
lib/Target/ARM64/ARM64FrameLowering.h [deleted file]
lib/Target/ARM64/ARM64ISelDAGToDAG.cpp [deleted file]
lib/Target/ARM64/ARM64ISelLowering.cpp [deleted file]
lib/Target/ARM64/ARM64ISelLowering.h [deleted file]
lib/Target/ARM64/ARM64InstrAtomics.td [deleted file]
lib/Target/ARM64/ARM64InstrFormats.td [deleted file]
lib/Target/ARM64/ARM64InstrInfo.cpp [deleted file]
lib/Target/ARM64/ARM64InstrInfo.h [deleted file]
lib/Target/ARM64/ARM64InstrInfo.td [deleted file]
lib/Target/ARM64/ARM64LoadStoreOptimizer.cpp [deleted file]
lib/Target/ARM64/ARM64MCInstLower.cpp [deleted file]
lib/Target/ARM64/ARM64MCInstLower.h [deleted file]
lib/Target/ARM64/ARM64MachineFunctionInfo.h [deleted file]
lib/Target/ARM64/ARM64PerfectShuffle.h [deleted file]
lib/Target/ARM64/ARM64PromoteConstant.cpp [deleted file]
lib/Target/ARM64/ARM64RegisterInfo.cpp [deleted file]
lib/Target/ARM64/ARM64RegisterInfo.h [deleted file]
lib/Target/ARM64/ARM64RegisterInfo.td [deleted file]
lib/Target/ARM64/ARM64SchedA53.td [deleted file]
lib/Target/ARM64/ARM64SchedCyclone.td [deleted file]
lib/Target/ARM64/ARM64Schedule.td [deleted file]
lib/Target/ARM64/ARM64SelectionDAGInfo.cpp [deleted file]
lib/Target/ARM64/ARM64SelectionDAGInfo.h [deleted file]
lib/Target/ARM64/ARM64StorePairSuppress.cpp [deleted file]
lib/Target/ARM64/ARM64Subtarget.cpp [deleted file]
lib/Target/ARM64/ARM64Subtarget.h [deleted file]
lib/Target/ARM64/ARM64TargetMachine.cpp [deleted file]
lib/Target/ARM64/ARM64TargetMachine.h [deleted file]
lib/Target/ARM64/ARM64TargetObjectFile.cpp [deleted file]
lib/Target/ARM64/ARM64TargetObjectFile.h [deleted file]
lib/Target/ARM64/ARM64TargetTransformInfo.cpp [deleted file]
lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp [deleted file]
lib/Target/ARM64/AsmParser/CMakeLists.txt [deleted file]
lib/Target/ARM64/AsmParser/LLVMBuild.txt [deleted file]
lib/Target/ARM64/AsmParser/Makefile [deleted file]
lib/Target/ARM64/CMakeLists.txt [deleted file]
lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp [deleted file]
lib/Target/ARM64/Disassembler/ARM64Disassembler.h [deleted file]
lib/Target/ARM64/Disassembler/ARM64ExternalSymbolizer.cpp [deleted file]
lib/Target/ARM64/Disassembler/ARM64ExternalSymbolizer.h [deleted file]
lib/Target/ARM64/Disassembler/CMakeLists.txt [deleted file]
lib/Target/ARM64/Disassembler/LLVMBuild.txt [deleted file]
lib/Target/ARM64/Disassembler/Makefile [deleted file]
lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp [deleted file]
lib/Target/ARM64/InstPrinter/ARM64InstPrinter.h [deleted file]
lib/Target/ARM64/InstPrinter/CMakeLists.txt [deleted file]
lib/Target/ARM64/InstPrinter/LLVMBuild.txt [deleted file]
lib/Target/ARM64/InstPrinter/Makefile [deleted file]
lib/Target/ARM64/LLVMBuild.txt [deleted file]
lib/Target/ARM64/MCTargetDesc/ARM64AddressingModes.h [deleted file]
lib/Target/ARM64/MCTargetDesc/ARM64AsmBackend.cpp [deleted file]
lib/Target/ARM64/MCTargetDesc/ARM64ELFObjectWriter.cpp [deleted file]
lib/Target/ARM64/MCTargetDesc/ARM64ELFStreamer.cpp [deleted file]
lib/Target/ARM64/MCTargetDesc/ARM64ELFStreamer.h [deleted file]
lib/Target/ARM64/MCTargetDesc/ARM64FixupKinds.h [deleted file]
lib/Target/ARM64/MCTargetDesc/ARM64MCAsmInfo.cpp [deleted file]
lib/Target/ARM64/MCTargetDesc/ARM64MCAsmInfo.h [deleted file]
lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp [deleted file]
lib/Target/ARM64/MCTargetDesc/ARM64MCExpr.cpp [deleted file]
lib/Target/ARM64/MCTargetDesc/ARM64MCExpr.h [deleted file]
lib/Target/ARM64/MCTargetDesc/ARM64MCTargetDesc.cpp [deleted file]
lib/Target/ARM64/MCTargetDesc/ARM64MCTargetDesc.h [deleted file]
lib/Target/ARM64/MCTargetDesc/ARM64MachObjectWriter.cpp [deleted file]
lib/Target/ARM64/MCTargetDesc/CMakeLists.txt [deleted file]
lib/Target/ARM64/MCTargetDesc/LLVMBuild.txt [deleted file]
lib/Target/ARM64/MCTargetDesc/Makefile [deleted file]
lib/Target/ARM64/Makefile [deleted file]
lib/Target/ARM64/TargetInfo/ARM64TargetInfo.cpp [deleted file]
lib/Target/ARM64/TargetInfo/CMakeLists.txt [deleted file]
lib/Target/ARM64/TargetInfo/LLVMBuild.txt [deleted file]
lib/Target/ARM64/TargetInfo/Makefile [deleted file]
lib/Target/ARM64/Utils/ARM64BaseInfo.cpp [deleted file]
lib/Target/ARM64/Utils/ARM64BaseInfo.h [deleted file]
lib/Target/ARM64/Utils/CMakeLists.txt [deleted file]
lib/Target/ARM64/Utils/LLVMBuild.txt [deleted file]
lib/Target/ARM64/Utils/Makefile [deleted file]
lib/Target/LLVMBuild.txt
lib/Transforms/InstCombine/InstCombineCalls.cpp
test/Analysis/CostModel/AArch64/lit.local.cfg [new file with mode: 0644]
test/Analysis/CostModel/AArch64/select.ll [new file with mode: 0644]
test/Analysis/CostModel/AArch64/store.ll [new file with mode: 0644]
test/Analysis/CostModel/ARM64/lit.local.cfg [deleted file]
test/Analysis/CostModel/ARM64/select.ll [deleted file]
test/Analysis/CostModel/ARM64/store.ll [deleted file]
test/CodeGen/AArch64/128bit_load_store.ll
test/CodeGen/AArch64/aarch64-neon-v1i1-setcc.ll [new file with mode: 0644]
test/CodeGen/AArch64/addsub.ll
test/CodeGen/AArch64/addsub_ext.ll
test/CodeGen/AArch64/alloca.ll
test/CodeGen/AArch64/analyze-branch.ll
test/CodeGen/AArch64/arm64-2011-03-09-CPSRSpill.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-2011-03-17-AsmPrinterCrash.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-2011-03-21-Unaligned-Frame-Index.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-2011-04-21-CPSRBug.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-2011-10-18-LdStOptBug.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-2012-01-11-ComparisonDAGCrash.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-2012-05-07-DAGCombineVectorExtract.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-2012-05-07-MemcpyAlignBug.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-2012-05-09-LOADgot-bug.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-2012-06-06-FPToUI.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-2012-07-11-InstrEmitterBug.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-2013-01-13-ffast-fcmp.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-2013-01-23-frem-crash.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-2013-01-23-sext-crash.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-2013-02-12-shufv8i8.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-2014-04-16-AnInfiniteLoopInDAGCombine.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-2014-04-28-sqshl-uqshl-i64Contant.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-2014-04-29-EXT-undef-mask.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-aapcs.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-abi-varargs.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-abi.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-abi_align.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-addp.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-addr-mode-folding.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-addr-type-promotion.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-addrmode.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-alloc-no-stack-realign.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-alloca-frame-pointer-offset.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-andCmpBrToTBZ.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-ands-bad-peephole.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-anyregcc-crash.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-anyregcc.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-arith-saturating.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-arith.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-arm64-dead-def-elimination-flag.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-atomic-128.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-atomic.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-basic-pic.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-big-endian-bitconverts.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-big-endian-eh.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-big-endian-varargs.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-big-endian-vector-callee.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-big-endian-vector-caller.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-big-imm-offsets.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-big-stack.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-bitfield-extract.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-blockaddress.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-build-vector.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-call-tailcalls.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-cast-opt.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-ccmp-heuristics.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-ccmp.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-clrsb.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-coalesce-ext.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-code-model-large-abs.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-collect-loh-garbage-crash.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-collect-loh-str.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-collect-loh.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-complex-copy-noneon.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-complex-ret.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-const-addr.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-convert-v2f64-v2i32.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-convert-v2i32-v2f64.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-copy-tuple.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-crc32.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-crypto.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-cse.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-csel.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-cvt.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-dagcombiner-convergence.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-dagcombiner-dead-indexed-load.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-dagcombiner-indexed-load.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-dagcombiner-load-slicing.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-dead-def-frame-index.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-dead-register-def-bug.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-dup.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-early-ifcvt.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-elf-calls.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-elf-constpool.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-elf-globals.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-ext.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-extend-int-to-fp.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-extend.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-extern-weak.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-extload-knownzero.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-extract.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-extract_subvector.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-fast-isel-addr-offset.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-fast-isel-alloca.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-fast-isel-br.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-fast-isel-call.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-fast-isel-conversion.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-fast-isel-fcmp.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-fast-isel-gv.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-fast-isel-icmp.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-fast-isel-indirectbr.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-fast-isel-materialize.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-fast-isel-noconvert.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-fast-isel-rem.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-fast-isel-ret.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-fast-isel-select.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-fast-isel.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-fastcc-tailcall.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-fastisel-gep-promote-before-add.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-fcmp-opt.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-fcopysign.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-fixed-point-scalar-cvt-dagcombine.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-fmadd.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-fmax.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-fminv.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-fmuladd.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-fold-address.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-fold-lsl.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-fp-contract-zero.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-fp-imm.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-fp.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-fp128-folding.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-fp128.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-frame-index.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-frameaddr.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-global-address.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-hello.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-i16-subreg-extract.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-icmp-opt.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-illegal-float-ops.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-indexed-memory.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-indexed-vector-ldst-2.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-inline-asm-error-I.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-inline-asm-error-J.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-inline-asm-error-K.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-inline-asm-error-L.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-inline-asm-error-M.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-inline-asm-error-N.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-inline-asm-zero-reg-error.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-inline-asm.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-join-reserved.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-jumptable.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-large-frame.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-ld1.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-ldp.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-ldur.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-ldxr-stxr.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-leaf.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-long-shift.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-memcpy-inline.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-memset-inline.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-memset-to-bzero.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-misched-basic-A53.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-movi.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-mul.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-named-reg-alloc.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-named-reg-notareg.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-neg.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-neon-2velem-high.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-neon-2velem.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-neon-3vdiff.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-neon-aba-abd.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-neon-across.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-neon-add-pairwise.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-neon-add-sub.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-neon-compare-instructions.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-neon-copy.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-neon-copyPhysReg-tuple.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-neon-mul-div.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-neon-scalar-by-elem-mul.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-neon-select_cc.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-neon-simd-ldst-one.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-neon-simd-shift.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-neon-simd-vget.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-neon-v1i1-setcc.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-neon-vector-list-spill.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-patchpoint.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-pic-local-symbol.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-platform-reg.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-popcnt.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-prefetch.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-promote-const.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-redzone.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-reg-copy-noneon.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-register-offset-addressing.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-register-pairing.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-regress-f128csel-flags.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-regress-interphase-shift.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-return-vector.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-returnaddr.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-rev.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-rounding.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-scaled_iv.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-scvt.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-shifted-sext.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-simd-scalar-to-vector.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-simplest-elf.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-sincos.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-sitofp-combine-chains.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-sli-sri-opt.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-smaxv.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-sminv.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-spill-lr.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-spill.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-st1.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-stack-no-frame.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-stackmap.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-stackpointer.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-stacksave.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-stp.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-strict-align.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-stur.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-subsections.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-subvector-extend.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-swizzle-tbl-i16-layout.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-tbl.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-this-return.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-tls-darwin.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-tls-dynamic-together.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-tls-dynamics.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-tls-execs.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-trap.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-trn.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-trunc-store.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-umaxv.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-uminv.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-umov.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-unaligned_ldst.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-uzp.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vaargs.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vabs.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vadd.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vaddlv.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vaddv.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-variadic-aapcs.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vbitwise.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vclz.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vcmp.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vcnt.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vcombine.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vcvt.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vcvt_f.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vcvt_f32_su32.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vcvt_n.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vcvt_su32_f32.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vcvtxd_f32_f64.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vecCmpBr.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vecFold.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vector-ext.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vector-imm.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vector-insertion.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vector-ldst.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vext.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vext_reverse.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vfloatintrinsics.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vhadd.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vhsub.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-virtual_base.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vmax.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vminmaxnm.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vmovn.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vmul.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-volatile.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vpopcnt.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vqadd.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vqsub.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vselect.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vsetcc_fp.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vshift.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vshr.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vshuffle.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vsqrt.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vsra.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-vsub.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-weak-reference.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-xaluo.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-zero-cycle-regmov.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-zext.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-zextload-unscaled.ll [new file with mode: 0644]
test/CodeGen/AArch64/arm64-zip.ll [new file with mode: 0644]
test/CodeGen/AArch64/atomic-ops-not-barriers.ll
test/CodeGen/AArch64/atomic-ops.ll
test/CodeGen/AArch64/basic-pic.ll
test/CodeGen/AArch64/bitfield-insert-0.ll
test/CodeGen/AArch64/bitfield-insert.ll
test/CodeGen/AArch64/bitfield.ll
test/CodeGen/AArch64/blockaddress.ll
test/CodeGen/AArch64/bool-loads.ll
test/CodeGen/AArch64/breg.ll
test/CodeGen/AArch64/callee-save.ll
test/CodeGen/AArch64/code-model-large-abs.ll
test/CodeGen/AArch64/compare-branch.ll
test/CodeGen/AArch64/complex-copy-noneon.ll
test/CodeGen/AArch64/cond-sel.ll
test/CodeGen/AArch64/directcond.ll
test/CodeGen/AArch64/dp1.ll
test/CodeGen/AArch64/eliminate-trunc.ll
test/CodeGen/AArch64/extern-weak.ll
test/CodeGen/AArch64/fastcc-reserved.ll
test/CodeGen/AArch64/fastcc.ll
test/CodeGen/AArch64/fcmp.ll
test/CodeGen/AArch64/fcvt-fixed.ll
test/CodeGen/AArch64/flags-multiuse.ll
test/CodeGen/AArch64/floatdp_2source.ll
test/CodeGen/AArch64/fp-cond-sel.ll
test/CodeGen/AArch64/fp-dp3.ll
test/CodeGen/AArch64/fp128-folding.ll
test/CodeGen/AArch64/fpimm.ll
test/CodeGen/AArch64/func-argpassing.ll
test/CodeGen/AArch64/func-calls.ll
test/CodeGen/AArch64/global-alignment.ll
test/CodeGen/AArch64/got-abuse.ll
test/CodeGen/AArch64/illegal-float-ops.ll
test/CodeGen/AArch64/init-array.ll
test/CodeGen/AArch64/inline-asm-constraints-badI.ll
test/CodeGen/AArch64/inline-asm-constraints-badK2.ll
test/CodeGen/AArch64/jump-table.ll
test/CodeGen/AArch64/large-consts.ll
test/CodeGen/AArch64/ldst-regoffset.ll
test/CodeGen/AArch64/ldst-unscaledimm.ll
test/CodeGen/AArch64/ldst-unsignedimm.ll
test/CodeGen/AArch64/lit.local.cfg [new file with mode: 0644]
test/CodeGen/AArch64/literal_pools_float.ll
test/CodeGen/AArch64/local_vars.ll
test/CodeGen/AArch64/logical_shifted_reg.ll
test/CodeGen/AArch64/mature-mc-support.ll
test/CodeGen/AArch64/movw-consts.ll
test/CodeGen/AArch64/movw-shift-encoding.ll
test/CodeGen/AArch64/neon-bitcast.ll
test/CodeGen/AArch64/neon-bitwise-instructions.ll
test/CodeGen/AArch64/neon-compare-instructions.ll
test/CodeGen/AArch64/neon-diagnostics.ll
test/CodeGen/AArch64/neon-extract.ll
test/CodeGen/AArch64/neon-fma.ll
test/CodeGen/AArch64/neon-fpround_f128.ll
test/CodeGen/AArch64/neon-idiv.ll
test/CodeGen/AArch64/neon-mla-mls.ll
test/CodeGen/AArch64/neon-mov.ll
test/CodeGen/AArch64/neon-or-combine.ll
test/CodeGen/AArch64/neon-perm.ll
test/CodeGen/AArch64/neon-scalar-by-elem-fma.ll
test/CodeGen/AArch64/neon-scalar-copy.ll
test/CodeGen/AArch64/neon-shift-left-long.ll
test/CodeGen/AArch64/neon-truncStore-extLoad.ll
test/CodeGen/AArch64/pic-eh-stubs.ll
test/CodeGen/AArch64/regress-f128csel-flags.ll
test/CodeGen/AArch64/regress-fp128-livein.ll
test/CodeGen/AArch64/regress-tblgen-chains.ll
test/CodeGen/AArch64/regress-w29-reserved-with-fp.ll
test/CodeGen/AArch64/setcc-takes-i32.ll
test/CodeGen/AArch64/sibling-call.ll
test/CodeGen/AArch64/sincos-expansion.ll
test/CodeGen/AArch64/sincospow-vector-expansion.ll
test/CodeGen/AArch64/tail-call.ll
test/CodeGen/AArch64/zero-reg.ll
test/CodeGen/ARM64/2011-03-09-CPSRSpill.ll [deleted file]
test/CodeGen/ARM64/2011-03-17-AsmPrinterCrash.ll [deleted file]
test/CodeGen/ARM64/2011-03-21-Unaligned-Frame-Index.ll [deleted file]
test/CodeGen/ARM64/2011-04-21-CPSRBug.ll [deleted file]
test/CodeGen/ARM64/2011-10-18-LdStOptBug.ll [deleted file]
test/CodeGen/ARM64/2012-01-11-ComparisonDAGCrash.ll [deleted file]
test/CodeGen/ARM64/2012-05-07-DAGCombineVectorExtract.ll [deleted file]
test/CodeGen/ARM64/2012-05-07-MemcpyAlignBug.ll [deleted file]
test/CodeGen/ARM64/2012-05-09-LOADgot-bug.ll [deleted file]
test/CodeGen/ARM64/2012-05-22-LdStOptBug.ll [deleted file]
test/CodeGen/ARM64/2012-06-06-FPToUI.ll [deleted file]
test/CodeGen/ARM64/2012-07-11-InstrEmitterBug.ll [deleted file]
test/CodeGen/ARM64/2013-01-13-ffast-fcmp.ll [deleted file]
test/CodeGen/ARM64/2013-01-23-frem-crash.ll [deleted file]
test/CodeGen/ARM64/2013-01-23-sext-crash.ll [deleted file]
test/CodeGen/ARM64/2013-02-12-shufv8i8.ll [deleted file]
test/CodeGen/ARM64/2014-04-16-AnInfiniteLoopInDAGCombine.ll [deleted file]
test/CodeGen/ARM64/2014-04-28-sqshl-uqshl-i64Contant.ll [deleted file]
test/CodeGen/ARM64/2014-04-29-EXT-undef-mask.ll [deleted file]
test/CodeGen/ARM64/AdvSIMD-Scalar.ll [deleted file]
test/CodeGen/ARM64/aapcs.ll [deleted file]
test/CodeGen/ARM64/aarch64-large-frame.ll [deleted file]
test/CodeGen/ARM64/aarch64-neon-2velem-high.ll [deleted file]
test/CodeGen/ARM64/aarch64-neon-2velem.ll [deleted file]
test/CodeGen/ARM64/aarch64-neon-3vdiff.ll [deleted file]
test/CodeGen/ARM64/aarch64-neon-aba-abd.ll [deleted file]
test/CodeGen/ARM64/aarch64-neon-across.ll [deleted file]
test/CodeGen/ARM64/aarch64-neon-add-pairwise.ll [deleted file]
test/CodeGen/ARM64/aarch64-neon-add-sub.ll [deleted file]
test/CodeGen/ARM64/aarch64-neon-copy.ll [deleted file]
test/CodeGen/ARM64/aarch64-neon-copyPhysReg-tuple.ll [deleted file]
test/CodeGen/ARM64/aarch64-neon-mul-div.ll [deleted file]
test/CodeGen/ARM64/aarch64-neon-scalar-by-elem-mul.ll [deleted file]
test/CodeGen/ARM64/aarch64-neon-select_cc.ll [deleted file]
test/CodeGen/ARM64/aarch64-neon-simd-ldst-one.ll [deleted file]
test/CodeGen/ARM64/aarch64-neon-simd-shift.ll [deleted file]
test/CodeGen/ARM64/aarch64-neon-simd-vget.ll [deleted file]
test/CodeGen/ARM64/aarch64-neon-v1i1-setcc.ll [deleted file]
test/CodeGen/ARM64/aarch64-neon-vector-list-spill.ll [deleted file]
test/CodeGen/ARM64/abi-varargs.ll [deleted file]
test/CodeGen/ARM64/abi.ll [deleted file]
test/CodeGen/ARM64/abi_align.ll [deleted file]
test/CodeGen/ARM64/addp.ll [deleted file]
test/CodeGen/ARM64/addr-mode-folding.ll [deleted file]
test/CodeGen/ARM64/addr-type-promotion.ll [deleted file]
test/CodeGen/ARM64/addrmode.ll [deleted file]
test/CodeGen/ARM64/alloc-no-stack-realign.ll [deleted file]
test/CodeGen/ARM64/alloca-frame-pointer-offset.ll [deleted file]
test/CodeGen/ARM64/andCmpBrToTBZ.ll [deleted file]
test/CodeGen/ARM64/ands-bad-peephole.ll [deleted file]
test/CodeGen/ARM64/anyregcc-crash.ll [deleted file]
test/CodeGen/ARM64/anyregcc.ll [deleted file]
test/CodeGen/ARM64/arith-saturating.ll [deleted file]
test/CodeGen/ARM64/arith.ll [deleted file]
test/CodeGen/ARM64/arm64-dead-def-elimination-flag.ll [deleted file]
test/CodeGen/ARM64/atomic-128.ll [deleted file]
test/CodeGen/ARM64/atomic.ll [deleted file]
test/CodeGen/ARM64/basic-pic.ll [deleted file]
test/CodeGen/ARM64/big-endian-bitconverts.ll [deleted file]
test/CodeGen/ARM64/big-endian-eh.ll [deleted file]
test/CodeGen/ARM64/big-endian-varargs.ll [deleted file]
test/CodeGen/ARM64/big-endian-vector-callee.ll [deleted file]
test/CodeGen/ARM64/big-endian-vector-caller.ll [deleted file]
test/CodeGen/ARM64/big-imm-offsets.ll [deleted file]
test/CodeGen/ARM64/big-stack.ll [deleted file]
test/CodeGen/ARM64/bitfield-extract.ll [deleted file]
test/CodeGen/ARM64/blockaddress.ll [deleted file]
test/CodeGen/ARM64/build-vector.ll [deleted file]
test/CodeGen/ARM64/call-tailcalls.ll [deleted file]
test/CodeGen/ARM64/cast-opt.ll [deleted file]
test/CodeGen/ARM64/ccmp-heuristics.ll [deleted file]
test/CodeGen/ARM64/ccmp.ll [deleted file]
test/CodeGen/ARM64/clrsb.ll [deleted file]
test/CodeGen/ARM64/coalesce-ext.ll [deleted file]
test/CodeGen/ARM64/code-model-large-abs.ll [deleted file]
test/CodeGen/ARM64/collect-loh-garbage-crash.ll [deleted file]
test/CodeGen/ARM64/collect-loh-str.ll [deleted file]
test/CodeGen/ARM64/collect-loh.ll [deleted file]
test/CodeGen/ARM64/compact-unwind-unhandled-cfi.S [deleted file]
test/CodeGen/ARM64/complex-copy-noneon.ll [deleted file]
test/CodeGen/ARM64/complex-ret.ll [deleted file]
test/CodeGen/ARM64/const-addr.ll [deleted file]
test/CodeGen/ARM64/convert-v2f64-v2i32.ll [deleted file]
test/CodeGen/ARM64/convert-v2i32-v2f64.ll [deleted file]
test/CodeGen/ARM64/copy-tuple.ll [deleted file]
test/CodeGen/ARM64/crc32.ll [deleted file]
test/CodeGen/ARM64/crypto.ll [deleted file]
test/CodeGen/ARM64/cse.ll [deleted file]
test/CodeGen/ARM64/csel.ll [deleted file]
test/CodeGen/ARM64/cvt.ll [deleted file]
test/CodeGen/ARM64/dagcombiner-convergence.ll [deleted file]
test/CodeGen/ARM64/dagcombiner-dead-indexed-load.ll [deleted file]
test/CodeGen/ARM64/dagcombiner-indexed-load.ll [deleted file]
test/CodeGen/ARM64/dagcombiner-load-slicing.ll [deleted file]
test/CodeGen/ARM64/dead-def-frame-index.ll [deleted file]
test/CodeGen/ARM64/dead-register-def-bug.ll [deleted file]
test/CodeGen/ARM64/dup.ll [deleted file]
test/CodeGen/ARM64/early-ifcvt.ll [deleted file]
test/CodeGen/ARM64/elf-calls.ll [deleted file]
test/CodeGen/ARM64/elf-constpool.ll [deleted file]
test/CodeGen/ARM64/elf-globals.ll [deleted file]
test/CodeGen/ARM64/ext.ll [deleted file]
test/CodeGen/ARM64/extend-int-to-fp.ll [deleted file]
test/CodeGen/ARM64/extend.ll [deleted file]
test/CodeGen/ARM64/extern-weak.ll [deleted file]
test/CodeGen/ARM64/extload-knownzero.ll [deleted file]
test/CodeGen/ARM64/extract.ll [deleted file]
test/CodeGen/ARM64/extract_subvector.ll [deleted file]
test/CodeGen/ARM64/fast-isel-addr-offset.ll [deleted file]
test/CodeGen/ARM64/fast-isel-alloca.ll [deleted file]
test/CodeGen/ARM64/fast-isel-br.ll [deleted file]
test/CodeGen/ARM64/fast-isel-call.ll [deleted file]
test/CodeGen/ARM64/fast-isel-conversion.ll [deleted file]
test/CodeGen/ARM64/fast-isel-fcmp.ll [deleted file]
test/CodeGen/ARM64/fast-isel-gv.ll [deleted file]
test/CodeGen/ARM64/fast-isel-icmp.ll [deleted file]
test/CodeGen/ARM64/fast-isel-indirectbr.ll [deleted file]
test/CodeGen/ARM64/fast-isel-intrinsic.ll [deleted file]
test/CodeGen/ARM64/fast-isel-materialize.ll [deleted file]
test/CodeGen/ARM64/fast-isel-noconvert.ll [deleted file]
test/CodeGen/ARM64/fast-isel-rem.ll [deleted file]
test/CodeGen/ARM64/fast-isel-ret.ll [deleted file]
test/CodeGen/ARM64/fast-isel-select.ll [deleted file]
test/CodeGen/ARM64/fast-isel.ll [deleted file]
test/CodeGen/ARM64/fastcc-tailcall.ll [deleted file]
test/CodeGen/ARM64/fastisel-gep-promote-before-add.ll [deleted file]
test/CodeGen/ARM64/fcmp-opt.ll [deleted file]
test/CodeGen/ARM64/fcopysign.ll [deleted file]
test/CodeGen/ARM64/fixed-point-scalar-cvt-dagcombine.ll [deleted file]
test/CodeGen/ARM64/fmadd.ll [deleted file]
test/CodeGen/ARM64/fmax.ll [deleted file]
test/CodeGen/ARM64/fminv.ll [deleted file]
test/CodeGen/ARM64/fmuladd.ll [deleted file]
test/CodeGen/ARM64/fold-address.ll [deleted file]
test/CodeGen/ARM64/fold-lsl.ll [deleted file]
test/CodeGen/ARM64/fp-contract-zero.ll [deleted file]
test/CodeGen/ARM64/fp-imm.ll [deleted file]
test/CodeGen/ARM64/fp.ll [deleted file]
test/CodeGen/ARM64/fp128-folding.ll [deleted file]
test/CodeGen/ARM64/fp128.ll [deleted file]
test/CodeGen/ARM64/frame-index.ll [deleted file]
test/CodeGen/ARM64/frameaddr.ll [deleted file]
test/CodeGen/ARM64/global-address.ll [deleted file]
test/CodeGen/ARM64/hello.ll [deleted file]
test/CodeGen/ARM64/i16-subreg-extract.ll [deleted file]
test/CodeGen/ARM64/icmp-opt.ll [deleted file]
test/CodeGen/ARM64/illegal-float-ops.ll [deleted file]
test/CodeGen/ARM64/indexed-memory.ll [deleted file]
test/CodeGen/ARM64/indexed-vector-ldst-2.ll [deleted file]
test/CodeGen/ARM64/indexed-vector-ldst.ll [deleted file]
test/CodeGen/ARM64/inline-asm-error-I.ll [deleted file]
test/CodeGen/ARM64/inline-asm-error-J.ll [deleted file]
test/CodeGen/ARM64/inline-asm-error-K.ll [deleted file]
test/CodeGen/ARM64/inline-asm-error-L.ll [deleted file]
test/CodeGen/ARM64/inline-asm-error-M.ll [deleted file]
test/CodeGen/ARM64/inline-asm-error-N.ll [deleted file]
test/CodeGen/ARM64/inline-asm-zero-reg-error.ll [deleted file]
test/CodeGen/ARM64/inline-asm.ll [deleted file]
test/CodeGen/ARM64/join-reserved.ll [deleted file]
test/CodeGen/ARM64/jumptable.ll [deleted file]
test/CodeGen/ARM64/ld1.ll [deleted file]
test/CodeGen/ARM64/ldp.ll [deleted file]
test/CodeGen/ARM64/ldur.ll [deleted file]
test/CodeGen/ARM64/ldxr-stxr.ll [deleted file]
test/CodeGen/ARM64/leaf.ll [deleted file]
test/CodeGen/ARM64/lit.local.cfg [deleted file]
test/CodeGen/ARM64/long-shift.ll [deleted file]
test/CodeGen/ARM64/memcpy-inline.ll [deleted file]
test/CodeGen/ARM64/memset-inline.ll [deleted file]
test/CodeGen/ARM64/memset-to-bzero.ll [deleted file]
test/CodeGen/ARM64/misched-basic-A53.ll [deleted file]
test/CodeGen/ARM64/misched-forwarding-A53.ll [deleted file]
test/CodeGen/ARM64/movi.ll [deleted file]
test/CodeGen/ARM64/mul.ll [deleted file]
test/CodeGen/ARM64/named-reg-alloc.ll [deleted file]
test/CodeGen/ARM64/named-reg-notareg.ll [deleted file]
test/CodeGen/ARM64/neg.ll [deleted file]
test/CodeGen/ARM64/neon-compare-instructions.ll [deleted file]
test/CodeGen/ARM64/neon-v1i1-setcc.ll [deleted file]
test/CodeGen/ARM64/patchpoint.ll [deleted file]
test/CodeGen/ARM64/pic-local-symbol.ll [deleted file]
test/CodeGen/ARM64/platform-reg.ll [deleted file]
test/CodeGen/ARM64/popcnt.ll [deleted file]
test/CodeGen/ARM64/prefetch.ll [deleted file]
test/CodeGen/ARM64/promote-const.ll [deleted file]
test/CodeGen/ARM64/redzone.ll [deleted file]
test/CodeGen/ARM64/reg-copy-noneon.ll [deleted file]
test/CodeGen/ARM64/register-offset-addressing.ll [deleted file]
test/CodeGen/ARM64/register-pairing.ll [deleted file]
test/CodeGen/ARM64/regress-f128csel-flags.ll [deleted file]
test/CodeGen/ARM64/regress-interphase-shift.ll [deleted file]
test/CodeGen/ARM64/return-vector.ll [deleted file]
test/CodeGen/ARM64/returnaddr.ll [deleted file]
test/CodeGen/ARM64/rev.ll [deleted file]
test/CodeGen/ARM64/rounding.ll [deleted file]
test/CodeGen/ARM64/scaled_iv.ll [deleted file]
test/CodeGen/ARM64/scvt.ll [deleted file]
test/CodeGen/ARM64/shifted-sext.ll [deleted file]
test/CodeGen/ARM64/simd-scalar-to-vector.ll [deleted file]
test/CodeGen/ARM64/simplest-elf.ll [deleted file]
test/CodeGen/ARM64/sincos.ll [deleted file]
test/CodeGen/ARM64/sitofp-combine-chains.ll [deleted file]
test/CodeGen/ARM64/sli-sri-opt.ll [deleted file]
test/CodeGen/ARM64/smaxv.ll [deleted file]
test/CodeGen/ARM64/sminv.ll [deleted file]
test/CodeGen/ARM64/spill-lr.ll [deleted file]
test/CodeGen/ARM64/spill.ll [deleted file]
test/CodeGen/ARM64/st1.ll [deleted file]
test/CodeGen/ARM64/stack-no-frame.ll [deleted file]
test/CodeGen/ARM64/stackmap.ll [deleted file]
test/CodeGen/ARM64/stackpointer.ll [deleted file]
test/CodeGen/ARM64/stacksave.ll [deleted file]
test/CodeGen/ARM64/stp.ll [deleted file]
test/CodeGen/ARM64/strict-align.ll [deleted file]
test/CodeGen/ARM64/stur.ll [deleted file]
test/CodeGen/ARM64/subsections.ll [deleted file]
test/CodeGen/ARM64/subvector-extend.ll [deleted file]
test/CodeGen/ARM64/swizzle-tbl-i16-layout.ll [deleted file]
test/CodeGen/ARM64/tbl.ll [deleted file]
test/CodeGen/ARM64/this-return.ll [deleted file]
test/CodeGen/ARM64/tls-darwin.ll [deleted file]
test/CodeGen/ARM64/tls-dynamic-together.ll [deleted file]
test/CodeGen/ARM64/tls-dynamics.ll [deleted file]
test/CodeGen/ARM64/tls-execs.ll [deleted file]
test/CodeGen/ARM64/trap.ll [deleted file]
test/CodeGen/ARM64/trn.ll [deleted file]
test/CodeGen/ARM64/trunc-store.ll [deleted file]
test/CodeGen/ARM64/umaxv.ll [deleted file]
test/CodeGen/ARM64/uminv.ll [deleted file]
test/CodeGen/ARM64/umov.ll [deleted file]
test/CodeGen/ARM64/unaligned_ldst.ll [deleted file]
test/CodeGen/ARM64/uzp.ll [deleted file]
test/CodeGen/ARM64/vaargs.ll [deleted file]
test/CodeGen/ARM64/vabs.ll [deleted file]
test/CodeGen/ARM64/vadd.ll [deleted file]
test/CodeGen/ARM64/vaddlv.ll [deleted file]
test/CodeGen/ARM64/vaddv.ll [deleted file]
test/CodeGen/ARM64/variadic-aapcs.ll [deleted file]
test/CodeGen/ARM64/vbitwise.ll [deleted file]
test/CodeGen/ARM64/vclz.ll [deleted file]
test/CodeGen/ARM64/vcmp.ll [deleted file]
test/CodeGen/ARM64/vcnt.ll [deleted file]
test/CodeGen/ARM64/vcombine.ll [deleted file]
test/CodeGen/ARM64/vcvt.ll [deleted file]
test/CodeGen/ARM64/vcvt_f.ll [deleted file]
test/CodeGen/ARM64/vcvt_f32_su32.ll [deleted file]
test/CodeGen/ARM64/vcvt_n.ll [deleted file]
test/CodeGen/ARM64/vcvt_su32_f32.ll [deleted file]
test/CodeGen/ARM64/vcvtxd_f32_f64.ll [deleted file]
test/CodeGen/ARM64/vecCmpBr.ll [deleted file]
test/CodeGen/ARM64/vecFold.ll [deleted file]
test/CodeGen/ARM64/vector-ext.ll [deleted file]
test/CodeGen/ARM64/vector-imm.ll [deleted file]
test/CodeGen/ARM64/vector-insertion.ll [deleted file]
test/CodeGen/ARM64/vector-ldst.ll [deleted file]
test/CodeGen/ARM64/vext.ll [deleted file]
test/CodeGen/ARM64/vext_reverse.ll [deleted file]
test/CodeGen/ARM64/vfloatintrinsics.ll [deleted file]
test/CodeGen/ARM64/vhadd.ll [deleted file]
test/CodeGen/ARM64/vhsub.ll [deleted file]
test/CodeGen/ARM64/virtual_base.ll [deleted file]
test/CodeGen/ARM64/vmax.ll [deleted file]
test/CodeGen/ARM64/vminmaxnm.ll [deleted file]
test/CodeGen/ARM64/vmovn.ll [deleted file]
test/CodeGen/ARM64/vmul.ll [deleted file]
test/CodeGen/ARM64/volatile.ll [deleted file]
test/CodeGen/ARM64/vpopcnt.ll [deleted file]
test/CodeGen/ARM64/vqadd.ll [deleted file]
test/CodeGen/ARM64/vqsub.ll [deleted file]
test/CodeGen/ARM64/vselect.ll [deleted file]
test/CodeGen/ARM64/vsetcc_fp.ll [deleted file]
test/CodeGen/ARM64/vshift.ll [deleted file]
test/CodeGen/ARM64/vshr.ll [deleted file]
test/CodeGen/ARM64/vshuffle.ll [deleted file]
test/CodeGen/ARM64/vsqrt.ll [deleted file]
test/CodeGen/ARM64/vsra.ll [deleted file]
test/CodeGen/ARM64/vsub.ll [deleted file]
test/CodeGen/ARM64/weak-reference.ll [deleted file]
test/CodeGen/ARM64/xaluo.ll [deleted file]
test/CodeGen/ARM64/zero-cycle-regmov.ll [deleted file]
test/CodeGen/ARM64/zero-cycle-zeroing.ll [deleted file]
test/CodeGen/ARM64/zext.ll [deleted file]
test/CodeGen/ARM64/zextload-unscaled.ll [deleted file]
test/CodeGen/ARM64/zip.ll [deleted file]
test/DebugInfo/AArch64/struct_by_value.ll [new file with mode: 0644]
test/DebugInfo/ARM64/lit.local.cfg [deleted file]
test/DebugInfo/ARM64/struct_by_value.ll [deleted file]
test/MC/AArch64/adrp-relocation.s
test/MC/AArch64/arm64-adr.s [new file with mode: 0644]
test/MC/AArch64/arm64-advsimd.s [new file with mode: 0644]
test/MC/AArch64/arm64-aliases.s [new file with mode: 0644]
test/MC/AArch64/arm64-arithmetic-encoding.s [new file with mode: 0644]
test/MC/AArch64/arm64-arm64-fixup.s [new file with mode: 0644]
test/MC/AArch64/arm64-basic-a64-instructions.s [new file with mode: 0644]
test/MC/AArch64/arm64-be-datalayout.s [new file with mode: 0644]
test/MC/AArch64/arm64-bitfield-encoding.s [new file with mode: 0644]
test/MC/AArch64/arm64-branch-encoding.s [new file with mode: 0644]
test/MC/AArch64/arm64-condbr-without-dots.s [new file with mode: 0644]
test/MC/AArch64/arm64-crypto.s [new file with mode: 0644]
test/MC/AArch64/arm64-diagno-predicate.s [new file with mode: 0644]
test/MC/AArch64/arm64-diags.s [new file with mode: 0644]
test/MC/AArch64/arm64-directive_loh.s [new file with mode: 0644]
test/MC/AArch64/arm64-elf-reloc-condbr.s [new file with mode: 0644]
test/MC/AArch64/arm64-elf-relocs.s [new file with mode: 0644]
test/MC/AArch64/arm64-fp-encoding.s [new file with mode: 0644]
test/MC/AArch64/arm64-large-relocs.s [new file with mode: 0644]
test/MC/AArch64/arm64-leaf-compact-unwind.s [new file with mode: 0644]
test/MC/AArch64/arm64-logical-encoding.s [new file with mode: 0644]
test/MC/AArch64/arm64-mapping-across-sections.s [new file with mode: 0644]
test/MC/AArch64/arm64-mapping-within-section.s [new file with mode: 0644]
test/MC/AArch64/arm64-memory.s [new file with mode: 0644]
test/MC/AArch64/arm64-nv-cond.s [new file with mode: 0644]
test/MC/AArch64/arm64-optional-hash.s [new file with mode: 0644]
test/MC/AArch64/arm64-separator.s [new file with mode: 0644]
test/MC/AArch64/arm64-simd-ldst.s [new file with mode: 0644]
test/MC/AArch64/arm64-small-data-fixups.s [new file with mode: 0644]
test/MC/AArch64/arm64-spsel-sysreg.s [new file with mode: 0644]
test/MC/AArch64/arm64-system-encoding.s [new file with mode: 0644]
test/MC/AArch64/arm64-target-specific-sysreg.s [new file with mode: 0644]
test/MC/AArch64/arm64-tls-modifiers-darwin.s [new file with mode: 0644]
test/MC/AArch64/arm64-tls-relocs.s [new file with mode: 0644]
test/MC/AArch64/arm64-v128_lo-diagnostics.s [new file with mode: 0644]
test/MC/AArch64/arm64-variable-exprs.s [new file with mode: 0644]
test/MC/AArch64/arm64-vector-lists.s [new file with mode: 0644]
test/MC/AArch64/arm64-verbose-vector-case.s [new file with mode: 0644]
test/MC/AArch64/basic-a64-diagnostics.s
test/MC/AArch64/basic-a64-instructions.s
test/MC/AArch64/basic-pic.s
test/MC/AArch64/elf-extern.s
test/MC/AArch64/elf-objdump.s
test/MC/AArch64/elf-reloc-addsubimm.s
test/MC/AArch64/elf-reloc-ldrlit.s
test/MC/AArch64/elf-reloc-ldstunsimm.s
test/MC/AArch64/elf-reloc-movw.s
test/MC/AArch64/elf-reloc-pcreladdressing.s
test/MC/AArch64/elf-reloc-tstb.s
test/MC/AArch64/elf-reloc-uncondbrimm.s
test/MC/AArch64/gicv3-regs-diagnostics.s
test/MC/AArch64/gicv3-regs.s
test/MC/AArch64/inline-asm-modifiers.s
test/MC/AArch64/jump-table.s
test/MC/AArch64/lit.local.cfg
test/MC/AArch64/mapping-across-sections.s
test/MC/AArch64/mapping-within-section.s
test/MC/AArch64/neon-3vdiff.s
test/MC/AArch64/neon-aba-abd.s
test/MC/AArch64/neon-add-pairwise.s
test/MC/AArch64/neon-add-sub-instructions.s
test/MC/AArch64/neon-bitwise-instructions.s
test/MC/AArch64/neon-compare-instructions.s
test/MC/AArch64/neon-diagnostics.s
test/MC/AArch64/neon-facge-facgt.s
test/MC/AArch64/neon-frsqrt-frecp.s
test/MC/AArch64/neon-halving-add-sub.s
test/MC/AArch64/neon-max-min-pairwise.s
test/MC/AArch64/neon-max-min.s
test/MC/AArch64/neon-mla-mls-instructions.s
test/MC/AArch64/neon-mov.s
test/MC/AArch64/neon-mul-div-instructions.s
test/MC/AArch64/neon-rounding-halving-add.s
test/MC/AArch64/neon-rounding-shift.s
test/MC/AArch64/neon-saturating-add-sub.s
test/MC/AArch64/neon-saturating-rounding-shift.s
test/MC/AArch64/neon-saturating-shift.s
test/MC/AArch64/neon-scalar-abs.s
test/MC/AArch64/neon-scalar-add-sub.s
test/MC/AArch64/neon-scalar-by-elem-mla.s
test/MC/AArch64/neon-scalar-by-elem-mul.s
test/MC/AArch64/neon-scalar-by-elem-saturating-mla.s
test/MC/AArch64/neon-scalar-by-elem-saturating-mul.s
test/MC/AArch64/neon-scalar-compare.s
test/MC/AArch64/neon-scalar-cvt.s
test/MC/AArch64/neon-scalar-dup.s
test/MC/AArch64/neon-scalar-extract-narrow.s
test/MC/AArch64/neon-scalar-fp-compare.s
test/MC/AArch64/neon-scalar-mul.s
test/MC/AArch64/neon-scalar-neg.s
test/MC/AArch64/neon-scalar-recip.s
test/MC/AArch64/neon-scalar-reduce-pairwise.s
test/MC/AArch64/neon-scalar-rounding-shift.s
test/MC/AArch64/neon-scalar-saturating-add-sub.s
test/MC/AArch64/neon-scalar-saturating-rounding-shift.s
test/MC/AArch64/neon-scalar-saturating-shift.s
test/MC/AArch64/neon-scalar-shift-imm.s
test/MC/AArch64/neon-scalar-shift.s
test/MC/AArch64/neon-shift-left-long.s
test/MC/AArch64/neon-shift.s
test/MC/AArch64/neon-simd-copy.s
test/MC/AArch64/neon-simd-shift.s
test/MC/AArch64/neon-sxtl.s
test/MC/AArch64/neon-uxtl.s
test/MC/AArch64/noneon-diagnostics.s
test/MC/AArch64/optional-hash.s
test/MC/AArch64/tls-relocs.s
test/MC/AArch64/trace-regs-diagnostics.s
test/MC/AArch64/trace-regs.s
test/MC/ARM64/adr.s [deleted file]
test/MC/ARM64/advsimd.s [deleted file]
test/MC/ARM64/aliases.s [deleted file]
test/MC/ARM64/arithmetic-encoding.s [deleted file]
test/MC/ARM64/arm64-fixup.s [deleted file]
test/MC/ARM64/basic-a64-instructions.s [deleted file]
test/MC/ARM64/be-datalayout.s [deleted file]
test/MC/ARM64/bitfield-encoding.s [deleted file]
test/MC/ARM64/branch-encoding.s [deleted file]
test/MC/ARM64/condbr-without-dots.s [deleted file]
test/MC/ARM64/crypto.s [deleted file]
test/MC/ARM64/diagno-predicate.s [deleted file]
test/MC/ARM64/diags.s [deleted file]
test/MC/ARM64/directive_loh.s [deleted file]
test/MC/ARM64/elf-reloc-condbr.s [deleted file]
test/MC/ARM64/elf-relocs.s [deleted file]
test/MC/ARM64/fp-encoding.s [deleted file]
test/MC/ARM64/large-relocs.s [deleted file]
test/MC/ARM64/leaf-compact-unwind.s [deleted file]
test/MC/ARM64/lit.local.cfg [deleted file]
test/MC/ARM64/logical-encoding.s [deleted file]
test/MC/ARM64/mapping-across-sections.s [deleted file]
test/MC/ARM64/mapping-within-section.s [deleted file]
test/MC/ARM64/memory.s [deleted file]
test/MC/ARM64/nv-cond.s [deleted file]
test/MC/ARM64/optional-hash.s [deleted file]
test/MC/ARM64/separator.s [deleted file]
test/MC/ARM64/simd-ldst.s [deleted file]
test/MC/ARM64/small-data-fixups.s [deleted file]
test/MC/ARM64/spsel-sysreg.s [deleted file]
test/MC/ARM64/system-encoding.s [deleted file]
test/MC/ARM64/target-specific-sysreg.s [deleted file]
test/MC/ARM64/tls-modifiers-darwin.s [deleted file]
test/MC/ARM64/tls-relocs.s [deleted file]
test/MC/ARM64/v128_lo-diagnostics.s [deleted file]
test/MC/ARM64/variable-exprs.s [deleted file]
test/MC/ARM64/vector-lists.s [deleted file]
test/MC/ARM64/verbose-vector-case.s [deleted file]
test/MC/Disassembler/AArch64/arm64-advsimd.txt [new file with mode: 0644]
test/MC/Disassembler/AArch64/arm64-arithmetic.txt [new file with mode: 0644]
test/MC/Disassembler/AArch64/arm64-basic-a64-undefined.txt [new file with mode: 0644]
test/MC/Disassembler/AArch64/arm64-bitfield.txt [new file with mode: 0644]
test/MC/Disassembler/AArch64/arm64-branch.txt [new file with mode: 0644]
test/MC/Disassembler/AArch64/arm64-canonical-form.txt [new file with mode: 0644]
test/MC/Disassembler/AArch64/arm64-crc32.txt [new file with mode: 0644]
test/MC/Disassembler/AArch64/arm64-crypto.txt [new file with mode: 0644]
test/MC/Disassembler/AArch64/arm64-invalid-logical.txt [new file with mode: 0644]
test/MC/Disassembler/AArch64/arm64-logical.txt [new file with mode: 0644]
test/MC/Disassembler/AArch64/arm64-memory.txt [new file with mode: 0644]
test/MC/Disassembler/AArch64/arm64-non-apple-fmov.txt [new file with mode: 0644]
test/MC/Disassembler/AArch64/arm64-scalar-fp.txt [new file with mode: 0644]
test/MC/Disassembler/AArch64/arm64-system.txt [new file with mode: 0644]
test/MC/Disassembler/AArch64/lit.local.cfg
test/MC/Disassembler/ARM64/advsimd.txt [deleted file]
test/MC/Disassembler/ARM64/arithmetic.txt [deleted file]
test/MC/Disassembler/ARM64/basic-a64-undefined.txt [deleted file]
test/MC/Disassembler/ARM64/bitfield.txt [deleted file]
test/MC/Disassembler/ARM64/branch.txt [deleted file]
test/MC/Disassembler/ARM64/canonical-form.txt [deleted file]
test/MC/Disassembler/ARM64/crc32.txt [deleted file]
test/MC/Disassembler/ARM64/crypto.txt [deleted file]
test/MC/Disassembler/ARM64/invalid-logical.txt [deleted file]
test/MC/Disassembler/ARM64/lit.local.cfg [deleted file]
test/MC/Disassembler/ARM64/logical.txt [deleted file]
test/MC/Disassembler/ARM64/memory.txt [deleted file]
test/MC/Disassembler/ARM64/non-apple-fmov.txt [deleted file]
test/MC/Disassembler/ARM64/scalar-fp.txt [deleted file]
test/MC/Disassembler/ARM64/system.txt [deleted file]
test/MC/MachO/AArch64/darwin-ARM64-local-label-diff.s [new file with mode: 0644]
test/MC/MachO/AArch64/darwin-ARM64-reloc.s [new file with mode: 0644]
test/MC/MachO/AArch64/lit.local.cfg [new file with mode: 0644]
test/MC/MachO/ARM64/darwin-ARM64-local-label-diff.s [deleted file]
test/MC/MachO/ARM64/darwin-ARM64-reloc.s [deleted file]
test/MC/MachO/ARM64/lit.local.cfg [deleted file]
test/Transforms/ConstantHoisting/AArch64/const-addr.ll [new file with mode: 0644]
test/Transforms/ConstantHoisting/AArch64/large-immediate.ll [new file with mode: 0644]
test/Transforms/ConstantHoisting/AArch64/lit.local.cfg [new file with mode: 0644]
test/Transforms/ConstantHoisting/ARM64/const-addr.ll [deleted file]
test/Transforms/ConstantHoisting/ARM64/large-immediate.ll [deleted file]
test/Transforms/ConstantHoisting/ARM64/lit.local.cfg [deleted file]
test/Transforms/GlobalMerge/AArch64/arm64.ll [new file with mode: 0644]
test/Transforms/GlobalMerge/AArch64/lit.local.cfg [new file with mode: 0644]
test/Transforms/GlobalMerge/ARM64/arm64.ll [deleted file]
test/Transforms/GlobalMerge/ARM64/lit.local.cfg [deleted file]
test/Transforms/InstCombine/2012-04-23-Neon-Intrinsics.ll
test/Transforms/LoopStrengthReduce/AArch64/lit.local.cfg [new file with mode: 0644]
test/Transforms/LoopStrengthReduce/AArch64/lsr-memcpy.ll [new file with mode: 0644]
test/Transforms/LoopStrengthReduce/AArch64/lsr-memset.ll [new file with mode: 0644]
test/Transforms/LoopStrengthReduce/AArch64/req-regs.ll [new file with mode: 0644]
test/Transforms/LoopStrengthReduce/ARM64/lit.local.cfg [deleted file]
test/Transforms/LoopStrengthReduce/ARM64/lsr-memcpy.ll [deleted file]
test/Transforms/LoopStrengthReduce/ARM64/lsr-memset.ll [deleted file]
test/Transforms/LoopStrengthReduce/ARM64/req-regs.ll [deleted file]
test/Transforms/LoopVectorize/AArch64/arm64-unroll.ll [new file with mode: 0644]
test/Transforms/LoopVectorize/AArch64/gather-cost.ll [new file with mode: 0644]
test/Transforms/LoopVectorize/ARM64/arm64-unroll.ll [deleted file]
test/Transforms/LoopVectorize/ARM64/gather-cost.ll [deleted file]
test/Transforms/LoopVectorize/ARM64/lit.local.cfg [deleted file]
test/Transforms/SLPVectorizer/AArch64/lit.local.cfg [new file with mode: 0644]
test/Transforms/SLPVectorizer/AArch64/mismatched-intrinsics.ll [new file with mode: 0644]
test/Transforms/SLPVectorizer/ARM64/lit.local.cfg [deleted file]
test/Transforms/SLPVectorizer/ARM64/mismatched-intrinsics.ll [deleted file]

index b19ab02..0d6eead 100644 (file)
@@ -127,7 +127,7 @@ set(LLVM_INCLUDE_DIR ${CMAKE_CURRENT_BINARY_DIR}/include)
 set(LLVM_LIBDIR_SUFFIX "" CACHE STRING "Define suffix of library directory name (32/64)" )
 
 set(LLVM_ALL_TARGETS
-  ARM64
+  AArch64
   ARM
   CppBackend
   Hexagon
@@ -143,7 +143,7 @@ set(LLVM_ALL_TARGETS
   )
 
 # List of targets with JIT support:
-set(LLVM_TARGETS_WITH_JIT X86 PowerPC ARM64 ARM Mips SystemZ)
+set(LLVM_TARGETS_WITH_JIT X86 PowerPC AArch64 ARM Mips SystemZ)
 
 set(LLVM_TARGETS_TO_BUILD "all"
     CACHE STRING "Semicolon-separated list of targets to build, or \"all\".")
index 344e66a..08f756c 100644 (file)
@@ -419,9 +419,9 @@ AC_CACHE_CHECK([target architecture],[llvm_cv_target_arch],
   amd64-* | x86_64-*)     llvm_cv_target_arch="x86_64" ;;
   sparc*-*)               llvm_cv_target_arch="Sparc" ;;
   powerpc*-*)             llvm_cv_target_arch="PowerPC" ;;
-  arm64*-*)               llvm_cv_target_arch="ARM64" ;;
+  arm64*-*)               llvm_cv_target_arch="AArch64" ;;
   arm*-*)                 llvm_cv_target_arch="ARM" ;;
-  aarch64*-*)             llvm_cv_target_arch="ARM64" ;;
+  aarch64*-*)             llvm_cv_target_arch="AArch64" ;;
   mips-* | mips64-*)      llvm_cv_target_arch="Mips" ;;
   mipsel-* | mips64el-*)  llvm_cv_target_arch="Mips" ;;
   xcore-*)                llvm_cv_target_arch="XCore" ;;
@@ -455,9 +455,9 @@ case $host in
   amd64-* | x86_64-*)     host_arch="x86_64" ;;
   sparc*-*)               host_arch="Sparc" ;;
   powerpc*-*)             host_arch="PowerPC" ;;
-  arm64*-*)               host_arch="ARM64" ;;
+  arm64*-*)               host_arch="AArch64" ;;
   arm*-*)                 host_arch="ARM" ;;
-  aarch64*-*)             host_arch="ARM64" ;;
+  aarch64*-*)             host_arch="AArch64" ;;
   mips-* | mips64-*)      host_arch="Mips" ;;
   mipsel-* | mips64el-*)  host_arch="Mips" ;;
   xcore-*)                host_arch="XCore" ;;
@@ -796,7 +796,7 @@ else
   esac
 fi
 
-TARGETS_WITH_JIT="ARM ARM64 Mips PowerPC SystemZ X86"
+TARGETS_WITH_JIT="ARM AArch64 Mips PowerPC SystemZ X86"
 AC_SUBST(TARGETS_WITH_JIT,$TARGETS_WITH_JIT)
 
 dnl Allow enablement of building and installing docs
@@ -949,7 +949,7 @@ if test "$llvm_cv_enable_crash_overrides" = "yes" ; then
 fi
 
 dnl List all possible targets
-ALL_TARGETS="X86 Sparc PowerPC ARM ARM64 Mips XCore MSP430 CppBackend NVPTX Hexagon SystemZ R600"
+ALL_TARGETS="X86 Sparc PowerPC ARM AArch64 Mips XCore MSP430 CppBackend NVPTX Hexagon SystemZ R600"
 AC_SUBST(ALL_TARGETS,$ALL_TARGETS)
 
 dnl Allow specific targets to be specified for building (or not)
@@ -970,8 +970,8 @@ case "$enableval" in
         x86_64)   TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
         sparc)    TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
         powerpc)  TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
-        aarch64)  TARGETS_TO_BUILD="ARM64 $TARGETS_TO_BUILD" ;;
-        arm64)    TARGETS_TO_BUILD="ARM64 $TARGETS_TO_BUILD" ;;
+        aarch64)  TARGETS_TO_BUILD="AArch64 $TARGETS_TO_BUILD" ;;
+        arm64)    TARGETS_TO_BUILD="AArch64 $TARGETS_TO_BUILD" ;;
         arm)      TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
         mips)     TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
         mipsel)   TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
@@ -989,7 +989,7 @@ case "$enableval" in
             x86_64)      TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
             Sparc)       TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
             PowerPC)     TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
-            AArch64)     TARGETS_TO_BUILD="ARM64 $TARGETS_TO_BUILD" ;;
+            AArch64)     TARGETS_TO_BUILD="AArch64 $TARGETS_TO_BUILD" ;;
             ARM)         TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
             Mips)        TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
             XCore)       TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
index ca4af73..1325e79 100755 (executable)
@@ -372,7 +372,7 @@ elseif (LLVM_NATIVE_ARCH MATCHES "powerpc")
 elseif (LLVM_NATIVE_ARCH MATCHES "aarch64")
   set(LLVM_NATIVE_ARCH AArch64)
 elseif (LLVM_NATIVE_ARCH MATCHES "arm64")
-  set(LLVM_NATIVE_ARCH ARM64)
+  set(LLVM_NATIVE_ARCH AArch64)
 elseif (LLVM_NATIVE_ARCH MATCHES "arm")
   set(LLVM_NATIVE_ARCH ARM)
 elseif (LLVM_NATIVE_ARCH MATCHES "mips")
index a5babe9..e1959df 100755 (executable)
--- a/configure
+++ b/configure
@@ -4151,9 +4151,9 @@ else
   amd64-* | x86_64-*)     llvm_cv_target_arch="x86_64" ;;
   sparc*-*)               llvm_cv_target_arch="Sparc" ;;
   powerpc*-*)             llvm_cv_target_arch="PowerPC" ;;
-  arm64*-*)               llvm_cv_target_arch="ARM64" ;;
+  arm64*-*)               llvm_cv_target_arch="AArch64" ;;
   arm*-*)                 llvm_cv_target_arch="ARM" ;;
-  aarch64*-*)             llvm_cv_target_arch="ARM64" ;;
+  aarch64*-*)             llvm_cv_target_arch="AArch64" ;;
   mips-* | mips64-*)      llvm_cv_target_arch="Mips" ;;
   mipsel-* | mips64el-*)  llvm_cv_target_arch="Mips" ;;
   xcore-*)                llvm_cv_target_arch="XCore" ;;
@@ -4188,9 +4188,9 @@ case $host in
   amd64-* | x86_64-*)     host_arch="x86_64" ;;
   sparc*-*)               host_arch="Sparc" ;;
   powerpc*-*)             host_arch="PowerPC" ;;
-  arm64*-*)               host_arch="ARM64" ;;
+  arm64*-*)               host_arch="AArch64" ;;
   arm*-*)                 host_arch="ARM" ;;
-  aarch64*-*)             host_arch="ARM64" ;;
+  aarch64*-*)             host_arch="AArch64" ;;
   mips-* | mips64-*)      host_arch="Mips" ;;
   mipsel-* | mips64el-*)  host_arch="Mips" ;;
   xcore-*)                host_arch="XCore" ;;
@@ -5120,7 +5120,7 @@ else
   esac
 fi
 
-TARGETS_WITH_JIT="ARM ARM64 Mips PowerPC SystemZ X86"
+TARGETS_WITH_JIT="ARM AArch64 Mips PowerPC SystemZ X86"
 TARGETS_WITH_JIT=$TARGETS_WITH_JIT
 
 
@@ -5357,7 +5357,7 @@ _ACEOF
 
 fi
 
-ALL_TARGETS="X86 Sparc PowerPC ARM ARM64 Mips XCore MSP430 CppBackend NVPTX Hexagon SystemZ R600"
+ALL_TARGETS="X86 Sparc PowerPC ARM AArch64 Mips XCore MSP430 CppBackend NVPTX Hexagon SystemZ R600"
 ALL_TARGETS=$ALL_TARGETS
 
 
@@ -5380,8 +5380,8 @@ case "$enableval" in
         x86_64)   TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
         sparc)    TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
         powerpc)  TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
-        aarch64)  TARGETS_TO_BUILD="ARM64 $TARGETS_TO_BUILD" ;;
-        arm64)    TARGETS_TO_BUILD="ARM64 $TARGETS_TO_BUILD" ;;
+        aarch64)  TARGETS_TO_BUILD="AArch64 $TARGETS_TO_BUILD" ;;
+        arm64)    TARGETS_TO_BUILD="AArch64 $TARGETS_TO_BUILD" ;;
         arm)      TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
         mips)     TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
         mipsel)   TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
@@ -5399,7 +5399,7 @@ case "$enableval" in
             x86_64)      TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
             Sparc)       TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
             PowerPC)     TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
-            AArch64)     TARGETS_TO_BUILD="ARM64 $TARGETS_TO_BUILD" ;;
+            AArch64)     TARGETS_TO_BUILD="AArch64 $TARGETS_TO_BUILD" ;;
             ARM)         TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
             Mips)        TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
             XCore)       TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
index fa8d3c0..9b72eca 100644 (file)
@@ -6877,7 +6877,7 @@ register in surrounding code, including inline assembly. Because of that,
 allocatable registers are not supported.
 
 Warning: So far it only works with the stack pointer on selected
-architectures (ARM, ARM64, AArch64, PowerPC and x86_64). Significant amount of
+architectures (ARM, AArch64, PowerPC and x86_64). Significant amount of
 work is needed to support other registers and even more so, allocatable
 registers.
 
index b133b4e..edd1621 100644 (file)
@@ -533,7 +533,7 @@ def int_clear_cache : Intrinsic<[], [llvm_ptr_ty, llvm_ptr_ty],
 include "llvm/IR/IntrinsicsPowerPC.td"
 include "llvm/IR/IntrinsicsX86.td"
 include "llvm/IR/IntrinsicsARM.td"
-include "llvm/IR/IntrinsicsARM64.td"
+include "llvm/IR/IntrinsicsAArch64.td"
 include "llvm/IR/IntrinsicsXCore.td"
 include "llvm/IR/IntrinsicsHexagon.td"
 include "llvm/IR/IntrinsicsNVVM.td"
diff --git a/include/llvm/IR/IntrinsicsAArch64.td b/include/llvm/IR/IntrinsicsAArch64.td
new file mode 100644 (file)
index 0000000..23757aa
--- /dev/null
@@ -0,0 +1,636 @@
+//===- IntrinsicsAARCH64.td - Defines AARCH64 intrinsics ---*- tablegen -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines all of the AARCH64-specific intrinsics.
+//
+//===----------------------------------------------------------------------===//
+
+let TargetPrefix = "aarch64" in {
+
+def int_aarch64_ldxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty]>;
+def int_aarch64_ldaxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty]>;
+def int_aarch64_stxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty]>;
+def int_aarch64_stlxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty]>;
+
+def int_aarch64_ldxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty]>;
+def int_aarch64_ldaxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty]>;
+def int_aarch64_stxp : Intrinsic<[llvm_i32_ty],
+                               [llvm_i64_ty, llvm_i64_ty, llvm_ptr_ty]>;
+def int_aarch64_stlxp : Intrinsic<[llvm_i32_ty],
+                                [llvm_i64_ty, llvm_i64_ty, llvm_ptr_ty]>;
+
+def int_aarch64_clrex : Intrinsic<[]>;
+
+def int_aarch64_sdiv : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
+                                LLVMMatchType<0>], [IntrNoMem]>;
+def int_aarch64_udiv : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
+                                LLVMMatchType<0>], [IntrNoMem]>;
+}
+
+//===----------------------------------------------------------------------===//
+// Advanced SIMD (NEON)
+
+let TargetPrefix = "aarch64" in {  // All intrinsics start with "llvm.aarch64.".
+  class AdvSIMD_2Scalar_Float_Intrinsic
+    : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
+                [IntrNoMem]>;
+
+  class AdvSIMD_FPToIntRounding_Intrinsic
+    : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty], [IntrNoMem]>;
+
+  class AdvSIMD_1IntArg_Intrinsic
+    : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrNoMem]>;
+  class AdvSIMD_1FloatArg_Intrinsic
+    : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
+  class AdvSIMD_1VectorArg_Intrinsic
+    : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
+  class AdvSIMD_1VectorArg_Expand_Intrinsic
+    : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
+  class AdvSIMD_1VectorArg_Long_Intrinsic
+    : Intrinsic<[llvm_anyvector_ty], [LLVMTruncatedType<0>], [IntrNoMem]>;
+  class AdvSIMD_1IntArg_Narrow_Intrinsic
+    : Intrinsic<[llvm_anyint_ty], [llvm_anyint_ty], [IntrNoMem]>;
+  class AdvSIMD_1VectorArg_Narrow_Intrinsic
+    : Intrinsic<[llvm_anyint_ty], [LLVMExtendedType<0>], [IntrNoMem]>;
+  class AdvSIMD_1VectorArg_Int_Across_Intrinsic
+    : Intrinsic<[llvm_anyint_ty], [llvm_anyvector_ty], [IntrNoMem]>;
+  class AdvSIMD_1VectorArg_Float_Across_Intrinsic
+    : Intrinsic<[llvm_anyfloat_ty], [llvm_anyvector_ty], [IntrNoMem]>;
+
+  class AdvSIMD_2IntArg_Intrinsic
+    : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
+                [IntrNoMem]>;
+  class AdvSIMD_2FloatArg_Intrinsic
+    : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
+                [IntrNoMem]>;
+  class AdvSIMD_2VectorArg_Intrinsic
+    : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
+                [IntrNoMem]>;
+  class AdvSIMD_2VectorArg_Compare_Intrinsic
+    : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, LLVMMatchType<1>],
+                [IntrNoMem]>;
+  class AdvSIMD_2Arg_FloatCompare_Intrinsic
+    : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, LLVMMatchType<1>],
+                [IntrNoMem]>;
+  class AdvSIMD_2VectorArg_Long_Intrinsic
+    : Intrinsic<[llvm_anyvector_ty],
+                [LLVMTruncatedType<0>, LLVMTruncatedType<0>],
+                [IntrNoMem]>;
+  class AdvSIMD_2VectorArg_Wide_Intrinsic
+    : Intrinsic<[llvm_anyvector_ty],
+                [LLVMMatchType<0>, LLVMTruncatedType<0>],
+                [IntrNoMem]>;
+  class AdvSIMD_2VectorArg_Narrow_Intrinsic
+    : Intrinsic<[llvm_anyvector_ty],
+                [LLVMExtendedType<0>, LLVMExtendedType<0>],
+                [IntrNoMem]>;
+  class AdvSIMD_2Arg_Scalar_Narrow_Intrinsic
+    : Intrinsic<[llvm_anyint_ty],
+                [LLVMExtendedType<0>, llvm_i32_ty],
+                [IntrNoMem]>;
+  class AdvSIMD_2VectorArg_Scalar_Expand_BySize_Intrinsic
+    : Intrinsic<[llvm_anyvector_ty],
+                [llvm_anyvector_ty],
+                [IntrNoMem]>;
+  class AdvSIMD_2VectorArg_Scalar_Wide_BySize_Intrinsic
+    : Intrinsic<[llvm_anyvector_ty],
+                [LLVMTruncatedType<0>],
+                [IntrNoMem]>;
+  class AdvSIMD_2VectorArg_Scalar_Wide_Intrinsic
+    : Intrinsic<[llvm_anyvector_ty],
+                [LLVMTruncatedType<0>, llvm_i32_ty],
+                [IntrNoMem]>;
+  class AdvSIMD_2VectorArg_Tied_Narrow_Intrinsic
+    : Intrinsic<[llvm_anyvector_ty],
+                [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty],
+                [IntrNoMem]>;
+
+  class AdvSIMD_3VectorArg_Intrinsic
+      : Intrinsic<[llvm_anyvector_ty],
+               [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
+               [IntrNoMem]>;
+  class AdvSIMD_3VectorArg_Scalar_Intrinsic
+      : Intrinsic<[llvm_anyvector_ty],
+               [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty],
+               [IntrNoMem]>;
+  class AdvSIMD_3VectorArg_Tied_Narrow_Intrinsic
+      : Intrinsic<[llvm_anyvector_ty],
+               [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty,
+                LLVMMatchType<1>], [IntrNoMem]>;
+  class AdvSIMD_3VectorArg_Scalar_Tied_Narrow_Intrinsic
+    : Intrinsic<[llvm_anyvector_ty],
+                [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty, llvm_i32_ty],
+                [IntrNoMem]>;
+  class AdvSIMD_CvtFxToFP_Intrinsic
+    : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty],
+                [IntrNoMem]>;
+  class AdvSIMD_CvtFPToFx_Intrinsic
+    : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty],
+                [IntrNoMem]>;
+}
+
+// Arithmetic ops
+
+let Properties = [IntrNoMem] in {
+  // Vector Add Across Lanes
+  def int_aarch64_neon_saddv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
+  def int_aarch64_neon_uaddv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
+  def int_aarch64_neon_faddv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
+
+  // Vector Long Add Across Lanes
+  def int_aarch64_neon_saddlv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
+  def int_aarch64_neon_uaddlv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
+
+  // Vector Halving Add
+  def int_aarch64_neon_shadd : AdvSIMD_2VectorArg_Intrinsic;
+  def int_aarch64_neon_uhadd : AdvSIMD_2VectorArg_Intrinsic;
+
+  // Vector Rounding Halving Add
+  def int_aarch64_neon_srhadd : AdvSIMD_2VectorArg_Intrinsic;
+  def int_aarch64_neon_urhadd : AdvSIMD_2VectorArg_Intrinsic;
+
+  // Vector Saturating Add
+  def int_aarch64_neon_sqadd : AdvSIMD_2IntArg_Intrinsic;
+  def int_aarch64_neon_suqadd : AdvSIMD_2IntArg_Intrinsic;
+  def int_aarch64_neon_usqadd : AdvSIMD_2IntArg_Intrinsic;
+  def int_aarch64_neon_uqadd : AdvSIMD_2IntArg_Intrinsic;
+
+  // Vector Add High-Half
+  // FIXME: this is a legacy intrinsic for aarch64_simd.h. Remove it when that
+  // header is no longer supported.
+  def int_aarch64_neon_addhn : AdvSIMD_2VectorArg_Narrow_Intrinsic;
+
+  // Vector Rounding Add High-Half
+  def int_aarch64_neon_raddhn : AdvSIMD_2VectorArg_Narrow_Intrinsic;
+
+  // Vector Saturating Doubling Multiply High
+  def int_aarch64_neon_sqdmulh : AdvSIMD_2IntArg_Intrinsic;
+
+  // Vector Saturating Rounding Doubling Multiply High
+  def int_aarch64_neon_sqrdmulh : AdvSIMD_2IntArg_Intrinsic;
+
+  // Vector Polynominal Multiply
+  def int_aarch64_neon_pmul : AdvSIMD_2VectorArg_Intrinsic;
+
+  // Vector Long Multiply
+  def int_aarch64_neon_smull : AdvSIMD_2VectorArg_Long_Intrinsic;
+  def int_aarch64_neon_umull : AdvSIMD_2VectorArg_Long_Intrinsic;
+  def int_aarch64_neon_pmull : AdvSIMD_2VectorArg_Long_Intrinsic;
+
+  // 64-bit polynomial multiply really returns an i128, which is not legal. Fake
+  // it with a v16i8.
+  def int_aarch64_neon_pmull64 :
+        Intrinsic<[llvm_v16i8_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
+
+  // Vector Extending Multiply
+  def int_aarch64_neon_fmulx : AdvSIMD_2FloatArg_Intrinsic {
+    let Properties = [IntrNoMem, Commutative];
+  }
+
+  // Vector Saturating Doubling Long Multiply
+  def int_aarch64_neon_sqdmull : AdvSIMD_2VectorArg_Long_Intrinsic;
+  def int_aarch64_neon_sqdmulls_scalar
+    : Intrinsic<[llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
+
+  // Vector Halving Subtract
+  def int_aarch64_neon_shsub : AdvSIMD_2VectorArg_Intrinsic;
+  def int_aarch64_neon_uhsub : AdvSIMD_2VectorArg_Intrinsic;
+
+  // Vector Saturating Subtract
+  def int_aarch64_neon_sqsub : AdvSIMD_2IntArg_Intrinsic;
+  def int_aarch64_neon_uqsub : AdvSIMD_2IntArg_Intrinsic;
+
+  // Vector Subtract High-Half
+  // FIXME: this is a legacy intrinsic for aarch64_simd.h. Remove it when that
+  // header is no longer supported.
+  def int_aarch64_neon_subhn : AdvSIMD_2VectorArg_Narrow_Intrinsic;
+
+  // Vector Rounding Subtract High-Half
+  def int_aarch64_neon_rsubhn : AdvSIMD_2VectorArg_Narrow_Intrinsic;
+
+  // Vector Compare Absolute Greater-than-or-equal
+  def int_aarch64_neon_facge : AdvSIMD_2Arg_FloatCompare_Intrinsic;
+
+  // Vector Compare Absolute Greater-than
+  def int_aarch64_neon_facgt : AdvSIMD_2Arg_FloatCompare_Intrinsic;
+
+  // Vector Absolute Difference
+  def int_aarch64_neon_sabd : AdvSIMD_2VectorArg_Intrinsic;
+  def int_aarch64_neon_uabd : AdvSIMD_2VectorArg_Intrinsic;
+  def int_aarch64_neon_fabd : AdvSIMD_2VectorArg_Intrinsic;
+
+  // Scalar Absolute Difference
+  def int_aarch64_sisd_fabd : AdvSIMD_2Scalar_Float_Intrinsic;
+
+  // Vector Max
+  def int_aarch64_neon_smax : AdvSIMD_2VectorArg_Intrinsic;
+  def int_aarch64_neon_umax : AdvSIMD_2VectorArg_Intrinsic;
+  def int_aarch64_neon_fmax : AdvSIMD_2VectorArg_Intrinsic;
+  def int_aarch64_neon_fmaxnmp : AdvSIMD_2VectorArg_Intrinsic;
+
+  // Vector Max Across Lanes
+  def int_aarch64_neon_smaxv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
+  def int_aarch64_neon_umaxv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
+  def int_aarch64_neon_fmaxv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
+  def int_aarch64_neon_fmaxnmv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
+
+  // Vector Min
+  def int_aarch64_neon_smin : AdvSIMD_2VectorArg_Intrinsic;
+  def int_aarch64_neon_umin : AdvSIMD_2VectorArg_Intrinsic;
+  def int_aarch64_neon_fmin : AdvSIMD_2VectorArg_Intrinsic;
+  def int_aarch64_neon_fminnmp : AdvSIMD_2VectorArg_Intrinsic;
+
+  // Vector Min/Max Number
+  def int_aarch64_neon_fminnm : AdvSIMD_2FloatArg_Intrinsic;
+  def int_aarch64_neon_fmaxnm : AdvSIMD_2FloatArg_Intrinsic;
+
+  // Vector Min Across Lanes
+  def int_aarch64_neon_sminv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
+  def int_aarch64_neon_uminv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
+  def int_aarch64_neon_fminv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
+  def int_aarch64_neon_fminnmv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
+
+  // Pairwise Add
+  def int_aarch64_neon_addp : AdvSIMD_2VectorArg_Intrinsic;
+
+  // Long Pairwise Add
+  // FIXME: In theory, we shouldn't need intrinsics for saddlp or
+  // uaddlp, but tblgen's type inference currently can't handle the
+  // pattern fragments this ends up generating.
+  def int_aarch64_neon_saddlp : AdvSIMD_1VectorArg_Expand_Intrinsic;
+  def int_aarch64_neon_uaddlp : AdvSIMD_1VectorArg_Expand_Intrinsic;
+
+  // Folding Maximum
+  def int_aarch64_neon_smaxp : AdvSIMD_2VectorArg_Intrinsic;
+  def int_aarch64_neon_umaxp : AdvSIMD_2VectorArg_Intrinsic;
+  def int_aarch64_neon_fmaxp : AdvSIMD_2VectorArg_Intrinsic;
+
+  // Folding Minimum
+  def int_aarch64_neon_sminp : AdvSIMD_2VectorArg_Intrinsic;
+  def int_aarch64_neon_uminp : AdvSIMD_2VectorArg_Intrinsic;
+  def int_aarch64_neon_fminp : AdvSIMD_2VectorArg_Intrinsic;
+
+  // Reciprocal Estimate/Step
+  def int_aarch64_neon_frecps : AdvSIMD_2FloatArg_Intrinsic;
+  def int_aarch64_neon_frsqrts : AdvSIMD_2FloatArg_Intrinsic;
+
+  // Reciprocal Exponent
+  def int_aarch64_neon_frecpx : AdvSIMD_1FloatArg_Intrinsic;
+
+  // Vector Saturating Shift Left
+  def int_aarch64_neon_sqshl : AdvSIMD_2IntArg_Intrinsic;
+  def int_aarch64_neon_uqshl : AdvSIMD_2IntArg_Intrinsic;
+
+  // Vector Rounding Shift Left
+  def int_aarch64_neon_srshl : AdvSIMD_2IntArg_Intrinsic;
+  def int_aarch64_neon_urshl : AdvSIMD_2IntArg_Intrinsic;
+
+  // Vector Saturating Rounding Shift Left
+  def int_aarch64_neon_sqrshl : AdvSIMD_2IntArg_Intrinsic;
+  def int_aarch64_neon_uqrshl : AdvSIMD_2IntArg_Intrinsic;
+
+  // Vector Signed->Unsigned Shift Left by Constant
+  def int_aarch64_neon_sqshlu : AdvSIMD_2IntArg_Intrinsic;
+
+  // Vector Signed->Unsigned Narrowing Saturating Shift Right by Constant
+  def int_aarch64_neon_sqshrun : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
+
+  // Vector Signed->Unsigned Rounding Narrowing Saturating Shift Right by Const
+  def int_aarch64_neon_sqrshrun : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
+
+  // Vector Narrowing Shift Right by Constant
+  def int_aarch64_neon_sqshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
+  def int_aarch64_neon_uqshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
+
+  // Vector Rounding Narrowing Shift Right by Constant
+  def int_aarch64_neon_rshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
+
+  // Vector Rounding Narrowing Saturating Shift Right by Constant
+  def int_aarch64_neon_sqrshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
+  def int_aarch64_neon_uqrshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
+
+  // Vector Shift Left
+  def int_aarch64_neon_sshl : AdvSIMD_2IntArg_Intrinsic;
+  def int_aarch64_neon_ushl : AdvSIMD_2IntArg_Intrinsic;
+
+  // Vector Widening Shift Left by Constant
+  def int_aarch64_neon_shll : AdvSIMD_2VectorArg_Scalar_Wide_BySize_Intrinsic;
+  def int_aarch64_neon_sshll : AdvSIMD_2VectorArg_Scalar_Wide_Intrinsic;
+  def int_aarch64_neon_ushll : AdvSIMD_2VectorArg_Scalar_Wide_Intrinsic;
+
+  // Vector Shift Right by Constant and Insert
+  def int_aarch64_neon_vsri : AdvSIMD_3VectorArg_Scalar_Intrinsic;
+
+  // Vector Shift Left by Constant and Insert
+  def int_aarch64_neon_vsli : AdvSIMD_3VectorArg_Scalar_Intrinsic;
+
+  // Vector Saturating Narrow
+  def int_aarch64_neon_scalar_sqxtn: AdvSIMD_1IntArg_Narrow_Intrinsic;
+  def int_aarch64_neon_scalar_uqxtn : AdvSIMD_1IntArg_Narrow_Intrinsic;
+  def int_aarch64_neon_sqxtn : AdvSIMD_1VectorArg_Narrow_Intrinsic;
+  def int_aarch64_neon_uqxtn : AdvSIMD_1VectorArg_Narrow_Intrinsic;
+
+  // Vector Saturating Extract and Unsigned Narrow
+  def int_aarch64_neon_scalar_sqxtun : AdvSIMD_1IntArg_Narrow_Intrinsic;
+  def int_aarch64_neon_sqxtun : AdvSIMD_1VectorArg_Narrow_Intrinsic;
+
+  // Vector Absolute Value
+  def int_aarch64_neon_abs : AdvSIMD_1IntArg_Intrinsic;
+
+  // Vector Saturating Absolute Value
+  def int_aarch64_neon_sqabs : AdvSIMD_1IntArg_Intrinsic;
+
+  // Vector Saturating Negation
+  def int_aarch64_neon_sqneg : AdvSIMD_1IntArg_Intrinsic;
+
+  // Vector Count Leading Sign Bits
+  def int_aarch64_neon_cls : AdvSIMD_1VectorArg_Intrinsic;
+
+  // Vector Reciprocal Estimate
+  def int_aarch64_neon_urecpe : AdvSIMD_1VectorArg_Intrinsic;
+  def int_aarch64_neon_frecpe : AdvSIMD_1FloatArg_Intrinsic;
+
+  // Vector Square Root Estimate
+  def int_aarch64_neon_ursqrte : AdvSIMD_1VectorArg_Intrinsic;
+  def int_aarch64_neon_frsqrte : AdvSIMD_1FloatArg_Intrinsic;
+
+  // Vector Bitwise Reverse
+  def int_aarch64_neon_rbit : AdvSIMD_1VectorArg_Intrinsic;
+
+  // Vector Conversions Between Half-Precision and Single-Precision.
+  def int_aarch64_neon_vcvtfp2hf
+    : Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>;
+  def int_aarch64_neon_vcvthf2fp
+    : Intrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>;
+
+  // Vector Conversions Between Floating-point and Fixed-point.
+  def int_aarch64_neon_vcvtfp2fxs : AdvSIMD_CvtFPToFx_Intrinsic;
+  def int_aarch64_neon_vcvtfp2fxu : AdvSIMD_CvtFPToFx_Intrinsic;
+  def int_aarch64_neon_vcvtfxs2fp : AdvSIMD_CvtFxToFP_Intrinsic;
+  def int_aarch64_neon_vcvtfxu2fp : AdvSIMD_CvtFxToFP_Intrinsic;
+
+  // Vector FP->Int Conversions
+  def int_aarch64_neon_fcvtas : AdvSIMD_FPToIntRounding_Intrinsic;
+  def int_aarch64_neon_fcvtau : AdvSIMD_FPToIntRounding_Intrinsic;
+  def int_aarch64_neon_fcvtms : AdvSIMD_FPToIntRounding_Intrinsic;
+  def int_aarch64_neon_fcvtmu : AdvSIMD_FPToIntRounding_Intrinsic;
+  def int_aarch64_neon_fcvtns : AdvSIMD_FPToIntRounding_Intrinsic;
+  def int_aarch64_neon_fcvtnu : AdvSIMD_FPToIntRounding_Intrinsic;
+  def int_aarch64_neon_fcvtps : AdvSIMD_FPToIntRounding_Intrinsic;
+  def int_aarch64_neon_fcvtpu : AdvSIMD_FPToIntRounding_Intrinsic;
+  def int_aarch64_neon_fcvtzs : AdvSIMD_FPToIntRounding_Intrinsic;
+  def int_aarch64_neon_fcvtzu : AdvSIMD_FPToIntRounding_Intrinsic;
+
+  // Vector FP Rounding: only ties to even is unrepresented by a normal
+  // intrinsic.
+  def int_aarch64_neon_frintn : AdvSIMD_1FloatArg_Intrinsic;
+
+  // Scalar FP->Int conversions
+
+  // Vector FP Inexact Narrowing
+  def int_aarch64_neon_fcvtxn : AdvSIMD_1VectorArg_Expand_Intrinsic;
+
+  // Scalar FP Inexact Narrowing
+  def int_aarch64_sisd_fcvtxn : Intrinsic<[llvm_float_ty], [llvm_double_ty],
+                                        [IntrNoMem]>;
+}
+
+let TargetPrefix = "aarch64" in {  // All intrinsics start with "llvm.aarch64.".
+  class AdvSIMD_2Vector2Index_Intrinsic
+    : Intrinsic<[llvm_anyvector_ty],
+                [llvm_anyvector_ty, llvm_i64_ty, LLVMMatchType<0>, llvm_i64_ty],
+                [IntrNoMem]>;
+}
+
+// Vector element to element moves
+def int_aarch64_neon_vcopy_lane: AdvSIMD_2Vector2Index_Intrinsic;
+
+let TargetPrefix = "aarch64" in {  // All intrinsics start with "llvm.aarch64.".
+  class AdvSIMD_1Vec_Load_Intrinsic
+      : Intrinsic<[llvm_anyvector_ty], [LLVMAnyPointerType<LLVMMatchType<0>>],
+                  [IntrReadArgMem]>;
+  class AdvSIMD_1Vec_Store_Lane_Intrinsic
+    : Intrinsic<[], [llvm_anyvector_ty, llvm_i64_ty, llvm_anyptr_ty],
+                [IntrReadWriteArgMem, NoCapture<2>]>;
+
+  class AdvSIMD_2Vec_Load_Intrinsic
+    : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
+                [LLVMAnyPointerType<LLVMMatchType<0>>],
+                [IntrReadArgMem]>;
+  class AdvSIMD_2Vec_Load_Lane_Intrinsic
+    : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
+                [LLVMMatchType<0>, LLVMMatchType<0>,
+                 llvm_i64_ty, llvm_anyptr_ty],
+                [IntrReadArgMem]>;
+  class AdvSIMD_2Vec_Store_Intrinsic
+    : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
+                     LLVMAnyPointerType<LLVMMatchType<0>>],
+                [IntrReadWriteArgMem, NoCapture<2>]>;
+  class AdvSIMD_2Vec_Store_Lane_Intrinsic
+    : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
+                 llvm_i64_ty, llvm_anyptr_ty],
+                [IntrReadWriteArgMem, NoCapture<3>]>;
+
+  class AdvSIMD_3Vec_Load_Intrinsic
+    : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>],
+                [LLVMAnyPointerType<LLVMMatchType<0>>],
+                [IntrReadArgMem]>;
+  class AdvSIMD_3Vec_Load_Lane_Intrinsic
+    : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>],
+                [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>,
+                 llvm_i64_ty, llvm_anyptr_ty],
+                [IntrReadArgMem]>;
+  class AdvSIMD_3Vec_Store_Intrinsic
+    : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
+                     LLVMMatchType<0>, LLVMAnyPointerType<LLVMMatchType<0>>],
+                [IntrReadWriteArgMem, NoCapture<3>]>;
+  class AdvSIMD_3Vec_Store_Lane_Intrinsic
+    : Intrinsic<[], [llvm_anyvector_ty,
+                 LLVMMatchType<0>, LLVMMatchType<0>,
+                 llvm_i64_ty, llvm_anyptr_ty],
+                [IntrReadWriteArgMem, NoCapture<4>]>;
+
+  class AdvSIMD_4Vec_Load_Intrinsic
+    : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
+                 LLVMMatchType<0>, LLVMMatchType<0>],
+                [LLVMAnyPointerType<LLVMMatchType<0>>],
+                [IntrReadArgMem]>;
+  class AdvSIMD_4Vec_Load_Lane_Intrinsic
+    : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
+                 LLVMMatchType<0>, LLVMMatchType<0>],
+                [LLVMMatchType<0>, LLVMMatchType<0>,
+                 LLVMMatchType<0>, LLVMMatchType<0>,
+                 llvm_i64_ty, llvm_anyptr_ty],
+                [IntrReadArgMem]>;
+  class AdvSIMD_4Vec_Store_Intrinsic
+    : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
+                 LLVMMatchType<0>, LLVMMatchType<0>,
+                 LLVMAnyPointerType<LLVMMatchType<0>>],
+                [IntrReadWriteArgMem, NoCapture<4>]>;
+  class AdvSIMD_4Vec_Store_Lane_Intrinsic
+    : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
+                 LLVMMatchType<0>, LLVMMatchType<0>,
+                 llvm_i64_ty, llvm_anyptr_ty],
+                [IntrReadWriteArgMem, NoCapture<5>]>;
+}
+
+// Memory ops
+
+def int_aarch64_neon_ld1x2 : AdvSIMD_2Vec_Load_Intrinsic;
+def int_aarch64_neon_ld1x3 : AdvSIMD_3Vec_Load_Intrinsic;
+def int_aarch64_neon_ld1x4 : AdvSIMD_4Vec_Load_Intrinsic;
+
+def int_aarch64_neon_st1x2 : AdvSIMD_2Vec_Store_Intrinsic;
+def int_aarch64_neon_st1x3 : AdvSIMD_3Vec_Store_Intrinsic;
+def int_aarch64_neon_st1x4 : AdvSIMD_4Vec_Store_Intrinsic;
+
+def int_aarch64_neon_ld2 : AdvSIMD_2Vec_Load_Intrinsic;
+def int_aarch64_neon_ld3 : AdvSIMD_3Vec_Load_Intrinsic;
+def int_aarch64_neon_ld4 : AdvSIMD_4Vec_Load_Intrinsic;
+
+def int_aarch64_neon_ld2lane : AdvSIMD_2Vec_Load_Lane_Intrinsic;
+def int_aarch64_neon_ld3lane : AdvSIMD_3Vec_Load_Lane_Intrinsic;
+def int_aarch64_neon_ld4lane : AdvSIMD_4Vec_Load_Lane_Intrinsic;
+
+def int_aarch64_neon_ld2r : AdvSIMD_2Vec_Load_Intrinsic;
+def int_aarch64_neon_ld3r : AdvSIMD_3Vec_Load_Intrinsic;
+def int_aarch64_neon_ld4r : AdvSIMD_4Vec_Load_Intrinsic;
+
+def int_aarch64_neon_st2  : AdvSIMD_2Vec_Store_Intrinsic;
+def int_aarch64_neon_st3  : AdvSIMD_3Vec_Store_Intrinsic;
+def int_aarch64_neon_st4  : AdvSIMD_4Vec_Store_Intrinsic;
+
+def int_aarch64_neon_st2lane  : AdvSIMD_2Vec_Store_Lane_Intrinsic;
+def int_aarch64_neon_st3lane  : AdvSIMD_3Vec_Store_Lane_Intrinsic;
+def int_aarch64_neon_st4lane  : AdvSIMD_4Vec_Store_Lane_Intrinsic;
+
+let TargetPrefix = "aarch64" in {  // All intrinsics start with "llvm.aarch64.".
+  class AdvSIMD_Tbl1_Intrinsic
+    : Intrinsic<[llvm_anyvector_ty], [llvm_v16i8_ty, LLVMMatchType<0>],
+                [IntrNoMem]>;
+  class AdvSIMD_Tbl2_Intrinsic
+    : Intrinsic<[llvm_anyvector_ty],
+                [llvm_v16i8_ty, llvm_v16i8_ty, LLVMMatchType<0>], [IntrNoMem]>;
+  class AdvSIMD_Tbl3_Intrinsic
+    : Intrinsic<[llvm_anyvector_ty],
+                [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty,
+                 LLVMMatchType<0>],
+                [IntrNoMem]>;
+  class AdvSIMD_Tbl4_Intrinsic
+    : Intrinsic<[llvm_anyvector_ty],
+                [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty,
+                 LLVMMatchType<0>],
+                [IntrNoMem]>;
+
+  class AdvSIMD_Tbx1_Intrinsic
+    : Intrinsic<[llvm_anyvector_ty],
+                [LLVMMatchType<0>, llvm_v16i8_ty, LLVMMatchType<0>],
+                [IntrNoMem]>;
+  class AdvSIMD_Tbx2_Intrinsic
+    : Intrinsic<[llvm_anyvector_ty],
+                [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty,
+                 LLVMMatchType<0>],
+                [IntrNoMem]>;
+  class AdvSIMD_Tbx3_Intrinsic
+    : Intrinsic<[llvm_anyvector_ty],
+                [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty,
+                 llvm_v16i8_ty, LLVMMatchType<0>],
+                [IntrNoMem]>;
+  class AdvSIMD_Tbx4_Intrinsic
+    : Intrinsic<[llvm_anyvector_ty],
+                [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty,
+                 llvm_v16i8_ty, llvm_v16i8_ty, LLVMMatchType<0>],
+                [IntrNoMem]>;
+}
+def int_aarch64_neon_tbl1 : AdvSIMD_Tbl1_Intrinsic;
+def int_aarch64_neon_tbl2 : AdvSIMD_Tbl2_Intrinsic;
+def int_aarch64_neon_tbl3 : AdvSIMD_Tbl3_Intrinsic;
+def int_aarch64_neon_tbl4 : AdvSIMD_Tbl4_Intrinsic;
+
+def int_aarch64_neon_tbx1 : AdvSIMD_Tbx1_Intrinsic;
+def int_aarch64_neon_tbx2 : AdvSIMD_Tbx2_Intrinsic;
+def int_aarch64_neon_tbx3 : AdvSIMD_Tbx3_Intrinsic;
+def int_aarch64_neon_tbx4 : AdvSIMD_Tbx4_Intrinsic;
+
+let TargetPrefix = "aarch64" in {
+  class Crypto_AES_DataKey_Intrinsic
+    : Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
+
+  class Crypto_AES_Data_Intrinsic
+    : Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty], [IntrNoMem]>;
+
+  // SHA intrinsic taking 5 words of the hash (v4i32, i32) and 4 of the schedule
+  // (v4i32).
+  class Crypto_SHA_5Hash4Schedule_Intrinsic
+    : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty],
+                [IntrNoMem]>;
+
+  // SHA intrinsic taking 5 words of the hash (v4i32, i32) and 4 of the schedule
+  // (v4i32).
+  class Crypto_SHA_1Hash_Intrinsic
+    : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
+
+  // SHA intrinsic taking 8 words of the schedule
+  class Crypto_SHA_8Schedule_Intrinsic
+    : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
+
+  // SHA intrinsic taking 12 words of the schedule
+  class Crypto_SHA_12Schedule_Intrinsic
+    : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
+                [IntrNoMem]>;
+
+  // SHA intrinsic taking 8 words of the hash and 4 of the schedule.
+  class Crypto_SHA_8Hash4Schedule_Intrinsic
+    : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
+                [IntrNoMem]>;
+}
+
+// AES
+def int_aarch64_crypto_aese   : Crypto_AES_DataKey_Intrinsic;
+def int_aarch64_crypto_aesd   : Crypto_AES_DataKey_Intrinsic;
+def int_aarch64_crypto_aesmc  : Crypto_AES_Data_Intrinsic;
+def int_aarch64_crypto_aesimc : Crypto_AES_Data_Intrinsic;
+
+// SHA1
+def int_aarch64_crypto_sha1c  : Crypto_SHA_5Hash4Schedule_Intrinsic;
+def int_aarch64_crypto_sha1p  : Crypto_SHA_5Hash4Schedule_Intrinsic;
+def int_aarch64_crypto_sha1m  : Crypto_SHA_5Hash4Schedule_Intrinsic;
+def int_aarch64_crypto_sha1h  : Crypto_SHA_1Hash_Intrinsic;
+
+def int_aarch64_crypto_sha1su0 : Crypto_SHA_12Schedule_Intrinsic;
+def int_aarch64_crypto_sha1su1 : Crypto_SHA_8Schedule_Intrinsic;
+
+// SHA256
+def int_aarch64_crypto_sha256h   : Crypto_SHA_8Hash4Schedule_Intrinsic;
+def int_aarch64_crypto_sha256h2  : Crypto_SHA_8Hash4Schedule_Intrinsic;
+def int_aarch64_crypto_sha256su0 : Crypto_SHA_8Schedule_Intrinsic;
+def int_aarch64_crypto_sha256su1 : Crypto_SHA_12Schedule_Intrinsic;
+
+//===----------------------------------------------------------------------===//
+// CRC32
+
+let TargetPrefix = "aarch64" in {
+
+def int_aarch64_crc32b  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
+    [IntrNoMem]>;
+def int_aarch64_crc32cb : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
+    [IntrNoMem]>;
+def int_aarch64_crc32h  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
+    [IntrNoMem]>;
+def int_aarch64_crc32ch : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
+    [IntrNoMem]>;
+def int_aarch64_crc32w  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
+    [IntrNoMem]>;
+def int_aarch64_crc32cw : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
+    [IntrNoMem]>;
+def int_aarch64_crc32x  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i64_ty],
+    [IntrNoMem]>;
+def int_aarch64_crc32cx : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i64_ty],
+    [IntrNoMem]>;
+}
diff --git a/include/llvm/IR/IntrinsicsARM64.td b/include/llvm/IR/IntrinsicsARM64.td
deleted file mode 100644 (file)
index 146ea5d..0000000
+++ /dev/null
@@ -1,636 +0,0 @@
-//===- IntrinsicsARM64.td - Defines ARM64 intrinsics -------*- tablegen -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file defines all of the ARM64-specific intrinsics.
-//
-//===----------------------------------------------------------------------===//
-
-let TargetPrefix = "arm64" in {
-
-def int_arm64_ldxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty]>;
-def int_arm64_ldaxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty]>;
-def int_arm64_stxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty]>;
-def int_arm64_stlxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty]>;
-
-def int_arm64_ldxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty]>;
-def int_arm64_ldaxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty]>;
-def int_arm64_stxp : Intrinsic<[llvm_i32_ty],
-                               [llvm_i64_ty, llvm_i64_ty, llvm_ptr_ty]>;
-def int_arm64_stlxp : Intrinsic<[llvm_i32_ty],
-                                [llvm_i64_ty, llvm_i64_ty, llvm_ptr_ty]>;
-
-def int_arm64_clrex : Intrinsic<[]>;
-
-def int_arm64_sdiv : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
-                                LLVMMatchType<0>], [IntrNoMem]>;
-def int_arm64_udiv : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
-                                LLVMMatchType<0>], [IntrNoMem]>;
-}
-
-//===----------------------------------------------------------------------===//
-// Advanced SIMD (NEON)
-
-let TargetPrefix = "arm64" in {  // All intrinsics start with "llvm.arm64.".
-  class AdvSIMD_2Scalar_Float_Intrinsic
-    : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
-                [IntrNoMem]>;
-
-  class AdvSIMD_FPToIntRounding_Intrinsic
-    : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty], [IntrNoMem]>;
-
-  class AdvSIMD_1IntArg_Intrinsic
-    : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrNoMem]>;
-  class AdvSIMD_1FloatArg_Intrinsic
-    : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
-  class AdvSIMD_1VectorArg_Intrinsic
-    : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
-  class AdvSIMD_1VectorArg_Expand_Intrinsic
-    : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
-  class AdvSIMD_1VectorArg_Long_Intrinsic
-    : Intrinsic<[llvm_anyvector_ty], [LLVMTruncatedType<0>], [IntrNoMem]>;
-  class AdvSIMD_1IntArg_Narrow_Intrinsic
-    : Intrinsic<[llvm_anyint_ty], [llvm_anyint_ty], [IntrNoMem]>;
-  class AdvSIMD_1VectorArg_Narrow_Intrinsic
-    : Intrinsic<[llvm_anyint_ty], [LLVMExtendedType<0>], [IntrNoMem]>;
-  class AdvSIMD_1VectorArg_Int_Across_Intrinsic
-    : Intrinsic<[llvm_anyint_ty], [llvm_anyvector_ty], [IntrNoMem]>;
-  class AdvSIMD_1VectorArg_Float_Across_Intrinsic
-    : Intrinsic<[llvm_anyfloat_ty], [llvm_anyvector_ty], [IntrNoMem]>;
-
-  class AdvSIMD_2IntArg_Intrinsic
-    : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
-                [IntrNoMem]>;
-  class AdvSIMD_2FloatArg_Intrinsic
-    : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
-                [IntrNoMem]>;
-  class AdvSIMD_2VectorArg_Intrinsic
-    : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
-                [IntrNoMem]>;
-  class AdvSIMD_2VectorArg_Compare_Intrinsic
-    : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, LLVMMatchType<1>],
-                [IntrNoMem]>;
-  class AdvSIMD_2Arg_FloatCompare_Intrinsic
-    : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, LLVMMatchType<1>],
-                [IntrNoMem]>;
-  class AdvSIMD_2VectorArg_Long_Intrinsic
-    : Intrinsic<[llvm_anyvector_ty],
-                [LLVMTruncatedType<0>, LLVMTruncatedType<0>],
-                [IntrNoMem]>;
-  class AdvSIMD_2VectorArg_Wide_Intrinsic
-    : Intrinsic<[llvm_anyvector_ty],
-                [LLVMMatchType<0>, LLVMTruncatedType<0>],
-                [IntrNoMem]>;
-  class AdvSIMD_2VectorArg_Narrow_Intrinsic
-    : Intrinsic<[llvm_anyvector_ty],
-                [LLVMExtendedType<0>, LLVMExtendedType<0>],
-                [IntrNoMem]>;
-  class AdvSIMD_2Arg_Scalar_Narrow_Intrinsic
-    : Intrinsic<[llvm_anyint_ty],
-                [LLVMExtendedType<0>, llvm_i32_ty],
-                [IntrNoMem]>;
-  class AdvSIMD_2VectorArg_Scalar_Expand_BySize_Intrinsic
-    : Intrinsic<[llvm_anyvector_ty],
-                [llvm_anyvector_ty],
-                [IntrNoMem]>;
-  class AdvSIMD_2VectorArg_Scalar_Wide_BySize_Intrinsic
-    : Intrinsic<[llvm_anyvector_ty],
-                [LLVMTruncatedType<0>],
-                [IntrNoMem]>;
-  class AdvSIMD_2VectorArg_Scalar_Wide_Intrinsic
-    : Intrinsic<[llvm_anyvector_ty],
-                [LLVMTruncatedType<0>, llvm_i32_ty],
-                [IntrNoMem]>;
-  class AdvSIMD_2VectorArg_Tied_Narrow_Intrinsic
-    : Intrinsic<[llvm_anyvector_ty],
-                [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty],
-                [IntrNoMem]>;
-
-  class AdvSIMD_3VectorArg_Intrinsic
-      : Intrinsic<[llvm_anyvector_ty],
-               [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
-               [IntrNoMem]>;
-  class AdvSIMD_3VectorArg_Scalar_Intrinsic
-      : Intrinsic<[llvm_anyvector_ty],
-               [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty],
-               [IntrNoMem]>;
-  class AdvSIMD_3VectorArg_Tied_Narrow_Intrinsic
-      : Intrinsic<[llvm_anyvector_ty],
-               [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty,
-                LLVMMatchType<1>], [IntrNoMem]>;
-  class AdvSIMD_3VectorArg_Scalar_Tied_Narrow_Intrinsic
-    : Intrinsic<[llvm_anyvector_ty],
-                [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty, llvm_i32_ty],
-                [IntrNoMem]>;
-  class AdvSIMD_CvtFxToFP_Intrinsic
-    : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty],
-                [IntrNoMem]>;
-  class AdvSIMD_CvtFPToFx_Intrinsic
-    : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty],
-                [IntrNoMem]>;
-}
-
-// Arithmetic ops
-
-let Properties = [IntrNoMem] in {
-  // Vector Add Across Lanes
-  def int_arm64_neon_saddv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
-  def int_arm64_neon_uaddv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
-  def int_arm64_neon_faddv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
-
-  // Vector Long Add Across Lanes
-  def int_arm64_neon_saddlv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
-  def int_arm64_neon_uaddlv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
-
-  // Vector Halving Add
-  def int_arm64_neon_shadd : AdvSIMD_2VectorArg_Intrinsic;
-  def int_arm64_neon_uhadd : AdvSIMD_2VectorArg_Intrinsic;
-
-  // Vector Rounding Halving Add
-  def int_arm64_neon_srhadd : AdvSIMD_2VectorArg_Intrinsic;
-  def int_arm64_neon_urhadd : AdvSIMD_2VectorArg_Intrinsic;
-
-  // Vector Saturating Add
-  def int_arm64_neon_sqadd : AdvSIMD_2IntArg_Intrinsic;
-  def int_arm64_neon_suqadd : AdvSIMD_2IntArg_Intrinsic;
-  def int_arm64_neon_usqadd : AdvSIMD_2IntArg_Intrinsic;
-  def int_arm64_neon_uqadd : AdvSIMD_2IntArg_Intrinsic;
-
-  // Vector Add High-Half
-  // FIXME: this is a legacy intrinsic for aarch64_simd.h. Remove it when that
-  // header is no longer supported.
-  def int_arm64_neon_addhn : AdvSIMD_2VectorArg_Narrow_Intrinsic;
-
-  // Vector Rounding Add High-Half
-  def int_arm64_neon_raddhn : AdvSIMD_2VectorArg_Narrow_Intrinsic;
-
-  // Vector Saturating Doubling Multiply High
-  def int_arm64_neon_sqdmulh : AdvSIMD_2IntArg_Intrinsic;
-
-  // Vector Saturating Rounding Doubling Multiply High
-  def int_arm64_neon_sqrdmulh : AdvSIMD_2IntArg_Intrinsic;
-
-  // Vector Polynominal Multiply
-  def int_arm64_neon_pmul : AdvSIMD_2VectorArg_Intrinsic;
-
-  // Vector Long Multiply
-  def int_arm64_neon_smull : AdvSIMD_2VectorArg_Long_Intrinsic;
-  def int_arm64_neon_umull : AdvSIMD_2VectorArg_Long_Intrinsic;
-  def int_arm64_neon_pmull : AdvSIMD_2VectorArg_Long_Intrinsic;
-
-  // 64-bit polynomial multiply really returns an i128, which is not legal. Fake
-  // it with a v16i8.
-  def int_arm64_neon_pmull64 :
-        Intrinsic<[llvm_v16i8_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
-
-  // Vector Extending Multiply
-  def int_arm64_neon_fmulx : AdvSIMD_2FloatArg_Intrinsic {
-    let Properties = [IntrNoMem, Commutative];
-  }
-
-  // Vector Saturating Doubling Long Multiply
-  def int_arm64_neon_sqdmull : AdvSIMD_2VectorArg_Long_Intrinsic;
-  def int_arm64_neon_sqdmulls_scalar
-    : Intrinsic<[llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
-
-  // Vector Halving Subtract
-  def int_arm64_neon_shsub : AdvSIMD_2VectorArg_Intrinsic;
-  def int_arm64_neon_uhsub : AdvSIMD_2VectorArg_Intrinsic;
-
-  // Vector Saturating Subtract
-  def int_arm64_neon_sqsub : AdvSIMD_2IntArg_Intrinsic;
-  def int_arm64_neon_uqsub : AdvSIMD_2IntArg_Intrinsic;
-
-  // Vector Subtract High-Half
-  // FIXME: this is a legacy intrinsic for aarch64_simd.h. Remove it when that
-  // header is no longer supported.
-  def int_arm64_neon_subhn : AdvSIMD_2VectorArg_Narrow_Intrinsic;
-
-  // Vector Rounding Subtract High-Half
-  def int_arm64_neon_rsubhn : AdvSIMD_2VectorArg_Narrow_Intrinsic;
-
-  // Vector Compare Absolute Greater-than-or-equal
-  def int_arm64_neon_facge : AdvSIMD_2Arg_FloatCompare_Intrinsic;
-
-  // Vector Compare Absolute Greater-than
-  def int_arm64_neon_facgt : AdvSIMD_2Arg_FloatCompare_Intrinsic;
-
-  // Vector Absolute Difference
-  def int_arm64_neon_sabd : AdvSIMD_2VectorArg_Intrinsic;
-  def int_arm64_neon_uabd : AdvSIMD_2VectorArg_Intrinsic;
-  def int_arm64_neon_fabd : AdvSIMD_2VectorArg_Intrinsic;
-
-  // Scalar Absolute Difference
-  def int_arm64_sisd_fabd : AdvSIMD_2Scalar_Float_Intrinsic;
-
-  // Vector Max
-  def int_arm64_neon_smax : AdvSIMD_2VectorArg_Intrinsic;
-  def int_arm64_neon_umax : AdvSIMD_2VectorArg_Intrinsic;
-  def int_arm64_neon_fmax : AdvSIMD_2VectorArg_Intrinsic;
-  def int_arm64_neon_fmaxnmp : AdvSIMD_2VectorArg_Intrinsic;
-
-  // Vector Max Across Lanes
-  def int_arm64_neon_smaxv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
-  def int_arm64_neon_umaxv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
-  def int_arm64_neon_fmaxv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
-  def int_arm64_neon_fmaxnmv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
-
-  // Vector Min
-  def int_arm64_neon_smin : AdvSIMD_2VectorArg_Intrinsic;
-  def int_arm64_neon_umin : AdvSIMD_2VectorArg_Intrinsic;
-  def int_arm64_neon_fmin : AdvSIMD_2VectorArg_Intrinsic;
-  def int_arm64_neon_fminnmp : AdvSIMD_2VectorArg_Intrinsic;
-
-  // Vector Min/Max Number
-  def int_arm64_neon_fminnm : AdvSIMD_2FloatArg_Intrinsic;
-  def int_arm64_neon_fmaxnm : AdvSIMD_2FloatArg_Intrinsic;
-
-  // Vector Min Across Lanes
-  def int_arm64_neon_sminv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
-  def int_arm64_neon_uminv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
-  def int_arm64_neon_fminv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
-  def int_arm64_neon_fminnmv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
-
-  // Pairwise Add
-  def int_arm64_neon_addp : AdvSIMD_2VectorArg_Intrinsic;
-
-  // Long Pairwise Add
-  // FIXME: In theory, we shouldn't need intrinsics for saddlp or
-  // uaddlp, but tblgen's type inference currently can't handle the
-  // pattern fragments this ends up generating.
-  def int_arm64_neon_saddlp : AdvSIMD_1VectorArg_Expand_Intrinsic;
-  def int_arm64_neon_uaddlp : AdvSIMD_1VectorArg_Expand_Intrinsic;
-
-  // Folding Maximum
-  def int_arm64_neon_smaxp : AdvSIMD_2VectorArg_Intrinsic;
-  def int_arm64_neon_umaxp : AdvSIMD_2VectorArg_Intrinsic;
-  def int_arm64_neon_fmaxp : AdvSIMD_2VectorArg_Intrinsic;
-
-  // Folding Minimum
-  def int_arm64_neon_sminp : AdvSIMD_2VectorArg_Intrinsic;
-  def int_arm64_neon_uminp : AdvSIMD_2VectorArg_Intrinsic;
-  def int_arm64_neon_fminp : AdvSIMD_2VectorArg_Intrinsic;
-
-  // Reciprocal Estimate/Step
-  def int_arm64_neon_frecps : AdvSIMD_2FloatArg_Intrinsic;
-  def int_arm64_neon_frsqrts : AdvSIMD_2FloatArg_Intrinsic;
-
-  // Reciprocal Exponent
-  def int_arm64_neon_frecpx : AdvSIMD_1FloatArg_Intrinsic;
-
-  // Vector Saturating Shift Left
-  def int_arm64_neon_sqshl : AdvSIMD_2IntArg_Intrinsic;
-  def int_arm64_neon_uqshl : AdvSIMD_2IntArg_Intrinsic;
-
-  // Vector Rounding Shift Left
-  def int_arm64_neon_srshl : AdvSIMD_2IntArg_Intrinsic;
-  def int_arm64_neon_urshl : AdvSIMD_2IntArg_Intrinsic;
-
-  // Vector Saturating Rounding Shift Left
-  def int_arm64_neon_sqrshl : AdvSIMD_2IntArg_Intrinsic;
-  def int_arm64_neon_uqrshl : AdvSIMD_2IntArg_Intrinsic;
-
-  // Vector Signed->Unsigned Shift Left by Constant
-  def int_arm64_neon_sqshlu : AdvSIMD_2IntArg_Intrinsic;
-
-  // Vector Signed->Unsigned Narrowing Saturating Shift Right by Constant
-  def int_arm64_neon_sqshrun : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
-
-  // Vector Signed->Unsigned Rounding Narrowing Saturating Shift Right by Const
-  def int_arm64_neon_sqrshrun : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
-
-  // Vector Narrowing Shift Right by Constant
-  def int_arm64_neon_sqshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
-  def int_arm64_neon_uqshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
-
-  // Vector Rounding Narrowing Shift Right by Constant
-  def int_arm64_neon_rshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
-
-  // Vector Rounding Narrowing Saturating Shift Right by Constant
-  def int_arm64_neon_sqrshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
-  def int_arm64_neon_uqrshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
-
-  // Vector Shift Left
-  def int_arm64_neon_sshl : AdvSIMD_2IntArg_Intrinsic;
-  def int_arm64_neon_ushl : AdvSIMD_2IntArg_Intrinsic;
-
-  // Vector Widening Shift Left by Constant
-  def int_arm64_neon_shll : AdvSIMD_2VectorArg_Scalar_Wide_BySize_Intrinsic;
-  def int_arm64_neon_sshll : AdvSIMD_2VectorArg_Scalar_Wide_Intrinsic;
-  def int_arm64_neon_ushll : AdvSIMD_2VectorArg_Scalar_Wide_Intrinsic;
-
-  // Vector Shift Right by Constant and Insert
-  def int_arm64_neon_vsri : AdvSIMD_3VectorArg_Scalar_Intrinsic;
-
-  // Vector Shift Left by Constant and Insert
-  def int_arm64_neon_vsli : AdvSIMD_3VectorArg_Scalar_Intrinsic;
-
-  // Vector Saturating Narrow
-  def int_arm64_neon_scalar_sqxtn: AdvSIMD_1IntArg_Narrow_Intrinsic;
-  def int_arm64_neon_scalar_uqxtn : AdvSIMD_1IntArg_Narrow_Intrinsic;
-  def int_arm64_neon_sqxtn : AdvSIMD_1VectorArg_Narrow_Intrinsic;
-  def int_arm64_neon_uqxtn : AdvSIMD_1VectorArg_Narrow_Intrinsic;
-
-  // Vector Saturating Extract and Unsigned Narrow
-  def int_arm64_neon_scalar_sqxtun : AdvSIMD_1IntArg_Narrow_Intrinsic;
-  def int_arm64_neon_sqxtun : AdvSIMD_1VectorArg_Narrow_Intrinsic;
-
-  // Vector Absolute Value
-  def int_arm64_neon_abs : AdvSIMD_1IntArg_Intrinsic;
-
-  // Vector Saturating Absolute Value
-  def int_arm64_neon_sqabs : AdvSIMD_1IntArg_Intrinsic;
-
-  // Vector Saturating Negation
-  def int_arm64_neon_sqneg : AdvSIMD_1IntArg_Intrinsic;
-
-  // Vector Count Leading Sign Bits
-  def int_arm64_neon_cls : AdvSIMD_1VectorArg_Intrinsic;
-
-  // Vector Reciprocal Estimate
-  def int_arm64_neon_urecpe : AdvSIMD_1VectorArg_Intrinsic;
-  def int_arm64_neon_frecpe : AdvSIMD_1FloatArg_Intrinsic;
-
-  // Vector Square Root Estimate
-  def int_arm64_neon_ursqrte : AdvSIMD_1VectorArg_Intrinsic;
-  def int_arm64_neon_frsqrte : AdvSIMD_1FloatArg_Intrinsic;
-
-  // Vector Bitwise Reverse
-  def int_arm64_neon_rbit : AdvSIMD_1VectorArg_Intrinsic;
-
-  // Vector Conversions Between Half-Precision and Single-Precision.
-  def int_arm64_neon_vcvtfp2hf
-    : Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>;
-  def int_arm64_neon_vcvthf2fp
-    : Intrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>;
-
-  // Vector Conversions Between Floating-point and Fixed-point.
-  def int_arm64_neon_vcvtfp2fxs : AdvSIMD_CvtFPToFx_Intrinsic;
-  def int_arm64_neon_vcvtfp2fxu : AdvSIMD_CvtFPToFx_Intrinsic;
-  def int_arm64_neon_vcvtfxs2fp : AdvSIMD_CvtFxToFP_Intrinsic;
-  def int_arm64_neon_vcvtfxu2fp : AdvSIMD_CvtFxToFP_Intrinsic;
-
-  // Vector FP->Int Conversions
-  def int_arm64_neon_fcvtas : AdvSIMD_FPToIntRounding_Intrinsic;
-  def int_arm64_neon_fcvtau : AdvSIMD_FPToIntRounding_Intrinsic;
-  def int_arm64_neon_fcvtms : AdvSIMD_FPToIntRounding_Intrinsic;
-  def int_arm64_neon_fcvtmu : AdvSIMD_FPToIntRounding_Intrinsic;
-  def int_arm64_neon_fcvtns : AdvSIMD_FPToIntRounding_Intrinsic;
-  def int_arm64_neon_fcvtnu : AdvSIMD_FPToIntRounding_Intrinsic;
-  def int_arm64_neon_fcvtps : AdvSIMD_FPToIntRounding_Intrinsic;
-  def int_arm64_neon_fcvtpu : AdvSIMD_FPToIntRounding_Intrinsic;
-  def int_arm64_neon_fcvtzs : AdvSIMD_FPToIntRounding_Intrinsic;
-  def int_arm64_neon_fcvtzu : AdvSIMD_FPToIntRounding_Intrinsic;
-
-  // Vector FP Rounding: only ties to even is unrepresented by a normal
-  // intrinsic.
-  def int_arm64_neon_frintn : AdvSIMD_1FloatArg_Intrinsic;
-
-  // Scalar FP->Int conversions
-
-  // Vector FP Inexact Narrowing
-  def int_arm64_neon_fcvtxn : AdvSIMD_1VectorArg_Expand_Intrinsic;
-
-  // Scalar FP Inexact Narrowing
-  def int_arm64_sisd_fcvtxn : Intrinsic<[llvm_float_ty], [llvm_double_ty],
-                                        [IntrNoMem]>;
-}
-
-let TargetPrefix = "arm64" in {  // All intrinsics start with "llvm.arm64.".
-  class AdvSIMD_2Vector2Index_Intrinsic
-    : Intrinsic<[llvm_anyvector_ty],
-                [llvm_anyvector_ty, llvm_i64_ty, LLVMMatchType<0>, llvm_i64_ty],
-                [IntrNoMem]>;
-}
-
-// Vector element to element moves
-def int_arm64_neon_vcopy_lane: AdvSIMD_2Vector2Index_Intrinsic;
-
-let TargetPrefix = "arm64" in {  // All intrinsics start with "llvm.arm64.".
-  class AdvSIMD_1Vec_Load_Intrinsic
-      : Intrinsic<[llvm_anyvector_ty], [LLVMAnyPointerType<LLVMMatchType<0>>],
-                  [IntrReadArgMem]>;
-  class AdvSIMD_1Vec_Store_Lane_Intrinsic
-    : Intrinsic<[], [llvm_anyvector_ty, llvm_i64_ty, llvm_anyptr_ty],
-                [IntrReadWriteArgMem, NoCapture<2>]>;
-
-  class AdvSIMD_2Vec_Load_Intrinsic
-    : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
-                [LLVMAnyPointerType<LLVMMatchType<0>>],
-                [IntrReadArgMem]>;
-  class AdvSIMD_2Vec_Load_Lane_Intrinsic
-    : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
-                [LLVMMatchType<0>, LLVMMatchType<0>,
-                 llvm_i64_ty, llvm_anyptr_ty],
-                [IntrReadArgMem]>;
-  class AdvSIMD_2Vec_Store_Intrinsic
-    : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
-                     LLVMAnyPointerType<LLVMMatchType<0>>],
-                [IntrReadWriteArgMem, NoCapture<2>]>;
-  class AdvSIMD_2Vec_Store_Lane_Intrinsic
-    : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
-                 llvm_i64_ty, llvm_anyptr_ty],
-                [IntrReadWriteArgMem, NoCapture<3>]>;
-
-  class AdvSIMD_3Vec_Load_Intrinsic
-    : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>],
-                [LLVMAnyPointerType<LLVMMatchType<0>>],
-                [IntrReadArgMem]>;
-  class AdvSIMD_3Vec_Load_Lane_Intrinsic
-    : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>],
-                [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>,
-                 llvm_i64_ty, llvm_anyptr_ty],
-                [IntrReadArgMem]>;
-  class AdvSIMD_3Vec_Store_Intrinsic
-    : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
-                     LLVMMatchType<0>, LLVMAnyPointerType<LLVMMatchType<0>>],
-                [IntrReadWriteArgMem, NoCapture<3>]>;
-  class AdvSIMD_3Vec_Store_Lane_Intrinsic
-    : Intrinsic<[], [llvm_anyvector_ty,
-                 LLVMMatchType<0>, LLVMMatchType<0>,
-                 llvm_i64_ty, llvm_anyptr_ty],
-                [IntrReadWriteArgMem, NoCapture<4>]>;
-
-  class AdvSIMD_4Vec_Load_Intrinsic
-    : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
-                 LLVMMatchType<0>, LLVMMatchType<0>],
-                [LLVMAnyPointerType<LLVMMatchType<0>>],
-                [IntrReadArgMem]>;
-  class AdvSIMD_4Vec_Load_Lane_Intrinsic
-    : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
-                 LLVMMatchType<0>, LLVMMatchType<0>],
-                [LLVMMatchType<0>, LLVMMatchType<0>,
-                 LLVMMatchType<0>, LLVMMatchType<0>,
-                 llvm_i64_ty, llvm_anyptr_ty],
-                [IntrReadArgMem]>;
-  class AdvSIMD_4Vec_Store_Intrinsic
-    : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
-                 LLVMMatchType<0>, LLVMMatchType<0>,
-                 LLVMAnyPointerType<LLVMMatchType<0>>],
-                [IntrReadWriteArgMem, NoCapture<4>]>;
-  class AdvSIMD_4Vec_Store_Lane_Intrinsic
-    : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
-                 LLVMMatchType<0>, LLVMMatchType<0>,
-                 llvm_i64_ty, llvm_anyptr_ty],
-                [IntrReadWriteArgMem, NoCapture<5>]>;
-}
-
-// Memory ops
-
-def int_arm64_neon_ld1x2 : AdvSIMD_2Vec_Load_Intrinsic;
-def int_arm64_neon_ld1x3 : AdvSIMD_3Vec_Load_Intrinsic;
-def int_arm64_neon_ld1x4 : AdvSIMD_4Vec_Load_Intrinsic;
-
-def int_arm64_neon_st1x2 : AdvSIMD_2Vec_Store_Intrinsic;
-def int_arm64_neon_st1x3 : AdvSIMD_3Vec_Store_Intrinsic;
-def int_arm64_neon_st1x4 : AdvSIMD_4Vec_Store_Intrinsic;
-
-def int_arm64_neon_ld2 : AdvSIMD_2Vec_Load_Intrinsic;
-def int_arm64_neon_ld3 : AdvSIMD_3Vec_Load_Intrinsic;
-def int_arm64_neon_ld4 : AdvSIMD_4Vec_Load_Intrinsic;
-
-def int_arm64_neon_ld2lane : AdvSIMD_2Vec_Load_Lane_Intrinsic;
-def int_arm64_neon_ld3lane : AdvSIMD_3Vec_Load_Lane_Intrinsic;
-def int_arm64_neon_ld4lane : AdvSIMD_4Vec_Load_Lane_Intrinsic;
-
-def int_arm64_neon_ld2r : AdvSIMD_2Vec_Load_Intrinsic;
-def int_arm64_neon_ld3r : AdvSIMD_3Vec_Load_Intrinsic;
-def int_arm64_neon_ld4r : AdvSIMD_4Vec_Load_Intrinsic;
-
-def int_arm64_neon_st2  : AdvSIMD_2Vec_Store_Intrinsic;
-def int_arm64_neon_st3  : AdvSIMD_3Vec_Store_Intrinsic;
-def int_arm64_neon_st4  : AdvSIMD_4Vec_Store_Intrinsic;
-
-def int_arm64_neon_st2lane  : AdvSIMD_2Vec_Store_Lane_Intrinsic;
-def int_arm64_neon_st3lane  : AdvSIMD_3Vec_Store_Lane_Intrinsic;
-def int_arm64_neon_st4lane  : AdvSIMD_4Vec_Store_Lane_Intrinsic;
-
-let TargetPrefix = "arm64" in {  // All intrinsics start with "llvm.arm64.".
-  class AdvSIMD_Tbl1_Intrinsic
-    : Intrinsic<[llvm_anyvector_ty], [llvm_v16i8_ty, LLVMMatchType<0>],
-                [IntrNoMem]>;
-  class AdvSIMD_Tbl2_Intrinsic
-    : Intrinsic<[llvm_anyvector_ty],
-                [llvm_v16i8_ty, llvm_v16i8_ty, LLVMMatchType<0>], [IntrNoMem]>;
-  class AdvSIMD_Tbl3_Intrinsic
-    : Intrinsic<[llvm_anyvector_ty],
-                [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty,
-                 LLVMMatchType<0>],
-                [IntrNoMem]>;
-  class AdvSIMD_Tbl4_Intrinsic
-    : Intrinsic<[llvm_anyvector_ty],
-                [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty,
-                 LLVMMatchType<0>],
-                [IntrNoMem]>;
-
-  class AdvSIMD_Tbx1_Intrinsic
-    : Intrinsic<[llvm_anyvector_ty],
-                [LLVMMatchType<0>, llvm_v16i8_ty, LLVMMatchType<0>],
-                [IntrNoMem]>;
-  class AdvSIMD_Tbx2_Intrinsic
-    : Intrinsic<[llvm_anyvector_ty],
-                [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty,
-                 LLVMMatchType<0>],
-                [IntrNoMem]>;
-  class AdvSIMD_Tbx3_Intrinsic
-    : Intrinsic<[llvm_anyvector_ty],
-                [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty,
-                 llvm_v16i8_ty, LLVMMatchType<0>],
-                [IntrNoMem]>;
-  class AdvSIMD_Tbx4_Intrinsic
-    : Intrinsic<[llvm_anyvector_ty],
-                [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty,
-                 llvm_v16i8_ty, llvm_v16i8_ty, LLVMMatchType<0>],
-                [IntrNoMem]>;
-}
-def int_arm64_neon_tbl1 : AdvSIMD_Tbl1_Intrinsic;
-def int_arm64_neon_tbl2 : AdvSIMD_Tbl2_Intrinsic;
-def int_arm64_neon_tbl3 : AdvSIMD_Tbl3_Intrinsic;
-def int_arm64_neon_tbl4 : AdvSIMD_Tbl4_Intrinsic;
-
-def int_arm64_neon_tbx1 : AdvSIMD_Tbx1_Intrinsic;
-def int_arm64_neon_tbx2 : AdvSIMD_Tbx2_Intrinsic;
-def int_arm64_neon_tbx3 : AdvSIMD_Tbx3_Intrinsic;
-def int_arm64_neon_tbx4 : AdvSIMD_Tbx4_Intrinsic;
-
-let TargetPrefix = "arm64" in {
-  class Crypto_AES_DataKey_Intrinsic
-    : Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
-
-  class Crypto_AES_Data_Intrinsic
-    : Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty], [IntrNoMem]>;
-
-  // SHA intrinsic taking 5 words of the hash (v4i32, i32) and 4 of the schedule
-  // (v4i32).
-  class Crypto_SHA_5Hash4Schedule_Intrinsic
-    : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty],
-                [IntrNoMem]>;
-
-  // SHA intrinsic taking 5 words of the hash (v4i32, i32) and 4 of the schedule
-  // (v4i32).
-  class Crypto_SHA_1Hash_Intrinsic
-    : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
-
-  // SHA intrinsic taking 8 words of the schedule
-  class Crypto_SHA_8Schedule_Intrinsic
-    : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
-
-  // SHA intrinsic taking 12 words of the schedule
-  class Crypto_SHA_12Schedule_Intrinsic
-    : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
-                [IntrNoMem]>;
-
-  // SHA intrinsic taking 8 words of the hash and 4 of the schedule.
-  class Crypto_SHA_8Hash4Schedule_Intrinsic
-    : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
-                [IntrNoMem]>;
-}
-
-// AES
-def int_arm64_crypto_aese   : Crypto_AES_DataKey_Intrinsic;
-def int_arm64_crypto_aesd   : Crypto_AES_DataKey_Intrinsic;
-def int_arm64_crypto_aesmc  : Crypto_AES_Data_Intrinsic;
-def int_arm64_crypto_aesimc : Crypto_AES_Data_Intrinsic;
-
-// SHA1
-def int_arm64_crypto_sha1c  : Crypto_SHA_5Hash4Schedule_Intrinsic;
-def int_arm64_crypto_sha1p  : Crypto_SHA_5Hash4Schedule_Intrinsic;
-def int_arm64_crypto_sha1m  : Crypto_SHA_5Hash4Schedule_Intrinsic;
-def int_arm64_crypto_sha1h  : Crypto_SHA_1Hash_Intrinsic;
-
-def int_arm64_crypto_sha1su0 : Crypto_SHA_12Schedule_Intrinsic;
-def int_arm64_crypto_sha1su1 : Crypto_SHA_8Schedule_Intrinsic;
-
-// SHA256
-def int_arm64_crypto_sha256h   : Crypto_SHA_8Hash4Schedule_Intrinsic;
-def int_arm64_crypto_sha256h2  : Crypto_SHA_8Hash4Schedule_Intrinsic;
-def int_arm64_crypto_sha256su0 : Crypto_SHA_8Schedule_Intrinsic;
-def int_arm64_crypto_sha256su1 : Crypto_SHA_12Schedule_Intrinsic;
-
-//===----------------------------------------------------------------------===//
-// CRC32
-
-let TargetPrefix = "arm64" in {
-
-def int_arm64_crc32b  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
-    [IntrNoMem]>;
-def int_arm64_crc32cb : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
-    [IntrNoMem]>;
-def int_arm64_crc32h  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
-    [IntrNoMem]>;
-def int_arm64_crc32ch : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
-    [IntrNoMem]>;
-def int_arm64_crc32w  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
-    [IntrNoMem]>;
-def int_arm64_crc32cw : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
-    [IntrNoMem]>;
-def int_arm64_crc32x  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i64_ty],
-    [IntrNoMem]>;
-def int_arm64_crc32cx : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i64_ty],
-    [IntrNoMem]>;
-}
index a70b03d..2b425fb 100644 (file)
@@ -168,8 +168,9 @@ void RuntimeDyldMachO::resolveRelocation(const RelocationEntry &RE,
   case Triple::thumb:
     resolveARMRelocation(RE, Value);
     break;
+  case Triple::aarch64:
   case Triple::arm64:
-    resolveARM64Relocation(RE, Value);
+    resolveAArch64Relocation(RE, Value);
     break;
   }
 }
@@ -289,8 +290,8 @@ bool RuntimeDyldMachO::resolveARMRelocation(const RelocationEntry &RE,
   return false;
 }
 
-bool RuntimeDyldMachO::resolveARM64Relocation(const RelocationEntry &RE,
-                                              uint64_t Value) {
+bool RuntimeDyldMachO::resolveAArch64Relocation(const RelocationEntry &RE,
+                                                uint64_t Value) {
   const SectionEntry &Section = Sections[RE.SectionID];
   uint8_t* LocalAddress = Section.Address + RE.Offset;
 
index 08573ee..060eb8c 100644 (file)
@@ -41,7 +41,7 @@ private:
   bool resolveI386Relocation(const RelocationEntry &RE, uint64_t Value);
   bool resolveX86_64Relocation(const RelocationEntry &RE, uint64_t Value);
   bool resolveARMRelocation(const RelocationEntry &RE, uint64_t Value);
-  bool resolveARM64Relocation(const RelocationEntry &RE, uint64_t Value);
+  bool resolveAArch64Relocation(const RelocationEntry &RE, uint64_t Value);
 
   // Populate stubs in __jump_table section.
   void populateJumpTable(MachOObjectFile &Obj, const SectionRef &JTSection,
index 028c191..99236bd 100644 (file)
@@ -312,7 +312,8 @@ bool LTOCodeGenerator::determineTarget(std::string &errMsg) {
       MCpu = "core2";
     else if (Triple.getArch() == llvm::Triple::x86)
       MCpu = "yonah";
-    else if (Triple.getArch() == llvm::Triple::arm64)
+    else if (Triple.getArch() == llvm::Triple::arm64 ||
+             Triple.getArch() == llvm::Triple::aarch64)
       MCpu = "cyclone";
   }
 
index 255951a..d117514 100644 (file)
@@ -168,7 +168,8 @@ LTOModule *LTOModule::makeLTOModule(MemoryBuffer *buffer,
       CPU = "core2";
     else if (Triple.getArch() == llvm::Triple::x86)
       CPU = "yonah";
-    else if (Triple.getArch() == llvm::Triple::arm64)
+    else if (Triple.getArch() == llvm::Triple::arm64 ||
+             Triple.getArch() == llvm::Triple::aarch64)
       CPU = "cyclone";
   }
 
index bb13279..9d413af 100644 (file)
@@ -23,7 +23,8 @@ void MCObjectFileInfo::InitMachOMCObjectFileInfo(Triple T) {
   IsFunctionEHFrameSymbolPrivate = false;
   SupportsWeakOmittedEHFrame = false;
 
-  if (T.isOSDarwin() && T.getArch() == Triple::arm64)
+  if (T.isOSDarwin() &&
+      (T.getArch() == Triple::arm64 || T.getArch() == Triple::aarch64))
     SupportsCompactUnwindWithoutEHFrame = true;
 
   PersonalityEncoding = dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel
@@ -151,7 +152,8 @@ void MCObjectFileInfo::InitMachOMCObjectFileInfo(Triple T) {
   COFFDebugSymbolsSection = nullptr;
 
   if ((T.isMacOSX() && !T.isMacOSXVersionLT(10, 6)) ||
-      (T.isOSDarwin() && T.getArch() == Triple::arm64)) {
+      (T.isOSDarwin() &&
+       (T.getArch() == Triple::arm64 || T.getArch() == Triple::aarch64))) {
     CompactUnwindSection =
       Ctx->getMachOSection("__LD", "__compact_unwind",
                            MachO::S_ATTR_DEBUG,
@@ -159,7 +161,7 @@ void MCObjectFileInfo::InitMachOMCObjectFileInfo(Triple T) {
 
     if (T.getArch() == Triple::x86_64 || T.getArch() == Triple::x86)
       CompactUnwindDwarfEHFrameOnly = 0x04000000;
-    else if (T.getArch() == Triple::arm64)
+    else if (T.getArch() == Triple::arm64 || T.getArch() == Triple::aarch64)
       CompactUnwindDwarfEHFrameOnly = 0x03000000;
   }
 
@@ -785,7 +787,7 @@ void MCObjectFileInfo::InitMCObjectFileInfo(StringRef TT, Reloc::Model relocm,
   // cellspu-apple-darwin. Perhaps we should fix in Triple?
   if ((Arch == Triple::x86 || Arch == Triple::x86_64 ||
        Arch == Triple::arm || Arch == Triple::thumb ||
-       Arch == Triple::arm64 ||
+       Arch == Triple::arm64 || Arch == Triple::aarch64 ||
        Arch == Triple::ppc || Arch == Triple::ppc64 ||
        Arch == Triple::UnknownArch) &&
       (T.isOSDarwin() || T.isOSBinFormatMachO())) {
diff --git a/lib/Target/AArch64/AArch64.h b/lib/Target/AArch64/AArch64.h
new file mode 100644 (file)
index 0000000..1c022aa
--- /dev/null
@@ -0,0 +1,49 @@
+//==-- AArch64.h - Top-level interface for AArch64  --------------*- C++ -*-==//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the entry points for global functions defined in the LLVM
+// AArch64 back-end.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef TARGET_AArch64_H
+#define TARGET_AArch64_H
+
+#include "Utils/AArch64BaseInfo.h"
+#include "MCTargetDesc/AArch64MCTargetDesc.h"
+#include "llvm/Target/TargetMachine.h"
+#include "llvm/Support/DataTypes.h"
+
+namespace llvm {
+
+class AArch64TargetMachine;
+class FunctionPass;
+class MachineFunctionPass;
+
+FunctionPass *createAArch64DeadRegisterDefinitions();
+FunctionPass *createAArch64ConditionalCompares();
+FunctionPass *createAArch64AdvSIMDScalar();
+FunctionPass *createAArch64BranchRelaxation();
+FunctionPass *createAArch64ISelDag(AArch64TargetMachine &TM,
+                                 CodeGenOpt::Level OptLevel);
+FunctionPass *createAArch64StorePairSuppressPass();
+FunctionPass *createAArch64ExpandPseudoPass();
+FunctionPass *createAArch64LoadStoreOptimizationPass();
+ModulePass *createAArch64PromoteConstantPass();
+FunctionPass *createAArch64AddressTypePromotionPass();
+/// \brief Creates an ARM-specific Target Transformation Info pass.
+ImmutablePass *
+createAArch64TargetTransformInfoPass(const AArch64TargetMachine *TM);
+
+FunctionPass *createAArch64CleanupLocalDynamicTLSPass();
+
+FunctionPass *createAArch64CollectLOHPass();
+} // end namespace llvm
+
+#endif
diff --git a/lib/Target/AArch64/AArch64.td b/lib/Target/AArch64/AArch64.td
new file mode 100644 (file)
index 0000000..1ad5ac8
--- /dev/null
@@ -0,0 +1,134 @@
+//=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Target-independent interfaces which we are implementing
+//===----------------------------------------------------------------------===//
+
+include "llvm/Target/Target.td"
+
+//===----------------------------------------------------------------------===//
+// AArch64 Subtarget features.
+//
+
+def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
+                                       "Enable ARMv8 FP">;
+
+def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
+  "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
+
+def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
+  "Enable cryptographic instructions">;
+
+def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
+  "Enable ARMv8 CRC-32 checksum instructions">;
+
+/// Cyclone has register move instructions which are "free".
+def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
+                                        "Has zero-cycle register moves">;
+
+/// Cyclone has instructions which zero registers for "free".
+def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
+                                        "Has zero-cycle zeroing instructions">;
+
+//===----------------------------------------------------------------------===//
+// Register File Description
+//===----------------------------------------------------------------------===//
+
+include "AArch64RegisterInfo.td"
+include "AArch64CallingConvention.td"
+
+//===----------------------------------------------------------------------===//
+// Instruction Descriptions
+//===----------------------------------------------------------------------===//
+
+include "AArch64Schedule.td"
+include "AArch64InstrInfo.td"
+
+def AArch64InstrInfo : InstrInfo;
+
+//===----------------------------------------------------------------------===//
+// AArch64 Processors supported.
+//
+include "AArch64SchedA53.td"
+include "AArch64SchedCyclone.td"
+
+def ProcA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
+                                   "Cortex-A53 ARM processors",
+                                   [FeatureFPARMv8,
+                                   FeatureNEON,
+                                   FeatureCrypto,
+                                   FeatureCRC]>;
+
+def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
+                                   "Cortex-A57 ARM processors",
+                                   [FeatureFPARMv8,
+                                   FeatureNEON,
+                                   FeatureCrypto,
+                                   FeatureCRC]>;
+
+def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
+                                   "Cyclone",
+                                   [FeatureFPARMv8,
+                                   FeatureNEON,
+                                   FeatureCrypto,
+                                   FeatureCRC,
+                                   FeatureZCRegMove, FeatureZCZeroing]>;
+
+def : ProcessorModel<"generic", NoSchedModel, [FeatureFPARMv8,
+                                              FeatureNEON,
+                                              FeatureCRC]>;
+
+def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
+def : ProcessorModel<"cortex-a57", NoSchedModel, [ProcA57]>;
+def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
+
+//===----------------------------------------------------------------------===//
+// Assembly parser
+//===----------------------------------------------------------------------===//
+
+def GenericAsmParserVariant : AsmParserVariant {
+  int Variant = 0;
+  string Name = "generic";
+}
+
+def AppleAsmParserVariant : AsmParserVariant {
+  int Variant = 1;
+  string Name = "apple-neon";
+}
+
+//===----------------------------------------------------------------------===//
+// Assembly printer
+//===----------------------------------------------------------------------===//
+// AArch64 Uses the MC printer for asm output, so make sure the TableGen
+// AsmWriter bits get associated with the correct class.
+def GenericAsmWriter : AsmWriter {
+  string AsmWriterClassName  = "InstPrinter";
+  int Variant = 0;
+  bit isMCAsmWriter = 1;
+}
+
+def AppleAsmWriter : AsmWriter {
+  let AsmWriterClassName = "AppleInstPrinter";
+  int Variant = 1;
+  int isMCAsmWriter = 1;
+}
+
+//===----------------------------------------------------------------------===//
+// Target Declaration
+//===----------------------------------------------------------------------===//
+
+def AArch64 : Target {
+  let InstructionSet = AArch64InstrInfo;
+  let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
+  let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];
+}
diff --git a/lib/Target/AArch64/AArch64AddressTypePromotion.cpp b/lib/Target/AArch64/AArch64AddressTypePromotion.cpp
new file mode 100644 (file)
index 0000000..04906f6
--- /dev/null
@@ -0,0 +1,492 @@
+//===-- AArch64AddressTypePromotion.cpp --- Promote type for addr accesses -==//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This pass tries to promote the computations use to obtained a sign extended
+// value used into memory accesses.
+// E.g.
+// a = add nsw i32 b, 3
+// d = sext i32 a to i64
+// e = getelementptr ..., i64 d
+//
+// =>
+// f = sext i32 b to i64
+// a = add nsw i64 f, 3
+// e = getelementptr ..., i64 a
+//
+// This is legal to do so if the computations are markers with either nsw or nuw
+// markers.
+// Moreover, the current heuristic is simple: it does not create new sext
+// operations, i.e., it gives up when a sext would have forked (e.g., if
+// a = add i32 b, c, two sexts are required to promote the computation).
+//
+// FIXME: This pass may be useful for other targets too.
+// ===---------------------------------------------------------------------===//
+
+#include "AArch64.h"
+#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/SmallPtrSet.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/IR/Constants.h"
+#include "llvm/IR/Dominators.h"
+#include "llvm/IR/Function.h"
+#include "llvm/IR/Instructions.h"
+#include "llvm/IR/Module.h"
+#include "llvm/IR/Operator.h"
+#include "llvm/Pass.h"
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/Debug.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "aarch64-type-promotion"
+
+static cl::opt<bool>
+EnableAddressTypePromotion("aarch64-type-promotion", cl::Hidden,
+                           cl::desc("Enable the type promotion pass"),
+                           cl::init(true));
+static cl::opt<bool>
+EnableMerge("aarch64-type-promotion-merge", cl::Hidden,
+            cl::desc("Enable merging of redundant sexts when one is dominating"
+                     " the other."),
+            cl::init(true));
+
+//===----------------------------------------------------------------------===//
+//                       AArch64AddressTypePromotion
+//===----------------------------------------------------------------------===//
+
+namespace llvm {
+void initializeAArch64AddressTypePromotionPass(PassRegistry &);
+}
+
+namespace {
+class AArch64AddressTypePromotion : public FunctionPass {
+
+public:
+  static char ID;
+  AArch64AddressTypePromotion()
+      : FunctionPass(ID), Func(nullptr), ConsideredSExtType(nullptr) {
+    initializeAArch64AddressTypePromotionPass(*PassRegistry::getPassRegistry());
+  }
+
+  const char *getPassName() const override {
+    return "AArch64 Address Type Promotion";
+  }
+
+  /// Iterate over the functions and promote the computation of interesting
+  // sext instructions.
+  bool runOnFunction(Function &F) override;
+
+private:
+  /// The current function.
+  Function *Func;
+  /// Filter out all sexts that does not have this type.
+  /// Currently initialized with Int64Ty.
+  Type *ConsideredSExtType;
+
+  // This transformation requires dominator info.
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
+    AU.setPreservesCFG();
+    AU.addRequired<DominatorTreeWrapperPass>();
+    AU.addPreserved<DominatorTreeWrapperPass>();
+    FunctionPass::getAnalysisUsage(AU);
+  }
+
+  typedef SmallPtrSet<Instruction *, 32> SetOfInstructions;
+  typedef SmallVector<Instruction *, 16> Instructions;
+  typedef DenseMap<Value *, Instructions> ValueToInsts;
+
+  /// Check if it is profitable to move a sext through this instruction.
+  /// Currently, we consider it is profitable if:
+  /// - Inst is used only once (no need to insert truncate).
+  /// - Inst has only one operand that will require a sext operation (we do
+  ///   do not create new sext operation).
+  bool shouldGetThrough(const Instruction *Inst);
+
+  /// Check if it is possible and legal to move a sext through this
+  /// instruction.
+  /// Current heuristic considers that we can get through:
+  /// - Arithmetic operation marked with the nsw or nuw flag.
+  /// - Other sext operation.
+  /// - Truncate operation if it was just dropping sign extended bits.
+  bool canGetThrough(const Instruction *Inst);
+
+  /// Move sext operations through safe to sext instructions.
+  bool propagateSignExtension(Instructions &SExtInsts);
+
+  /// Is this sext should be considered for code motion.
+  /// We look for sext with ConsideredSExtType and uses in at least one
+  // GetElementPtrInst.
+  bool shouldConsiderSExt(const Instruction *SExt) const;
+
+  /// Collect all interesting sext operations, i.e., the ones with the right
+  /// type and used in memory accesses.
+  /// More precisely, a sext instruction is considered as interesting if it
+  /// is used in a "complex" getelementptr or it exits at least another
+  /// sext instruction that sign extended the same initial value.
+  /// A getelementptr is considered as "complex" if it has more than 2
+  // operands.
+  void analyzeSExtension(Instructions &SExtInsts);
+
+  /// Merge redundant sign extension operations in common dominator.
+  void mergeSExts(ValueToInsts &ValToSExtendedUses,
+                  SetOfInstructions &ToRemove);
+};
+} // end anonymous namespace.
+
+char AArch64AddressTypePromotion::ID = 0;
+
+INITIALIZE_PASS_BEGIN(AArch64AddressTypePromotion, "aarch64-type-promotion",
+                      "AArch64 Type Promotion Pass", false, false)
+INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
+INITIALIZE_PASS_END(AArch64AddressTypePromotion, "aarch64-type-promotion",
+                    "AArch64 Type Promotion Pass", false, false)
+
+FunctionPass *llvm::createAArch64AddressTypePromotionPass() {
+  return new AArch64AddressTypePromotion();
+}
+
+bool AArch64AddressTypePromotion::canGetThrough(const Instruction *Inst) {
+  if (isa<SExtInst>(Inst))
+    return true;
+
+  const BinaryOperator *BinOp = dyn_cast<BinaryOperator>(Inst);
+  if (BinOp && isa<OverflowingBinaryOperator>(BinOp) &&
+      (BinOp->hasNoUnsignedWrap() || BinOp->hasNoSignedWrap()))
+    return true;
+
+  // sext(trunc(sext)) --> sext
+  if (isa<TruncInst>(Inst) && isa<SExtInst>(Inst->getOperand(0))) {
+    const Instruction *Opnd = cast<Instruction>(Inst->getOperand(0));
+    // Check that the truncate just drop sign extended bits.
+    if (Inst->getType()->getIntegerBitWidth() >=
+            Opnd->getOperand(0)->getType()->getIntegerBitWidth() &&
+        Inst->getOperand(0)->getType()->getIntegerBitWidth() <=
+            ConsideredSExtType->getIntegerBitWidth())
+      return true;
+  }
+
+  return false;
+}
+
+bool AArch64AddressTypePromotion::shouldGetThrough(const Instruction *Inst) {
+  // If the type of the sext is the same as the considered one, this sext
+  // will become useless.
+  // Otherwise, we will have to do something to preserve the original value,
+  // unless it is used once.
+  if (isa<SExtInst>(Inst) &&
+      (Inst->getType() == ConsideredSExtType || Inst->hasOneUse()))
+    return true;
+
+  // If the Inst is used more that once, we may need to insert truncate
+  // operations and we don't do that at the moment.
+  if (!Inst->hasOneUse())
+    return false;
+
+  // This truncate is used only once, thus if we can get thourgh, it will become
+  // useless.
+  if (isa<TruncInst>(Inst))
+    return true;
+
+  // If both operands are not constant, a new sext will be created here.
+  // Current heuristic is: each step should be profitable.
+  // Therefore we don't allow to increase the number of sext even if it may
+  // be profitable later on.
+  if (isa<BinaryOperator>(Inst) && isa<ConstantInt>(Inst->getOperand(1)))
+    return true;
+
+  return false;
+}
+
+static bool shouldSExtOperand(const Instruction *Inst, int OpIdx) {
+  if (isa<SelectInst>(Inst) && OpIdx == 0)
+    return false;
+  return true;
+}
+
+bool
+AArch64AddressTypePromotion::shouldConsiderSExt(const Instruction *SExt) const {
+  if (SExt->getType() != ConsideredSExtType)
+    return false;
+
+  for (const Use &U : SExt->uses()) {
+    if (isa<GetElementPtrInst>(*U))
+      return true;
+  }
+
+  return false;
+}
+
+// Input:
+// - SExtInsts contains all the sext instructions that are use direclty in
+//   GetElementPtrInst, i.e., access to memory.
+// Algorithm:
+// - For each sext operation in SExtInsts:
+//   Let var be the operand of sext.
+//   while it is profitable (see shouldGetThrough), legal, and safe
+//   (see canGetThrough) to move sext through var's definition:
+//   * promote the type of var's definition.
+//   * fold var into sext uses.
+//   * move sext above var's definition.
+//   * update sext operand to use the operand of var that should be sign
+//     extended (by construction there is only one).
+//
+//   E.g.,
+//   a = ... i32 c, 3
+//   b = sext i32 a to i64 <- is it legal/safe/profitable to get through 'a'
+//   ...
+//   = b
+// => Yes, update the code
+//   b = sext i32 c to i64
+//   a = ... i64 b, 3
+//   ...
+//   = a
+// Iterate on 'c'.
+bool
+AArch64AddressTypePromotion::propagateSignExtension(Instructions &SExtInsts) {
+  DEBUG(dbgs() << "*** Propagate Sign Extension ***\n");
+
+  bool LocalChange = false;
+  SetOfInstructions ToRemove;
+  ValueToInsts ValToSExtendedUses;
+  while (!SExtInsts.empty()) {
+    // Get through simple chain.
+    Instruction *SExt = SExtInsts.pop_back_val();
+
+    DEBUG(dbgs() << "Consider:\n" << *SExt << '\n');
+
+    // If this SExt has already been merged continue.
+    if (SExt->use_empty() && ToRemove.count(SExt)) {
+      DEBUG(dbgs() << "No uses => marked as delete\n");
+      continue;
+    }
+
+    // Now try to get through the chain of definitions.
+    while (isa<Instruction>(SExt->getOperand(0))) {
+      Instruction *Inst = dyn_cast<Instruction>(SExt->getOperand(0));
+      DEBUG(dbgs() << "Try to get through:\n" << *Inst << '\n');
+      if (!canGetThrough(Inst) || !shouldGetThrough(Inst)) {
+        // We cannot get through something that is not an Instruction
+        // or not safe to SExt.
+        DEBUG(dbgs() << "Cannot get through\n");
+        break;
+      }
+
+      LocalChange = true;
+      // If this is a sign extend, it becomes useless.
+      if (isa<SExtInst>(Inst) || isa<TruncInst>(Inst)) {
+        DEBUG(dbgs() << "SExt or trunc, mark it as to remove\n");
+        // We cannot use replaceAllUsesWith here because we may trigger some
+        // assertion on the type as all involved sext operation may have not
+        // been moved yet.
+        while (!Inst->use_empty()) {
+          Value::use_iterator UseIt = Inst->use_begin();
+          Instruction *UseInst = dyn_cast<Instruction>(*UseIt);
+          assert(UseInst && "Use of sext is not an Instruction!");
+          UseInst->setOperand(UseIt->getOperandNo(), SExt);
+        }
+        ToRemove.insert(Inst);
+        SExt->setOperand(0, Inst->getOperand(0));
+        SExt->moveBefore(Inst);
+        continue;
+      }
+
+      // Get through the Instruction:
+      // 1. Update its type.
+      // 2. Replace the uses of SExt by Inst.
+      // 3. Sign extend each operand that needs to be sign extended.
+
+      // Step #1.
+      Inst->mutateType(SExt->getType());
+      // Step #2.
+      SExt->replaceAllUsesWith(Inst);
+      // Step #3.
+      Instruction *SExtForOpnd = SExt;
+
+      DEBUG(dbgs() << "Propagate SExt to operands\n");
+      for (int OpIdx = 0, EndOpIdx = Inst->getNumOperands(); OpIdx != EndOpIdx;
+           ++OpIdx) {
+        DEBUG(dbgs() << "Operand:\n" << *(Inst->getOperand(OpIdx)) << '\n');
+        if (Inst->getOperand(OpIdx)->getType() == SExt->getType() ||
+            !shouldSExtOperand(Inst, OpIdx)) {
+          DEBUG(dbgs() << "No need to propagate\n");
+          continue;
+        }
+        // Check if we can statically sign extend the operand.
+        Value *Opnd = Inst->getOperand(OpIdx);
+        if (const ConstantInt *Cst = dyn_cast<ConstantInt>(Opnd)) {
+          DEBUG(dbgs() << "Statically sign extend\n");
+          Inst->setOperand(OpIdx, ConstantInt::getSigned(SExt->getType(),
+                                                         Cst->getSExtValue()));
+          continue;
+        }
+        // UndefValue are typed, so we have to statically sign extend them.
+        if (isa<UndefValue>(Opnd)) {
+          DEBUG(dbgs() << "Statically sign extend\n");
+          Inst->setOperand(OpIdx, UndefValue::get(SExt->getType()));
+          continue;
+        }
+
+        // Otherwise we have to explicity sign extend it.
+        assert(SExtForOpnd &&
+               "Only one operand should have been sign extended");
+
+        SExtForOpnd->setOperand(0, Opnd);
+
+        DEBUG(dbgs() << "Move before:\n" << *Inst << "\nSign extend\n");
+        // Move the sign extension before the insertion point.
+        SExtForOpnd->moveBefore(Inst);
+        Inst->setOperand(OpIdx, SExtForOpnd);
+        // If more sext are required, new instructions will have to be created.
+        SExtForOpnd = nullptr;
+      }
+      if (SExtForOpnd == SExt) {
+        DEBUG(dbgs() << "Sign extension is useless now\n");
+        ToRemove.insert(SExt);
+        break;
+      }
+    }
+
+    // If the use is already of the right type, connect its uses to its argument
+    // and delete it.
+    // This can happen for an Instruction which all uses are sign extended.
+    if (!ToRemove.count(SExt) &&
+        SExt->getType() == SExt->getOperand(0)->getType()) {
+      DEBUG(dbgs() << "Sign extension is useless, attach its use to "
+                      "its argument\n");
+      SExt->replaceAllUsesWith(SExt->getOperand(0));
+      ToRemove.insert(SExt);
+    } else
+      ValToSExtendedUses[SExt->getOperand(0)].push_back(SExt);
+  }
+
+  if (EnableMerge)
+    mergeSExts(ValToSExtendedUses, ToRemove);
+
+  // Remove all instructions marked as ToRemove.
+  for (Instruction *I: ToRemove)
+    I->eraseFromParent();
+  return LocalChange;
+}
+
+void AArch64AddressTypePromotion::mergeSExts(ValueToInsts &ValToSExtendedUses,
+                                             SetOfInstructions &ToRemove) {
+  DominatorTree &DT = getAnalysis<DominatorTreeWrapperPass>().getDomTree();
+
+  for (auto &Entry : ValToSExtendedUses) {
+    Instructions &Insts = Entry.second;
+    Instructions CurPts;
+    for (Instruction *Inst : Insts) {
+      if (ToRemove.count(Inst))
+        continue;
+      bool inserted = false;
+      for (auto Pt : CurPts) {
+        if (DT.dominates(Inst, Pt)) {
+          DEBUG(dbgs() << "Replace all uses of:\n" << *Pt << "\nwith:\n"
+                       << *Inst << '\n');
+          (Pt)->replaceAllUsesWith(Inst);
+          ToRemove.insert(Pt);
+          Pt = Inst;
+          inserted = true;
+          break;
+        }
+        if (!DT.dominates(Pt, Inst))
+          // Give up if we need to merge in a common dominator as the
+          // expermients show it is not profitable.
+          continue;
+
+        DEBUG(dbgs() << "Replace all uses of:\n" << *Inst << "\nwith:\n"
+                     << *Pt << '\n');
+        Inst->replaceAllUsesWith(Pt);
+        ToRemove.insert(Inst);
+        inserted = true;
+        break;
+      }
+      if (!inserted)
+        CurPts.push_back(Inst);
+    }
+  }
+}
+
+void AArch64AddressTypePromotion::analyzeSExtension(Instructions &SExtInsts) {
+  DEBUG(dbgs() << "*** Analyze Sign Extensions ***\n");
+
+  DenseMap<Value *, Instruction *> SeenChains;
+
+  for (auto &BB : *Func) {
+    for (auto &II : BB) {
+      Instruction *SExt = &II;
+
+      // Collect all sext operation per type.
+      if (!isa<SExtInst>(SExt) || !shouldConsiderSExt(SExt))
+        continue;
+
+      DEBUG(dbgs() << "Found:\n" << (*SExt) << '\n');
+
+      // Cases where we actually perform the optimization:
+      // 1. SExt is used in a getelementptr with more than 2 operand =>
+      //    likely we can merge some computation if they are done on 64 bits.
+      // 2. The beginning of the SExt chain is SExt several time. =>
+      //    code sharing is possible.
+
+      bool insert = false;
+      // #1.
+      for (const Use &U : SExt->uses()) {
+        const Instruction *Inst = dyn_cast<GetElementPtrInst>(U);
+        if (Inst && Inst->getNumOperands() > 2) {
+          DEBUG(dbgs() << "Interesting use in GetElementPtrInst\n" << *Inst
+                       << '\n');
+          insert = true;
+          break;
+        }
+      }
+
+      // #2.
+      // Check the head of the chain.
+      Instruction *Inst = SExt;
+      Value *Last;
+      do {
+        int OpdIdx = 0;
+        const BinaryOperator *BinOp = dyn_cast<BinaryOperator>(Inst);
+        if (BinOp && isa<ConstantInt>(BinOp->getOperand(0)))
+          OpdIdx = 1;
+        Last = Inst->getOperand(OpdIdx);
+        Inst = dyn_cast<Instruction>(Last);
+      } while (Inst && canGetThrough(Inst) && shouldGetThrough(Inst));
+
+      DEBUG(dbgs() << "Head of the chain:\n" << *Last << '\n');
+      DenseMap<Value *, Instruction *>::iterator AlreadySeen =
+          SeenChains.find(Last);
+      if (insert || AlreadySeen != SeenChains.end()) {
+        DEBUG(dbgs() << "Insert\n");
+        SExtInsts.push_back(SExt);
+        if (AlreadySeen != SeenChains.end() && AlreadySeen->second != nullptr) {
+          DEBUG(dbgs() << "Insert chain member\n");
+          SExtInsts.push_back(AlreadySeen->second);
+          SeenChains[Last] = nullptr;
+        }
+      } else {
+        DEBUG(dbgs() << "Record its chain membership\n");
+        SeenChains[Last] = SExt;
+      }
+    }
+  }
+}
+
+bool AArch64AddressTypePromotion::runOnFunction(Function &F) {
+  if (!EnableAddressTypePromotion || F.isDeclaration())
+    return false;
+  Func = &F;
+  ConsideredSExtType = Type::getInt64Ty(Func->getContext());
+
+  DEBUG(dbgs() << "*** " << getPassName() << ": " << Func->getName() << '\n');
+
+  Instructions SExtInsts;
+  analyzeSExtension(SExtInsts);
+  return propagateSignExtension(SExtInsts);
+}
diff --git a/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp b/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp
new file mode 100644 (file)
index 0000000..734fb21
--- /dev/null
@@ -0,0 +1,387 @@
+//===-- AArch64AdvSIMDScalar.cpp - Replace dead defs w/ zero reg --===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+// When profitable, replace GPR targeting i64 instructions with their
+// AdvSIMD scalar equivalents. Generally speaking, "profitable" is defined
+// as minimizing the number of cross-class register copies.
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// TODO: Graph based predicate heuristics.
+// Walking the instruction list linearly will get many, perhaps most, of
+// the cases, but to do a truly thorough job of this, we need a more
+// wholistic approach.
+//
+// This optimization is very similar in spirit to the register allocator's
+// spill placement, only here we're determining where to place cross-class
+// register copies rather than spills. As such, a similar approach is
+// called for.
+//
+// We want to build up a set of graphs of all instructions which are candidates
+// for transformation along with instructions which generate their inputs and
+// consume their outputs. For each edge in the graph, we assign a weight
+// based on whether there is a copy required there (weight zero if not) and
+// the block frequency of the block containing the defining or using
+// instruction, whichever is less. Our optimization is then a graph problem
+// to minimize the total weight of all the graphs, then transform instructions
+// and add or remove copy instructions as called for to implement the
+// solution.
+//===----------------------------------------------------------------------===//
+
+#include "AArch64.h"
+#include "AArch64InstrInfo.h"
+#include "AArch64RegisterInfo.h"
+#include "llvm/ADT/Statistic.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
+using namespace llvm;
+
+#define DEBUG_TYPE "aarch64-simd-scalar"
+
+// Allow forcing all i64 operations with equivalent SIMD instructions to use
+// them. For stress-testing the transformation function.
+static cl::opt<bool>
+TransformAll("aarch64-simd-scalar-force-all",
+             cl::desc("Force use of AdvSIMD scalar instructions everywhere"),
+             cl::init(false), cl::Hidden);
+
+STATISTIC(NumScalarInsnsUsed, "Number of scalar instructions used");
+STATISTIC(NumCopiesDeleted, "Number of cross-class copies deleted");
+STATISTIC(NumCopiesInserted, "Number of cross-class copies inserted");
+
+namespace {
+class AArch64AdvSIMDScalar : public MachineFunctionPass {
+  MachineRegisterInfo *MRI;
+  const AArch64InstrInfo *TII;
+
+private:
+  // isProfitableToTransform - Predicate function to determine whether an
+  // instruction should be transformed to its equivalent AdvSIMD scalar
+  // instruction. "add Xd, Xn, Xm" ==> "add Dd, Da, Db", for example.
+  bool isProfitableToTransform(const MachineInstr *MI) const;
+
+  // transformInstruction - Perform the transformation of an instruction
+  // to its equivalant AdvSIMD scalar instruction. Update inputs and outputs
+  // to be the correct register class, minimizing cross-class copies.
+  void transformInstruction(MachineInstr *MI);
+
+  // processMachineBasicBlock - Main optimzation loop.
+  bool processMachineBasicBlock(MachineBasicBlock *MBB);
+
+public:
+  static char ID; // Pass identification, replacement for typeid.
+  explicit AArch64AdvSIMDScalar() : MachineFunctionPass(ID) {}
+
+  bool runOnMachineFunction(MachineFunction &F) override;
+
+  const char *getPassName() const override {
+    return "AdvSIMD Scalar Operation Optimization";
+  }
+
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
+    AU.setPreservesCFG();
+    MachineFunctionPass::getAnalysisUsage(AU);
+  }
+};
+char AArch64AdvSIMDScalar::ID = 0;
+} // end anonymous namespace
+
+static bool isGPR64(unsigned Reg, unsigned SubReg,
+                    const MachineRegisterInfo *MRI) {
+  if (SubReg)
+    return false;
+  if (TargetRegisterInfo::isVirtualRegister(Reg))
+    return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass);
+  return AArch64::GPR64RegClass.contains(Reg);
+}
+
+static bool isFPR64(unsigned Reg, unsigned SubReg,
+                    const MachineRegisterInfo *MRI) {
+  if (TargetRegisterInfo::isVirtualRegister(Reg))
+    return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) &&
+            SubReg == 0) ||
+           (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) &&
+            SubReg == AArch64::dsub);
+  // Physical register references just check the register class directly.
+  return (AArch64::FPR64RegClass.contains(Reg) && SubReg == 0) ||
+         (AArch64::FPR128RegClass.contains(Reg) && SubReg == AArch64::dsub);
+}
+
+// getSrcFromCopy - Get the original source register for a GPR64 <--> FPR64
+// copy instruction. Return zero_reg if the instruction is not a copy.
+static unsigned getSrcFromCopy(const MachineInstr *MI,
+                               const MachineRegisterInfo *MRI,
+                               unsigned &SubReg) {
+  SubReg = 0;
+  // The "FMOV Xd, Dn" instruction is the typical form.
+  if (MI->getOpcode() == AArch64::FMOVDXr ||
+      MI->getOpcode() == AArch64::FMOVXDr)
+    return MI->getOperand(1).getReg();
+  // A lane zero extract "UMOV.d Xd, Vn[0]" is equivalent. We shouldn't see
+  // these at this stage, but it's easy to check for.
+  if (MI->getOpcode() == AArch64::UMOVvi64 && MI->getOperand(2).getImm() == 0) {
+    SubReg = AArch64::dsub;
+    return MI->getOperand(1).getReg();
+  }
+  // Or just a plain COPY instruction. This can be directly to/from FPR64,
+  // or it can be a dsub subreg reference to an FPR128.
+  if (MI->getOpcode() == AArch64::COPY) {
+    if (isFPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(),
+                MRI) &&
+        isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI))
+      return MI->getOperand(1).getReg();
+    if (isGPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(),
+                MRI) &&
+        isFPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(),
+                MRI)) {
+      SubReg = MI->getOperand(1).getSubReg();
+      return MI->getOperand(1).getReg();
+    }
+  }
+
+  // Otherwise, this is some other kind of instruction.
+  return 0;
+}
+
+// getTransformOpcode - For any opcode for which there is an AdvSIMD equivalent
+// that we're considering transforming to, return that AdvSIMD opcode. For all
+// others, return the original opcode.
+static int getTransformOpcode(unsigned Opc) {
+  switch (Opc) {
+  default:
+    break;
+  // FIXME: Lots more possibilities.
+  case AArch64::ADDXrr:
+    return AArch64::ADDv1i64;
+  case AArch64::SUBXrr:
+    return AArch64::SUBv1i64;
+  }
+  // No AdvSIMD equivalent, so just return the original opcode.
+  return Opc;
+}
+
+static bool isTransformable(const MachineInstr *MI) {
+  int Opc = MI->getOpcode();
+  return Opc != getTransformOpcode(Opc);
+}
+
+// isProfitableToTransform - Predicate function to determine whether an
+// instruction should be transformed to its equivalent AdvSIMD scalar
+// instruction. "add Xd, Xn, Xm" ==> "add Dd, Da, Db", for example.
+bool
+AArch64AdvSIMDScalar::isProfitableToTransform(const MachineInstr *MI) const {
+  // If this instruction isn't eligible to be transformed (no SIMD equivalent),
+  // early exit since that's the common case.
+  if (!isTransformable(MI))
+    return false;
+
+  // Count the number of copies we'll need to add and approximate the number
+  // of copies that a transform will enable us to remove.
+  unsigned NumNewCopies = 3;
+  unsigned NumRemovableCopies = 0;
+
+  unsigned OrigSrc0 = MI->getOperand(1).getReg();
+  unsigned OrigSrc1 = MI->getOperand(2).getReg();
+  unsigned Src0 = 0, SubReg0;
+  unsigned Src1 = 0, SubReg1;
+  if (!MRI->def_empty(OrigSrc0)) {
+    MachineRegisterInfo::def_instr_iterator Def =
+        MRI->def_instr_begin(OrigSrc0);
+    assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!");
+    Src0 = getSrcFromCopy(&*Def, MRI, SubReg0);
+    // If the source was from a copy, we don't need to insert a new copy.
+    if (Src0)
+      --NumNewCopies;
+    // If there are no other users of the original source, we can delete
+    // that instruction.
+    if (Src0 && MRI->hasOneNonDBGUse(OrigSrc0))
+      ++NumRemovableCopies;
+  }
+  if (!MRI->def_empty(OrigSrc1))