Two more test cases: or_ops.ll (arithmetic or operations) and vecinsert.ll

(vector insertions)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45216 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp
index 253fafb8e95efdaf7ca1d42989132eea6b4009dd..7d221877512e78549ce28f513a247f3fa67039ad 100644 (file)
--- a/lib/Target/CellSPU/SPUISelLowering.cpp
+++ b/lib/Target/CellSPU/SPUISelLowering.cpp
@@ -880,13 +880,12 @@ LowerConstantFP(SDOperand Op, SelectionDAG &DAG) {
   assert((FP != 0) &&
         "LowerConstantFP: Node is not ConstantFPSDNode");
 
-  const APFloat &apf = FP->getValueAPF();
-
   if (VT == MVT::f32) {
+    float targetConst = FP->getValueAPF().convertToFloat();
     return DAG.getNode(SPUISD::SFPConstant, VT,
-                      DAG.getTargetConstantFP(apf.convertToFloat(), VT));
+                      DAG.getTargetConstantFP(targetConst, VT));
   } else if (VT == MVT::f64) {
-    uint64_t dbits = DoubleToBits(apf.convertToDouble());
+    uint64_t dbits = DoubleToBits(FP->getValueAPF().convertToDouble());
     return DAG.getNode(ISD::BIT_CONVERT, VT,
                       LowerConstant(DAG.getConstant(dbits, MVT::i64), DAG));
   }

diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp
index efd45f56dcdf48392a41e697e6243ba7fefe81ab..5c2bd52d50198bc9707ddbfd6a79169910397741 100644 (file)
--- a/lib/Target/CellSPU/SPUInstrInfo.cpp
+++ b/lib/Target/CellSPU/SPUInstrInfo.cpp
@@ -98,13 +98,13 @@ SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
     destReg = MI.getOperand(0).getReg();
     return true;
 #endif
-    // case SPU::ORv16i8_i8:
+  case SPU::ORv16i8_i8:
   case SPU::ORv8i16_i16:
   case SPU::ORv4i32_i32:
   case SPU::ORv2i64_i64:
   case SPU::ORv4f32_f32:
   case SPU::ORv2f64_f64:
-    // case SPU::ORi8_v16i8:
+  case SPU::ORi8_v16i8:
   case SPU::ORi16_v8i16:
   case SPU::ORi32_v4i32:
   case SPU::ORi64_v2i64:

diff --git a/test/CodeGen/CellSPU/dg.exp b/test/CodeGen/CellSPU/dg.exp
new file mode 100644 (file)
index 0000000..1c0f7f8
--- /dev/null
+++ b/test/CodeGen/CellSPU/dg.exp
@@ -0,0 +1,5 @@
+load_lib llvm.exp
+
+if { [llvm_supports_target CellSPU] } {
+  RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]]
+}

diff --git a/test/CodeGen/CellSPU/or_ops.ll b/test/CodeGen/CellSPU/or_ops.ll
new file mode 100644 (file)
index 0000000..6c46b41
--- /dev/null
+++ b/test/CodeGen/CellSPU/or_ops.ll
@@ -0,0 +1,262 @@
+; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
+; RUN: grep and    %t1.s | count 2
+; RUN: grep orc    %t1.s | count 85
+; RUN: grep ori    %t1.s | count 30
+; RUN: grep orhi   %t1.s | count 30
+; RUN: grep orbi   %t1.s | count 15
+
+; OR instruction generation:
+define <4 x i32> @or_v4i32_1(<4 x i32> %arg1, <4 x i32> %arg2) {
+        %A = or <4 x i32> %arg1, %arg2
+        ret <4 x i32> %A
+}
+
+define <4 x i32> @or_v4i32_2(<4 x i32> %arg1, <4 x i32> %arg2) {
+        %A = or <4 x i32> %arg2, %arg1
+        ret <4 x i32> %A
+}
+
+define <8 x i16> @or_v8i16_1(<8 x i16> %arg1, <8 x i16> %arg2) {
+        %A = or <8 x i16> %arg1, %arg2
+        ret <8 x i16> %A
+}
+
+define <8 x i16> @or_v8i16_2(<8 x i16> %arg1, <8 x i16> %arg2) {
+        %A = or <8 x i16> %arg2, %arg1
+        ret <8 x i16> %A
+}
+
+define <16 x i8> @or_v16i8_1(<16 x i8> %arg1, <16 x i8> %arg2) {
+        %A = or <16 x i8> %arg2, %arg1
+        ret <16 x i8> %A
+}
+
+define <16 x i8> @or_v16i8_2(<16 x i8> %arg1, <16 x i8> %arg2) {
+        %A = or <16 x i8> %arg1, %arg2
+        ret <16 x i8> %A
+}
+
+define i32 @or_i32_1(i32 %arg1, i32 %arg2) {
+       %A = or i32 %arg2, %arg1
+       ret i32 %A
+}
+
+define i32 @or_i32_2(i32 %arg1, i32 %arg2) {
+       %A = or i32 %arg1, %arg2
+       ret i32 %A
+}
+
+define i16 @or_i16_1(i16 %arg1, i16 %arg2) {
+       %A = or i16 %arg2, %arg1
+       ret i16 %A
+}
+
+define i16 @or_i16_2(i16 %arg1, i16 %arg2) {
+       %A = or i16 %arg1, %arg2
+       ret i16 %A
+}
+
+define i8 @or_i8_1(i8 %arg1, i8 %arg2) {
+       %A = or i8 %arg2, %arg1
+       ret i8 %A
+}
+
+define i8 @or_i8_2(i8 %arg1, i8 %arg2) {
+       %A = or i8 %arg1, %arg2
+       ret i8 %A
+}
+
+; ORC instruction generation:
+define <4 x i32> @orc_v4i32_1(<4 x i32> %arg1, <4 x i32> %arg2) {
+        %A = xor <4 x i32> %arg2, < i32 -1, i32 -1, i32 -1, i32 -1 >
+        %B = or <4 x i32> %arg1, %A
+        ret <4 x i32> %B
+}
+
+define <4 x i32> @orc_v4i32_2(<4 x i32> %arg1, <4 x i32> %arg2) {
+        %A = xor <4 x i32> %arg1, < i32 -1, i32 -1, i32 -1, i32 -1 >
+        %B = or <4 x i32> %arg2, %A
+        ret <4 x i32> %B
+}
+
+define <4 x i32> @orc_v4i32_3(<4 x i32> %arg1, <4 x i32> %arg2) {
+        %A = xor <4 x i32> %arg1, < i32 -1, i32 -1, i32 -1, i32 -1 >
+        %B = or <4 x i32> %A, %arg2
+        ret <4 x i32> %B
+}
+
+define <8 x i16> @orc_v8i16_1(<8 x i16> %arg1, <8 x i16> %arg2) {
+        %A = xor <8 x i16> %arg2, < i16 -1, i16 -1, i16 -1, i16 -1,
+                                    i16 -1, i16 -1, i16 -1, i16 -1 >
+        %B = or <8 x i16> %arg1, %A
+        ret <8 x i16> %B
+}
+
+define <8 x i16> @orc_v8i16_2(<8 x i16> %arg1, <8 x i16> %arg2) {
+        %A = xor <8 x i16> %arg1, < i16 -1, i16 -1, i16 -1, i16 -1,
+                                    i16 -1, i16 -1, i16 -1, i16 -1 >
+        %B = or <8 x i16> %arg2, %A
+        ret <8 x i16> %B
+}
+
+define <16 x i8> @orc_v16i8_1(<16 x i8> %arg1, <16 x i8> %arg2) {
+        %A = xor <16 x i8> %arg1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
+                                    i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
+                                    i8 -1, i8 -1, i8 -1, i8 -1 >
+        %B = or <16 x i8> %arg2, %A
+        ret <16 x i8> %B
+}
+
+define <16 x i8> @orc_v16i8_2(<16 x i8> %arg1, <16 x i8> %arg2) {
+        %A = xor <16 x i8> %arg2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
+                                    i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
+                                    i8 -1, i8 -1, i8 -1, i8 -1 >
+        %B = or <16 x i8> %arg1, %A
+        ret <16 x i8> %B
+}
+
+define <16 x i8> @orc_v16i8_3(<16 x i8> %arg1, <16 x i8> %arg2) {
+        %A = xor <16 x i8> %arg2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
+                                    i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
+                                    i8 -1, i8 -1, i8 -1, i8 -1 >
+        %B = or <16 x i8> %A, %arg1
+        ret <16 x i8> %B
+}
+
+define i32 @orc_i32_1(i32 %arg1, i32 %arg2) {
+       %A = xor i32 %arg2, -1
+       %B = or i32 %A, %arg1
+       ret i32 %B
+}
+
+define i32 @orc_i32_2(i32 %arg1, i32 %arg2) {
+       %A = xor i32 %arg1, -1
+       %B = or i32 %A, %arg2
+       ret i32 %B
+}
+
+define i32 @orc_i32_3(i32 %arg1, i32 %arg2) {
+       %A = xor i32 %arg2, -1
+       %B = or i32 %arg1, %A
+       ret i32 %B
+}
+
+define i16 @orc_i16_1(i16 %arg1, i16 %arg2) {
+       %A = xor i16 %arg2, -1
+       %B = or i16 %A, %arg1
+       ret i16 %B
+}
+
+define i16 @orc_i16_2(i16 %arg1, i16 %arg2) {
+       %A = xor i16 %arg1, -1
+       %B = or i16 %A, %arg2
+       ret i16 %B
+}
+
+define i16 @orc_i16_3(i16 %arg1, i16 %arg2) {
+       %A = xor i16 %arg2, -1
+       %B = or i16 %arg1, %A
+       ret i16 %B
+}
+
+define i8 @orc_i8_1(i8 %arg1, i8 %arg2) {
+       %A = xor i8 %arg2, -1
+       %B = or i8 %A, %arg1
+       ret i8 %B
+}
+
+define i8 @orc_i8_2(i8 %arg1, i8 %arg2) {
+       %A = xor i8 %arg1, -1
+       %B = or i8 %A, %arg2
+       ret i8 %B
+}
+
+define i8 @orc_i8_3(i8 %arg1, i8 %arg2) {
+       %A = xor i8 %arg2, -1
+       %B = or i8 %arg1, %A
+       ret i8 %B
+}
+
+; ORI instruction generation (i32 data type):
+define <4 x i32> @ori_v4i32_1(<4 x i32> %in) {
+        %tmp2 = or <4 x i32> %in, < i32 511, i32 511, i32 511, i32 511 >
+        ret <4 x i32> %tmp2
+}
+
+define <4 x i32> @ori_v4i32_2(<4 x i32> %in) {
+        %tmp2 = or <4 x i32> %in, < i32 510, i32 510, i32 510, i32 510 >
+        ret <4 x i32> %tmp2
+}
+
+define <4 x i32> @ori_v4i32_3(<4 x i32> %in) {
+        %tmp2 = or <4 x i32> %in, < i32 -1, i32 -1, i32 -1, i32 -1 >
+        ret <4 x i32> %tmp2
+}
+
+define <4 x i32> @ori_v4i32_4(<4 x i32> %in) {
+        %tmp2 = or <4 x i32> %in, < i32 -512, i32 -512, i32 -512, i32 -512 >
+        ret <4 x i32> %tmp2
+}
+
+define i32 @ori_u32(i32 zeroext  %in) zeroext  {
+        %tmp37 = or i32 %in, 37         ; <i32> [#uses=1]
+        ret i32 %tmp37
+}
+
+define i32 @ori_i32(i32 signext  %in) signext  {
+        %tmp38 = or i32 %in, 37         ; <i32> [#uses=1]
+        ret i32 %tmp38
+}
+
+; ORHI instruction generation (i16 data type):
+define <8 x i16> @orhi_v8i16_1(<8 x i16> %in) {
+        %tmp2 = or <8 x i16> %in, < i16 511, i16 511, i16 511, i16 511,
+                                    i16 511, i16 511, i16 511, i16 511 >
+        ret <8 x i16> %tmp2
+}
+
+define <8 x i16> @orhi_v8i16_2(<8 x i16> %in) {
+        %tmp2 = or <8 x i16> %in, < i16 510, i16 510, i16 510, i16 510,
+                                    i16 510, i16 510, i16 510, i16 510 >
+        ret <8 x i16> %tmp2
+}
+
+define <8 x i16> @orhi_v8i16_3(<8 x i16> %in) {
+        %tmp2 = or <8 x i16> %in, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1,
+                                    i16 -1, i16 -1, i16 -1 >
+        ret <8 x i16> %tmp2
+}
+
+define <8 x i16> @orhi_v8i16_4(<8 x i16> %in) {
+        %tmp2 = or <8 x i16> %in, < i16 -512, i16 -512, i16 -512, i16 -512,
+                                    i16 -512, i16 -512, i16 -512, i16 -512 >
+        ret <8 x i16> %tmp2
+}
+
+define i16 @orhi_u16(i16 zeroext  %in) zeroext  {
+        %tmp37 = or i16 %in, 37         ; <i16> [#uses=1]
+        ret i16 %tmp37
+}
+
+define i16 @orhi_i16(i16 signext  %in) signext  {
+        %tmp38 = or i16 %in, 37         ; <i16> [#uses=1]
+        ret i16 %tmp38
+}
+
+; ORBI instruction generation (i8 data type):
+define <16 x i8> @orbi_v16i8(<16 x i8> %in) {
+        %tmp2 = or <16 x i8> %in, < i8 42, i8 42, i8 42, i8 42, i8 42, i8 42,
+                                    i8 42, i8 42, i8 42, i8 42, i8 42, i8 42,
+                                    i8 42, i8 42, i8 42, i8 42 >
+        ret <16 x i8> %tmp2
+}
+
+define i8 @orbi_u8(i8 zeroext  %in) zeroext  {
+        %tmp37 = or i8 %in, 37         ; <i8> [#uses=1]
+        ret i8 %tmp37
+}
+
+define i8 @orbi_i8(i8 signext  %in) signext  {
+        %tmp38 = or i8 %in, 37         ; <i8> [#uses=1]
+        ret i8 %tmp38
+}

diff --git a/test/CodeGen/CellSPU/vecinsert.ll b/test/CodeGen/CellSPU/vecinsert.ll
new file mode 100644 (file)
index 0000000..104a205
--- /dev/null
+++ b/test/CodeGen/CellSPU/vecinsert.ll
@@ -0,0 +1,53 @@
+; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
+; RUN: grep cbd     %t1.s | count 3 &&
+; RUN: grep chd     %t1.s | count 3 &&
+; RUN: grep cwd     %t1.s | count 6 &&
+; RUN: grep il      %t1.s | count 4 &&
+; RUN: grep ilh     %t1.s | count 3 &&
+; RUN: grep iohl    %t1.s | count 1 &&
+; RUN: grep ilhu    %t1.s | count 1 &&
+; RUN: grep shufb   %t1.s | count 12 &&
+; RUN: grep 17219   %t1.s | count 1 &&
+; RUN: grep 22598   %t1.s | count 1 &&
+; RUN: grep -- -39  %t1.s | count 1 &&
+; RUN: grep    24   %t1.s | count 1 &&
+; RUN: grep  1159   %t1.s | count 1
+; ModuleID = 'vecinsert.bc'
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128"
+target triple = "spu-unknown-elf"
+
+; 67 -> 0x43, as 8-bit vector constant load = 0x4343 (17219)0x4343
+define <16 x i8> @test_v16i8(<16 x i8> %P, i8 %x) {
+entry:
+       %tmp1 = insertelement <16 x i8> %P, i8 %x, i32 10
+       %tmp1.1 = insertelement <16 x i8> %tmp1, i8 67, i32 7
+       %tmp1.2 = insertelement <16 x i8> %tmp1.1, i8 %x, i32 15
+       ret <16 x i8> %tmp1.2
+}
+
+; 22598 -> 0x5846
+define <8 x i16> @test_v8i16(<8 x i16> %P, i16 %x) {
+entry:
+       %tmp1 = insertelement <8 x i16> %P, i16 %x, i32 5
+       %tmp1.1 = insertelement <8 x i16> %tmp1, i16 22598, i32 7
+       %tmp1.2 = insertelement <8 x i16> %tmp1.1, i16 %x, i32 2
+       ret <8 x i16> %tmp1.2
+}
+
+; 1574023 -> 0x180487 (ILHU 24/IOHL 1159)
+define <4 x i32> @test_v4i32_1(<4 x i32> %P, i32 %x) {
+entry:
+       %tmp1 = insertelement <4 x i32> %P, i32 %x, i32 2
+       %tmp1.1 = insertelement <4 x i32> %tmp1, i32 1574023, i32 1
+       %tmp1.2 = insertelement <4 x i32> %tmp1.1, i32 %x, i32 3
+       ret <4 x i32> %tmp1.2
+}
+
+; Should generate IL for the load
+define <4 x i32> @test_v4i32_2(<4 x i32> %P, i32 %x) {
+entry:
+       %tmp1 = insertelement <4 x i32> %P, i32 %x, i32 2
+       %tmp1.1 = insertelement <4 x i32> %tmp1, i32 -39, i32 1
+       %tmp1.2 = insertelement <4 x i32> %tmp1.1, i32 %x, i32 3
+       ret <4 x i32> %tmp1.2
+}