Merging r259177:

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r259177 | echristo | 2016-01-28 23:20:01 -0800 (Thu, 28 Jan 2016) | 5 lines

Since LI/LIS sign extend the constant passed into the instruction we should
check that the sign extended constant fits into 16-bits if we want a
zero extended value, otherwise go ahead and put it together piecemeal.

Fixes PR26356.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_38@259713 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCFastISel.cpp b/lib/Target/PowerPC/PPCFastISel.cpp
index 188c8e84c64d6a159bc7a55a875f1c2c12352222..777cc3b601c0742c523c8f9f05cb7fde8044d81d 100644 (file)
--- a/lib/Target/PowerPC/PPCFastISel.cpp
+++ b/lib/Target/PowerPC/PPCFastISel.cpp
@@ -2099,7 +2099,9 @@ unsigned PPCFastISel::PPCMaterializeInt(const ConstantInt *CI, MVT VT,
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ImmReg)
         .addImm(CI->getSExtValue());
     return ImmReg;
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ImmReg)
         .addImm(CI->getSExtValue());
     return ImmReg;

-  } else if (!UseSExt && isUInt<16>(CI->getZExtValue())) {
+  } else if (!UseSExt && isUInt<16>(CI->getSExtValue())) {
+    // Since LI will sign extend the constant we need to make sure that for
+    // our zeroext constants that the sign extended constant fits into 16-bits.

     unsigned Opc = (VT == MVT::i64) ? PPC::LI8 : PPC::LI;
     unsigned ImmReg = createResultReg(RC);
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ImmReg)
     unsigned Opc = (VT == MVT::i64) ? PPC::LI8 : PPC::LI;
     unsigned ImmReg = createResultReg(RC);
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ImmReg)


@@ -2109,7 +2111,6 @@ unsigned PPCFastISel::PPCMaterializeInt(const ConstantInt *CI, MVT VT,
 
   // Construct the constant piecewise.
   int64_t Imm = UseSExt ? CI->getSExtValue() : CI->getZExtValue();
 
   // Construct the constant piecewise.
   int64_t Imm = UseSExt ? CI->getSExtValue() : CI->getZExtValue();

-

   if (VT == MVT::i64)
     return PPCMaterialize64BitInt(Imm, RC);
   else if (VT == MVT::i32)
   if (VT == MVT::i64)
     return PPCMaterialize64BitInt(Imm, RC);
   else if (VT == MVT::i32)

diff --git a/test/CodeGen/PowerPC/fast-isel-ret.ll b/test/CodeGen/PowerPC/fast-isel-ret.ll
index e05ef7d9ab82477832ff00cbd71fde25270c7453..0adb5a9351090264832f8428f19be1957e1cc574 100644 (file)
--- a/test/CodeGen/PowerPC/fast-isel-ret.ll
+++ b/test/CodeGen/PowerPC/fast-isel-ret.ll
@@ -186,3 +186,12 @@ entry:
 ; ELF64: blr
   ret i32 -1
 }
 ; ELF64: blr
   ret i32 -1
 }

+
+define zeroext i16 @ret20() nounwind {
+entry:
+; ELF64-LABEL: ret20
+; ELF64: lis{{.*}}0
+; ELF64: ori{{.*}}32768
+; ELF64: blr
+  ret i16 32768
+}