two register machineoperands are not identical unless their subregs match.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45455 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index f54cbe7f1c80afefb38ea54dec210a1d889714d4..e8f692e15f8acc1535fa4429496a69f07ad0f390 100644 (file)
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -153,7 +153,8 @@ bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
   switch (getType()) {
   default: assert(0 && "Unrecognized operand type");
   case MachineOperand::MO_Register:
-    return getReg() == Other.getReg() && isDef() == Other.isDef();
+    return getReg() == Other.getReg() && isDef() == Other.isDef() &&
+           getSubReg() == Other.getSubReg();
   case MachineOperand::MO_Immediate:
     return getImm() == Other.getImm();
   case MachineOperand::MO_MachineBasicBlock: