///
/// This is an ImmutablePass solely for the purpose of exposing CodeGen options
/// to the internals of other CodeGen passes.
-///
-/// FIXME: Why are we passing the DisableVerify flags around instead of setting
-/// an options in the target machine, like all the other driver options?
class TargetPassConfig : public ImmutablePass {
protected:
TargetMachine *TM;
PassManagerBase ±
+
+ // Target Pass Options
+ //
bool DisableVerify;
public:
- TargetPassConfig(TargetMachine *tm, PassManagerBase &pm,
- bool DisableVerifyFlag);
+ TargetPassConfig(TargetMachine *tm, PassManagerBase &pm);
// Dummy constructor.
TargetPassConfig();
return *static_cast<TMC*>(TM);
}
+ const TargetLowering *getTargetLowering() const {
+ return TM->getTargetLowering();
+ }
+
CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); }
- const TargetLowering *getTargetLowering() const { return TM->getTargetLowering(); }
+ void setDisableVerify(bool disable) { DisableVerify = disable; }
+
+ /// Add common target configurable passes that perform LLVM IR to IR
+ /// transforms following machine independent optimization.
+ virtual void addIRPasses();
+
+ /// Add common passes that perform LLVM IR to IR transforms in preparation for
+ /// instruction selection.
+ virtual void addISelPrepare();
+
+ /// addInstSelector - This method should install an instruction selector pass,
+ /// which converts from LLVM code to machine instructions.
+ virtual bool addInstSelector() {
+ return true;
+ }
/// Add the complete, standard set of LLVM CodeGen passes.
/// Fully developed targets will not generally override this.
- virtual bool addCodeGenPasses(MCContext *&OutContext);
-
+ virtual void addMachinePasses();
protected:
- /// Convenient points in the common codegen pass pipeline for inserting
- /// passes, and major CodeGen stages that some targets may override.
+ /// Methods with trivial inline returns are convenient points in the common
+ /// codegen pass pipeline where targets may insert passes. Methods with
+ /// out-of-line standard implementations are major CodeGen stages called by
+ /// addMachinePasses. Some targets may override major stages when inserting
+ /// passes is insufficient, but maintaining overriden stages is more work.
///
/// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
return true;
}
- /// addInstSelector - This method should install an instruction selector pass,
- /// which converts from LLVM code to machine instructions.
- virtual bool addInstSelector() {
- return true;
- }
-
/// addPreRegAlloc - This method may be implemented by targets that want to
/// run passes immediately before register allocation. This should return
/// true if -print-machineinstrs should print after these passes.
public:
/// createPassConfig - Create a pass configuration object to be used by
/// addPassToEmitX methods for generating a pipeline of CodeGen passes.
- virtual TargetPassConfig *createPassConfig(PassManagerBase &PM,
- bool DisableVerify);
+ virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
/// addPassesToEmitFile - Add passes to the specified pass manager to get the
/// specified file emitted. Typically this will involve several steps of code
//
//===----------------------------------------------------------------------===//
-#include "llvm/Target/TargetMachine.h"
+#include "llvm/Transforms/Scalar.h"
#include "llvm/PassManager.h"
#include "llvm/CodeGen/AsmPrinter.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/MachineFunctionAnalysis.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/Target/TargetLowering.h"
+#include "llvm/Target/TargetLoweringObjectFile.h"
+#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSubtargetInfo.h"
-#include "llvm/Target/TargetInstrInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include "llvm/ADT/OwningPtr.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/FormattedStream.h"
#include "llvm/Support/TargetRegistry.h"
using namespace llvm;
+// Enable or disable FastISel. Both options are needed, because
+// FastISel is enabled by default with -fast, and we wish to be
+// able to enable or disable fast-isel independently from -O0.
+static cl::opt<cl::boolOrDefault>
+EnableFastISelOption("fast-isel", cl::Hidden,
+ cl::desc("Enable the \"fast\" instruction selector"));
+
static cl::opt<bool> ShowMCEncoding("show-mc-encoding", cl::Hidden,
cl::desc("Show encoding in .s output"));
static cl::opt<bool> ShowMCInst("show-mc-inst", cl::Hidden,
"and that InitializeAllTargetMCs() is being invoked!");
}
+/// Turn exception handling constructs into something the code generators can
+/// handle.
+static void addPassesToHandleExceptions(TargetMachine *TM,
+ PassManagerBase &PM) {
+ switch (TM->getMCAsmInfo()->getExceptionHandlingType()) {
+ case ExceptionHandling::SjLj:
+ // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
+ // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
+ // catch info can get misplaced when a selector ends up more than one block
+ // removed from the parent invoke(s). This could happen when a landing
+ // pad is shared by multiple invokes and is also a target of a normal
+ // edge from elsewhere.
+ PM.add(createSjLjEHPass(TM->getTargetLowering()));
+ // FALLTHROUGH
+ case ExceptionHandling::DwarfCFI:
+ case ExceptionHandling::ARM:
+ case ExceptionHandling::Win64:
+ PM.add(createDwarfEHPass(TM));
+ break;
+ case ExceptionHandling::None:
+ PM.add(createLowerInvokePass(TM->getTargetLowering()));
+
+ // The lower invoke pass may create unreachable code. Remove it.
+ PM.add(createUnreachableBlockEliminationPass());
+ break;
+ }
+}
+
+/// addPassesToX helper drives creation and initialization of TargetPassConfig.
+static MCContext *addPassesToGenerateCode(LLVMTargetMachine *TM,
+ PassManagerBase &PM,
+ bool DisableVerify) {
+ // Targets may override createPassConfig to provide a target-specific sublass.
+ TargetPassConfig *PassConfig = TM->createPassConfig(PM);
+
+ // Set PassConfig options provided by TargetMachine.
+ PassConfig->setDisableVerify(DisableVerify);
+
+ PassConfig->addIRPasses();
+
+ addPassesToHandleExceptions(TM, PM);
+
+ PassConfig->addISelPrepare();
+
+ // Install a MachineModuleInfo class, which is an immutable pass that holds
+ // all the per-module stuff we're generating, including MCContext.
+ MachineModuleInfo *MMI =
+ new MachineModuleInfo(*TM->getMCAsmInfo(), *TM->getRegisterInfo(),
+ &TM->getTargetLowering()->getObjFileLowering());
+ PM.add(MMI);
+ MCContext *Context = &MMI->getContext(); // Return the MCContext specifically by-ref.
+
+ // Set up a MachineFunction for the rest of CodeGen to work on.
+ PM.add(new MachineFunctionAnalysis(*TM));
+
+ // Enable FastISel with -fast, but allow that to be overridden.
+ if (EnableFastISelOption == cl::BOU_TRUE ||
+ (TM->getOptLevel() == CodeGenOpt::None &&
+ EnableFastISelOption != cl::BOU_FALSE))
+ TM->setFastISel(true);
+
+ // Ask the target for an isel.
+ if (PassConfig->addInstSelector())
+ return NULL;
+
+ PassConfig->addMachinePasses();
+
+ return Context;
+}
+
bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
formatted_raw_ostream &Out,
CodeGenFileType FileType,
bool DisableVerify) {
// Add common CodeGen passes.
- MCContext *Context = 0;
- TargetPassConfig *PassConfig = createPassConfig(PM, DisableVerify);
- PM.add(PassConfig);
- if (PassConfig->addCodeGenPasses(Context))
+ MCContext *Context = addPassesToGenerateCode(this, PM, DisableVerify);
+ if (!Context)
return true;
- assert(Context != 0 && "Failed to get MCContext");
if (hasMCSaveTempLabels())
Context->setAllowTemporaryLabels(false);
JITCodeEmitter &JCE,
bool DisableVerify) {
// Add common CodeGen passes.
- MCContext *Ctx = 0;
- OwningPtr<TargetPassConfig> PassConfig(createPassConfig(PM, DisableVerify));
- if (PassConfig->addCodeGenPasses(Ctx))
+ MCContext *Context = addPassesToGenerateCode(this, PM, DisableVerify);
+ if (!Context)
return true;
addCodeEmitter(PM, JCE);
raw_ostream &Out,
bool DisableVerify) {
// Add common CodeGen passes.
- OwningPtr<TargetPassConfig> PassConfig(createPassConfig(PM, DisableVerify));
- if (PassConfig->addCodeGenPasses(Ctx))
+ Ctx = addPassesToGenerateCode(this, PM, DisableVerify);
+ if (!Ctx)
return true;
if (hasMCSaveTempLabels())
#include "llvm/Transforms/Scalar.h"
#include "llvm/PassManager.h"
#include "llvm/CodeGen/GCStrategy.h"
-#include "llvm/CodeGen/MachineFunctionAnalysis.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/Target/TargetLowering.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/MC/MCAsmInfo.h"
#include "llvm/Assembly/PrintModulePass.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
cl::desc("Verify generated machine code"),
cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
-// Enable or disable FastISel. Both options are needed, because
-// FastISel is enabled by default with -fast, and we wish to be
-// able to enable or disable fast-isel independently from -O0.
-static cl::opt<cl::boolOrDefault>
-EnableFastISelOption("fast-isel", cl::Hidden,
- cl::desc("Enable the \"fast\" instruction selector"));
-
//===---------------------------------------------------------------------===//
/// TargetPassConfig
//===---------------------------------------------------------------------===//
// Out of line virtual method.
TargetPassConfig::~TargetPassConfig() {}
-TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm,
- bool DisableVerifyFlag)
- : ImmutablePass(ID), TM(tm), PM(pm), DisableVerify(DisableVerifyFlag) {
+TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm)
+ : ImmutablePass(ID), TM(tm), PM(pm), DisableVerify(false) {
// Register all target independent codegen passes to activate their PassIDs,
// including this pass itself.
initializeCodeGen(*PassRegistry::getPassRegistry());
/// addPassToEmitX methods for generating a pipeline of CodeGen passes.
///
/// Targets may override this to extend TargetPassConfig.
-TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM,
- bool DisableVerify) {
- return new TargetPassConfig(this, PM, DisableVerify);
+TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) {
+ return new TargetPassConfig(this, PM);
}
TargetPassConfig::TargetPassConfig()
llvm_unreachable("TargetPassConfig should not be constructed on-the-fly");
}
+void TargetPassConfig::addCommonPass(char &ID) {
+ // FIXME: about to be implemented.
+}
void TargetPassConfig::printNoVerify(const char *Banner) const {
if (TM->shouldPrintMachineCode())
PM.add(createMachineVerifierPass(Banner));
}
-/// addCodeGenPasses - Add standard LLVM codegen passes used for both
-/// emitting to assembly files or machine code output.
-///
-bool TargetPassConfig::addCodeGenPasses(MCContext *&OutContext) {
- // Standard LLVM-Level Passes.
-
+/// Add common target configurable passes that perform LLVM IR to IR transforms
+/// following machine independent optimization.
+void TargetPassConfig::addIRPasses() {
// Basic AliasAnalysis support.
// Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
// BasicAliasAnalysis wins if they disagree. This is intended to help
// Make sure that no unreachable blocks are instruction selected.
PM.add(createUnreachableBlockEliminationPass());
+}
- // Turn exception handling constructs into something the code generators can
- // handle.
- switch (TM->getMCAsmInfo()->getExceptionHandlingType()) {
- case ExceptionHandling::SjLj:
- // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
- // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
- // catch info can get misplaced when a selector ends up more than one block
- // removed from the parent invoke(s). This could happen when a landing
- // pad is shared by multiple invokes and is also a target of a normal
- // edge from elsewhere.
- PM.add(createSjLjEHPass(getTargetLowering()));
- // FALLTHROUGH
- case ExceptionHandling::DwarfCFI:
- case ExceptionHandling::ARM:
- case ExceptionHandling::Win64:
- PM.add(createDwarfEHPass(TM));
- break;
- case ExceptionHandling::None:
- PM.add(createLowerInvokePass(getTargetLowering()));
-
- // The lower invoke pass may create unreachable code. Remove it.
- PM.add(createUnreachableBlockEliminationPass());
- break;
- }
-
+/// Add common passes that perform LLVM IR to IR transforms in preparation for
+/// instruction selection.
+void TargetPassConfig::addISelPrepare() {
if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
PM.add(createCodeGenPreparePass(getTargetLowering()));
// to ensure that the IR is valid.
if (!DisableVerify)
PM.add(createVerifierPass());
+}
- // Standard Lower-Level Passes.
-
- // Install a MachineModuleInfo class, which is an immutable pass that holds
- // all the per-module stuff we're generating, including MCContext.
- MachineModuleInfo *MMI =
- new MachineModuleInfo(*TM->getMCAsmInfo(), *TM->getRegisterInfo(),
- &getTargetLowering()->getObjFileLowering());
- PM.add(MMI);
- OutContext = &MMI->getContext(); // Return the MCContext specifically by-ref.
-
- // Set up a MachineFunction for the rest of CodeGen to work on.
- PM.add(new MachineFunctionAnalysis(*TM));
-
- // Enable FastISel with -fast, but allow that to be overridden.
- if (EnableFastISelOption == cl::BOU_TRUE ||
- (getOptLevel() == CodeGenOpt::None &&
- EnableFastISelOption != cl::BOU_FALSE))
- TM->setFastISel(true);
-
- // Ask the target for an isel.
- if (addInstSelector())
- return true;
-
+void TargetPassConfig::addMachinePasses() {
// Print the instruction selected machine code...
printAndVerify("After Instruction Selection");
if (addPreEmitPass())
printNoVerify("After PreEmit passes");
-
- return false;
}
//===---------------------------------------------------------------------===//
/// ARM Code Generator Pass Configuration Options.
class ARMPassConfig : public TargetPassConfig {
public:
- ARMPassConfig(ARMBaseTargetMachine *TM, PassManagerBase &PM,
- bool DisableVerifyFlag)
- : TargetPassConfig(TM, PM, DisableVerifyFlag) {}
+ ARMPassConfig(ARMBaseTargetMachine *TM, PassManagerBase &PM)
+ : TargetPassConfig(TM, PM) {}
ARMBaseTargetMachine &getARMTargetMachine() const {
return getTM<ARMBaseTargetMachine>();
};
} // namespace
-TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM,
- bool DisableVerify) {
- return new ARMPassConfig(this, PM, DisableVerify);
+TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
+ return new ARMPassConfig(this, PM);
}
bool ARMPassConfig::addPreISel() {
}
// Pass Pipeline Configuration
- virtual TargetPassConfig *createPassConfig(PassManagerBase &PM, bool DisableVerify);
+ virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
virtual bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &MCE);
};
/// SPU Code Generator Pass Configuration Options.
class SPUPassConfig : public TargetPassConfig {
public:
- SPUPassConfig(SPUTargetMachine *TM, PassManagerBase &PM,
- bool DisableVerifyFlag)
- : TargetPassConfig(TM, PM, DisableVerifyFlag) {}
+ SPUPassConfig(SPUTargetMachine *TM, PassManagerBase &PM)
+ : TargetPassConfig(TM, PM) {}
SPUTargetMachine &getSPUTargetMachine() const {
return getTM<SPUTargetMachine>();
};
} // namespace
-TargetPassConfig *SPUTargetMachine::createPassConfig(PassManagerBase &PM,
- bool DisableVerify) {
- return new SPUPassConfig(this, PM, DisableVerify);
+TargetPassConfig *SPUTargetMachine::createPassConfig(PassManagerBase &PM) {
+ return new SPUPassConfig(this, PM);
}
bool SPUPassConfig::addInstSelector() {
}
// Pass Pipeline Configuration
- virtual TargetPassConfig *createPassConfig(PassManagerBase &PM,
- bool DisableVerify);
+ virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
};
} // end namespace llvm
/// Hexagon Code Generator Pass Configuration Options.
class HexagonPassConfig : public TargetPassConfig {
public:
- HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM,
- bool DisableVerifyFlag)
- : TargetPassConfig(TM, PM, DisableVerifyFlag) {}
+ HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
+ : TargetPassConfig(TM, PM) {}
HexagonTargetMachine &getHexagonTargetMachine() const {
return getTM<HexagonTargetMachine>();
};
} // namespace
-TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM,
- bool DisableVerify) {
- return new HexagonPassConfig(this, PM, DisableVerify);
+TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
+ return new HexagonPassConfig(this, PM);
}
bool HexagonPassConfig::addInstSelector() {
// Pass Pipeline Configuration.
virtual bool addPassesForOptimizations(PassManagerBase &PM);
- virtual TargetPassConfig *createPassConfig(PassManagerBase &PM,
- bool DisableVerify);
+ virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
};
extern bool flag_aligned_memcpy;
/// MBlaze Code Generator Pass Configuration Options.
class MBlazePassConfig : public TargetPassConfig {
public:
- MBlazePassConfig(MBlazeTargetMachine *TM, PassManagerBase &PM,
- bool DisableVerifyFlag)
- : TargetPassConfig(TM, PM, DisableVerifyFlag) {}
+ MBlazePassConfig(MBlazeTargetMachine *TM, PassManagerBase &PM)
+ : TargetPassConfig(TM, PM) {}
MBlazeTargetMachine &getMBlazeTargetMachine() const {
return getTM<MBlazeTargetMachine>();
};
} // namespace
-TargetPassConfig *MBlazeTargetMachine::createPassConfig(PassManagerBase &PM,
- bool DisableVerify) {
- return new MBlazePassConfig(this, PM, DisableVerify);
+TargetPassConfig *MBlazeTargetMachine::createPassConfig(PassManagerBase &PM) {
+ return new MBlazePassConfig(this, PM);
}
// Install an instruction selector pass using
}
// Pass Pipeline Configuration
- virtual TargetPassConfig *createPassConfig(PassManagerBase &PM,
- bool DisableVerify);
+ virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
};
} // End llvm namespace
/// MSP430 Code Generator Pass Configuration Options.
class MSP430PassConfig : public TargetPassConfig {
public:
- MSP430PassConfig(MSP430TargetMachine *TM, PassManagerBase &PM,
- bool DisableVerifyFlag)
- : TargetPassConfig(TM, PM, DisableVerifyFlag) {}
+ MSP430PassConfig(MSP430TargetMachine *TM, PassManagerBase &PM)
+ : TargetPassConfig(TM, PM) {}
MSP430TargetMachine &getMSP430TargetMachine() const {
return getTM<MSP430TargetMachine>();
};
} // namespace
-TargetPassConfig *MSP430TargetMachine::createPassConfig(PassManagerBase &PM,
- bool DisableVerify) {
- return new MSP430PassConfig(this, PM, DisableVerify);
+TargetPassConfig *MSP430TargetMachine::createPassConfig(PassManagerBase &PM) {
+ return new MSP430PassConfig(this, PM);
}
bool MSP430PassConfig::addInstSelector() {
return &TSInfo;
}
- virtual TargetPassConfig *createPassConfig(PassManagerBase &PM,
- bool DisableVerify);
+ virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
}; // MSP430TargetMachine.
} // end namespace llvm
/// Mips Code Generator Pass Configuration Options.
class MipsPassConfig : public TargetPassConfig {
public:
- MipsPassConfig(MipsTargetMachine *TM, PassManagerBase &PM,
- bool DisableVerifyFlag)
- : TargetPassConfig(TM, PM, DisableVerifyFlag) {}
+ MipsPassConfig(MipsTargetMachine *TM, PassManagerBase &PM)
+ : TargetPassConfig(TM, PM) {}
MipsTargetMachine &getMipsTargetMachine() const {
return getTM<MipsTargetMachine>();
};
} // namespace
-TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM,
- bool DisableVerify) {
- return new MipsPassConfig(this, PM, DisableVerify);
+TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) {
+ return new MipsPassConfig(this, PM);
}
// Install an instruction selector pass using
}
// Pass Pipeline Configuration
- virtual TargetPassConfig *createPassConfig(PassManagerBase &PM,
- bool DisableVerify);
+ virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
virtual bool addCodeEmitter(PassManagerBase &PM,
JITCodeEmitter &JCE);
/// PTX Code Generator Pass Configuration Options.
class PTXPassConfig : public TargetPassConfig {
public:
- PTXPassConfig(PTXTargetMachine *TM, PassManagerBase &PM, bool DisableVerifyFlag)
- : TargetPassConfig(TM, PM, DisableVerifyFlag) {}
+ PTXPassConfig(PTXTargetMachine *TM, PassManagerBase &PM)
+ : TargetPassConfig(TM, PM) {}
PTXTargetMachine &getPTXTargetMachine() const {
return getTM<PTXTargetMachine>();
};
} // namespace
-TargetPassConfig *PTXTargetMachine::createPassConfig(PassManagerBase &PM,
- bool DisableVerify) {
- return new PTXPassConfig(this, PM, DisableVerify);
+TargetPassConfig *PTXTargetMachine::createPassConfig(PassManagerBase &PM) {
+ return new PTXPassConfig(this, PM);
}
bool PTXPassConfig::addInstSelector() {
// Add common CodeGen passes.
MCContext *Context = 0;
- OwningPtr<TargetPassConfig> PassConfig(createPassConfig(PM, DisableVerify));
+
+ // FIXME: soon this will be converted to use the exposed TargetPassConfig API.
+ OwningPtr<PTXPassConfig> PassConfig(
+ static_cast<PTXPassConfig*>(createPassConfig(PM)));
+
+ PassConfig->setDisableVerify(DisableVerify);
+
if (PassConfig->addCodeGenPasses(Context))
return true;
assert(Context != 0 && "Failed to get MCContext");
}
// Pass Pipeline Configuration
- virtual TargetPassConfig *createPassConfig(PassManagerBase &PM,
- bool DisableVerify);
+ virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
}; // class PTXTargetMachine
/// PPC Code Generator Pass Configuration Options.
class PPCPassConfig : public TargetPassConfig {
public:
- PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM,
- bool DisableVerifyFlag)
- : TargetPassConfig(TM, PM, DisableVerifyFlag) {}
+ PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
+ : TargetPassConfig(TM, PM) {}
PPCTargetMachine &getPPCTargetMachine() const {
return getTM<PPCTargetMachine>();
};
} // namespace
-TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM,
- bool DisableVerify) {
- return new PPCPassConfig(this, PM, DisableVerify);
+TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
+ return new PPCPassConfig(this, PM);
}
bool PPCPassConfig::addInstSelector() {
}
// Pass Pipeline Configuration
- virtual TargetPassConfig *createPassConfig(PassManagerBase &PM,
- bool DisableVerify);
+ virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
virtual bool addCodeEmitter(PassManagerBase &PM,
JITCodeEmitter &JCE);
};
/// Sparc Code Generator Pass Configuration Options.
class SparcPassConfig : public TargetPassConfig {
public:
- SparcPassConfig(SparcTargetMachine *TM, PassManagerBase &PM,
- bool DisableVerifyFlag)
- : TargetPassConfig(TM, PM, DisableVerifyFlag) {}
+ SparcPassConfig(SparcTargetMachine *TM, PassManagerBase &PM)
+ : TargetPassConfig(TM, PM) {}
SparcTargetMachine &getSparcTargetMachine() const {
return getTM<SparcTargetMachine>();
};
} // namespace
-TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM,
- bool DisableVerify) {
- return new SparcPassConfig(this, PM, DisableVerify);
+TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) {
+ return new SparcPassConfig(this, PM);
}
bool SparcPassConfig::addInstSelector() {
virtual const TargetData *getTargetData() const { return &DataLayout; }
// Pass Pipeline Configuration
- virtual TargetPassConfig *createPassConfig(PassManagerBase &PM,
- bool DisableVerify);
+ virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
};
/// SparcV8TargetMachine - Sparc 32-bit target machine
/// X86 Code Generator Pass Configuration Options.
class X86PassConfig : public TargetPassConfig {
public:
- X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM,
- bool DisableVerifyFlag)
- : TargetPassConfig(TM, PM, DisableVerifyFlag) {}
+ X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM)
+ : TargetPassConfig(TM, PM) {}
X86TargetMachine &getX86TargetMachine() const {
return getTM<X86TargetMachine>();
};
} // namespace
-TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM,
- bool DisableVerify) {
- return new X86PassConfig(this, PM, DisableVerify);
+TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
+ return new X86PassConfig(this, PM);
}
bool X86PassConfig::addInstSelector() {
}
// Set up the pass pipeline.
- virtual TargetPassConfig *createPassConfig(PassManagerBase &PM,
- bool DisableVerify);
+ virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
virtual bool addCodeEmitter(PassManagerBase &PM,
JITCodeEmitter &JCE);
/// XCore Code Generator Pass Configuration Options.
class XCorePassConfig : public TargetPassConfig {
public:
- XCorePassConfig(XCoreTargetMachine *TM, PassManagerBase &PM,
- bool DisableVerifyFlag)
- : TargetPassConfig(TM, PM, DisableVerifyFlag) {}
+ XCorePassConfig(XCoreTargetMachine *TM, PassManagerBase &PM)
+ : TargetPassConfig(TM, PM) {}
XCoreTargetMachine &getXCoreTargetMachine() const {
return getTM<XCoreTargetMachine>();
};
} // namespace
-TargetPassConfig *XCoreTargetMachine::createPassConfig(PassManagerBase &PM,
- bool DisableVerify) {
- return new XCorePassConfig(this, PM, DisableVerify);
+TargetPassConfig *XCoreTargetMachine::createPassConfig(PassManagerBase &PM) {
+ return new XCorePassConfig(this, PM);
}
bool XCorePassConfig::addInstSelector() {
virtual const TargetData *getTargetData() const { return &DataLayout; }
// Pass Pipeline Configuration
- virtual TargetPassConfig *createPassConfig(PassManagerBase &PM,
- bool DisableVerify);
+ virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
};
} // end namespace llvm
projects / oota-llvm.git / commitdiff