[ARM] Add support for Cortex-M7, FPv5-SP and FPv5-DP (LLVM)
authorOliver Stannard <oliver.stannard@arm.com>
Wed, 1 Oct 2014 09:02:17 +0000 (09:02 +0000)
committerOliver Stannard <oliver.stannard@arm.com>
Wed, 1 Oct 2014 09:02:17 +0000 (09:02 +0000)
commitff18b9ff38e4044ea4acb8c8f1751653c1ac7697
tree73b0314152ef46bae89e71a13a10a7ba1654c521
parent9a11fba79f93aad7765d394c7d062e0678efdbf8
[ARM] Add support for Cortex-M7, FPv5-SP and FPv5-DP (LLVM)

The Cortex-M7 has 3 options for its FPU: none, FPv5-SP-D16 and
FPv5-DP-D16. FPv5 has the same instructions as FP-ARMv8, so it can be
modelled using the same target feature, and all double-precision
operations are already disabled by the fp-only-sp target features.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218747 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/ARM/ARM.td
lib/Target/ARM/ARMAsmPrinter.cpp
lib/Target/ARM/ARMFPUName.def
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
test/CodeGen/ARM/build-attributes.ll
test/CodeGen/Thumb2/cortex-fp.ll
test/CodeGen/Thumb2/float-cmp.ll
test/CodeGen/Thumb2/float-intrinsics-double.ll
test/CodeGen/Thumb2/float-intrinsics-float.ll
test/CodeGen/Thumb2/float-ops.ll