Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the disassem...
authorSilviu Baranga <silviu.baranga@arm.com>
Wed, 18 Apr 2012 13:12:50 +0000 (13:12 +0000)
committerSilviu Baranga <silviu.baranga@arm.com>
Wed, 18 Apr 2012 13:12:50 +0000 (13:12 +0000)
commitfa1ebc6abe95b79b7f82030eea53586a8704eb7e
tree158b6ad7a4ddd16be07017fc6616a12f9bd8e53b
parente546c4c9c3004274c8e275e8303ca078b794bf28
Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the disassembler. Since the upredicability conditions are complex, C++ code was added to handle them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155001 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/ARM/ARMInstrInfo.td
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt [new file with mode: 0644]
test/MC/Disassembler/ARM/unpredictable-MRRC2-arm.txt [new file with mode: 0644]