LLVM support for vector quad bit permute and gather instructions through builtins
authorNemanja Ivanovic <nemanja.i.ibm@gmail.com>
Thu, 11 Jun 2015 06:21:25 +0000 (06:21 +0000)
committerNemanja Ivanovic <nemanja.i.ibm@gmail.com>
Thu, 11 Jun 2015 06:21:25 +0000 (06:21 +0000)
commitf7d6501d1dfe8ceba0bc3d26850f94e6d8604567
tree0471f464858b1ccc3364d7bd3e9662361dd264bb
parent7963762fcef932e36d0ac0e7ee0af823eefbe2c2
LLVM support for vector quad bit permute and gather instructions through builtins

This patch corresponds to review:
http://reviews.llvm.org/D10096

This is the back end portion of the patch related to D10095.
The patch adds the instructions and back end intrinsics for:
vbpermq
vgbbd

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239505 91177308-0d34-0410-b5e6-96231b3b80d8
include/llvm/IR/IntrinsicsPowerPC.td
lib/Target/PowerPC/PPCInstrAltivec.td
test/CodeGen/PowerPC/builtins-ppc-p8vector.ll [new file with mode: 0644]
test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
test/MC/PowerPC/ppc64-encoding-vmx.s