This change implements the following three logical vector operations:
authorKit Barton <kbarton@ca.ibm.com>
Mon, 9 Feb 2015 17:03:18 +0000 (17:03 +0000)
committerKit Barton <kbarton@ca.ibm.com>
Mon, 9 Feb 2015 17:03:18 +0000 (17:03 +0000)
commitf60b0de42a8bb5ead55022c6342527bf31f8fbb8
tree26a43eee177fa9b3e39bfc72b650b86a2c32c8c8
parent50c61d25691d4767283a37d3d71e9ba84b4ac7d9
This change implements the following three logical vector operations:

veqv (vector equivalence)
vnand
vorc
I increased the AddedComplexity for these instructions to 500 to ensure they are generated instead of issuing other VSX instructions.

Phabricator review: http://reviews.llvm.org/D7469

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228580 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/PowerPC/PPCInstrAltivec.td
test/CodeGen/PowerPC/vec_veqv_vnand_vorc.ll [new file with mode: 0644]
test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
test/MC/PowerPC/ppc64-encoding-vmx.s