MachineVerifier: Allow undef reads if a matching superreg is defined.

MachineVerifier: Allow undef reads if a matching superreg is defined.

Summary:
Some pseudo instruction expansions break down a wide register use into
multiple uses of smaller sub registers. If the super register was
partially undefined the broken down sub registers may be completely
undefined now leading to MachineVerifier complaints. Unfortunately
liveness information to add the required dead flags is not easily
(cheaply) available when expanding pseudo instructions.

This commit changes the verifier to be quiet if there is an additional
implicit use of a super register. Pseudo instruction expanders can use
this to mark cases where partially defined values get potentially broken
into completely undefined ones.

Differential Revision: http://reviews.llvm.org/D6973

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226047 91177308-0d34-0410-b5e6-96231b3b80d8