Fix the invalid opcode for Mips branch instructions in the assembler

Fix the invalid opcode for Mips branch instructions in the assembler

For mips a branch an 18-bit signed offset (the 16-bit
offset field shifted left 2 bits) is added to the
address of the instruction following the branch
(not the branch itself), in the branch delay slot,
to form a PC-relative effective target address.

Previously, the code generator did not perform the
shift of the immediate branch offset which resulted
in wrong instruction opcode. This patch fixes the issue.

Contributor: Vladimir Medic

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177687 91177308-0d34-0410-b5e6-96231b3b80d8