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(parent: b062a9b) | patch
MIR Parser: Verify the implicit machine register operands.
authorAlex Lorenz <arphaman@gmail.com>
Tue, 7 Jul 2015 02:08:46 +0000 (02:08 +0000)
committerAlex Lorenz <arphaman@gmail.com>
Tue, 7 Jul 2015 02:08:46 +0000 (02:08 +0000)
commitd0ef9f31157a9159cf6f2c62b7e4538cbdc81642
treee71d1d1f2a4bd81ef87b529b916b39e4b0cd824btree | snapshot
parentb062a9b4116823a5f9a4c0629d82cfbe443e1766commit | diff
MIR Parser: Verify the implicit machine register operands.

This commit verifies that the parsed machine instructions contain the implicit
register operands as specified by the MCInstrDesc. Variadic and call
instructions aren't verified.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10781

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241537 91177308-0d34-0410-b5e6-96231b3b80d8
13 files changed:
lib/CodeGen/MIRParser/MIParser.cpp diff | blob | history
test/CodeGen/MIR/X86/expected-different-implicit-operand.mir [new file with mode: 0644] blob
test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir [new file with mode: 0644] blob
test/CodeGen/MIR/X86/expected-number-after-bb.mir diff | blob | history
test/CodeGen/MIR/X86/global-value-operands.mir diff | blob | history
test/CodeGen/MIR/X86/large-index-number-error.mir diff | blob | history
test/CodeGen/MIR/X86/machine-basic-block-operands.mir diff | blob | history
test/CodeGen/MIR/X86/machine-instructions.mir diff | blob | history
test/CodeGen/MIR/X86/missing-implicit-operand.mir [new file with mode: 0644] blob
test/CodeGen/MIR/X86/named-registers.mir diff | blob | history
test/CodeGen/MIR/X86/register-mask-operands.mir diff | blob | history
test/CodeGen/MIR/X86/unknown-machine-basic-block.mir diff | blob | history
test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir diff | blob | history
C/C++ LLVM-based compilers that forbids OOTA behaviors