Optimize some special cases for SSE4a insertqi
authorFilipe Cabecinhas <me@filcab.net>
Thu, 24 Apr 2014 00:38:14 +0000 (00:38 +0000)
committerFilipe Cabecinhas <me@filcab.net>
Thu, 24 Apr 2014 00:38:14 +0000 (00:38 +0000)
commitcd9f6b870ef0660ad4023d34a32c21c0d66516e6
tree02822ba2abcd228738fa907e78ad0bcb568bbb40
parent8bd9405026b50394e173a4b3159aacd841efe564
Optimize some special cases for SSE4a insertqi

Summary:
Since the upper 64 bits of the destination register are undefined when
performing this operation, we can substitute it and let the optimizer
figure out that only a copy is needed.

Also added range merging, if an instruction copies a range that can be
merged with a previous copied range.

Added test cases for both optimizations.

Reviewers: grosbach, nadav

CC: llvm-commits
Differential Revision: http://reviews.llvm.org/D3357

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207055 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Transforms/InstCombine/InstCombineCalls.cpp
test/Transforms/InstCombine/vec_demanded_elts.ll