A7.3 register encoding
authorJohnny Chen <johnny.chen@apple.com>
Tue, 5 Apr 2011 22:57:07 +0000 (22:57 +0000)
committerJohnny Chen <johnny.chen@apple.com>
Tue, 5 Apr 2011 22:57:07 +0000 (22:57 +0000)
commitc3281c10c94185e18338764b225a730a7c3e3ec4
treed2501307a259747e16299c200c92fa38cd648f46
parentda19475328ece3da19437a2e9eef035dcafa2814
A7.3 register encoding
    Qd -> bit[12] == 0
    Qn -> bit[16] == 0
    Qm -> bit[0]  == 0

If one of these bits is 1, the instruction is UNDEFINED.

rdar://problem/9238399
rdar://problem/9238445

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128949 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
test/MC/Disassembler/ARM/invalid-VQADD-arm.txt [new file with mode: 0644]
test/MC/Disassembler/ARM/neon-tests.txt