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(parent: 02d2e61) | patch
Optimize vector select from all 0s or all 1s
authorMichael Liao <michael.liao@intel.com>
Thu, 11 Apr 2013 05:15:54 +0000 (05:15 +0000)
committerMichael Liao <michael.liao@intel.com>
Thu, 11 Apr 2013 05:15:54 +0000 (05:15 +0000)
commitbf53841cfe3c341ebc0fca102d641c2018855254
tree0288e1038ed3afd3eadc5ecf44b98d8dec9e63a3tree | snapshot
parent02d2e612521954b5ff7c1ba6fd53e36bc51e1c48commit | diff
Optimize vector select from all 0s or all 1s

As packed comparisons in AVX/SSE produce all 0s or all 1s in each SIMD lane,
vector select could be simplified to AND/OR or removed if one or both values
being selected is all 0s or all 1s.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179267 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86ISelLowering.cpp diff | blob | history
test/CodeGen/X86/select-with-and-or.ll [new file with mode: 0644] blob
C/C++ LLVM-based compilers that forbids OOTA behaviors