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(parent: 3fe91a4) | patch
Mips assembler: Explicit floating point condition register recognition.
authorJack Carter <jack.carter@imgtec.com>
Mon, 15 Apr 2013 22:21:55 +0000 (22:21 +0000)
committerJack Carter <jack.carter@imgtec.com>
Mon, 15 Apr 2013 22:21:55 +0000 (22:21 +0000)
commitb8145e3881872fffbac15693c94536446f060330
treeb61b7cda938b0b17eaee1195df4057613aebcfa4tree | snapshot
parent3fe91a4453cad041f038398de978679106b5ed67commit | diff
Mips assembler: Explicit floating point condition register recognition.

This patch allows the assembler to recognize $fcc0
as a valid register for conditional move instructions.

Corresponding test cases have been added.

Contributer: Vladimir Medic

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179567 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/Mips/AsmParser/MipsAsmParser.cpp diff | blob | history
test/MC/Mips/mips-fpu-instructions.s diff | blob | history
C/C++ LLVM-based compilers that forbids OOTA behaviors