Revert 202433 - Provide a target override for the latest regalloc heuristic
authorRenato Golin <renato.golin@linaro.org>
Fri, 3 Oct 2014 12:20:53 +0000 (12:20 +0000)
committerRenato Golin <renato.golin@linaro.org>
Fri, 3 Oct 2014 12:20:53 +0000 (12:20 +0000)
commitb157cb7afd6789d0b43fbe0804fbfca030d718ef
tree6ffa4a1d561d3dfa5b36f1b4db123d85bdb8152f
parent7ae6f2abf6c6ac1cd2ff03dc82f1e15138d95757
Revert 202433 - Provide a target override for the latest regalloc heuristic

That commit was introduced in order to help investigate a problem in ARM
codegen breaking from commit 202304 (Add a limit to the heuristic that register
allocates instructions in local order). Recent analisys indicated that the
problem no longer exists, so I'm reverting this change.

See PR18996.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218981 91177308-0d34-0410-b5e6-96231b3b80d8
include/llvm/Target/TargetRegisterInfo.h
lib/CodeGen/RegAllocGreedy.cpp
lib/Target/ARM/ARMBaseRegisterInfo.cpp
lib/Target/ARM/ARMBaseRegisterInfo.h
test/CodeGen/ARM/vldm-sched-a9.ll