teach SimplifyDemandedBits that exact shifts demand the bits they
authorChris Lattner <sabre@nondot.org>
Thu, 10 Feb 2011 05:09:34 +0000 (05:09 +0000)
committerChris Lattner <sabre@nondot.org>
Thu, 10 Feb 2011 05:09:34 +0000 (05:09 +0000)
commita81556fb52e39e3f6cde0c11c1acd2bdf8a560a2
tree2a94b97bd825bc7bd08c100423b9dd93b32d17e2
parent4d96c638af0458f4de637998da942a5e166d6ea5
teach SimplifyDemandedBits that exact shifts demand the bits they
are shifting out since they do require them to be zeros.  Similarly
for NUW/NSW bits of shl

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125263 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp