[mips] Fix delay slot filler so that instructions with register operand $1 are
authorAkira Hatanaka <ahatanaka@mips.com>
Fri, 16 Nov 2012 02:39:34 +0000 (02:39 +0000)
committerAkira Hatanaka <ahatanaka@mips.com>
Fri, 16 Nov 2012 02:39:34 +0000 (02:39 +0000)
commita032dbd62f46a40b2cf759ce0dd0ebd41ef0614c
tree1526a67e09837250eaa27e9da8776f1710166ad3
parent96952bd3b10d6a880b406461e2373b8781abc919
[mips] Fix delay slot filler so that instructions with register operand $1 are
allowed in branch delay slot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168131 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/Mips/MipsDelaySlotFiller.cpp
test/CodeGen/Mips/brdelayslot.ll