This patch adds support for the vector quadword add/sub instructions introduced
authorKit Barton <kbarton@ca.ibm.com>
Mon, 25 May 2015 15:49:26 +0000 (15:49 +0000)
committerKit Barton <kbarton@ca.ibm.com>
Mon, 25 May 2015 15:49:26 +0000 (15:49 +0000)
commit948ecae20e91da3f16898827a4c9c505ba1a988f
tree21730025fad7f8a7d9477e6ac99c76ccec2d2550
parent68c5b83e1219c4803d4974b8007cc4c000c74602
This patch adds support for the vector quadword add/sub instructions introduced
in POWER8:

vadduqm
vaddeuqm
vaddcuq
vaddecuq
vsubuqm
vsubeuqm
vsubcuq
vsubecuq
In addition to adding the instructions themselves, it also adds support for the
v1i128 type for intrinsics (Intrinsics.td, Function.cpp, and
IntrinsicEmitter.cpp).

http://reviews.llvm.org/D9081

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238144 91177308-0d34-0410-b5e6-96231b3b80d8
include/llvm/IR/Intrinsics.td
include/llvm/IR/IntrinsicsPowerPC.td
lib/IR/Function.cpp
lib/Target/PowerPC/PPCISelLowering.cpp
lib/Target/PowerPC/PPCInstrAltivec.td
test/CodeGen/PowerPC/ppc64-i128-abi.ll
test/CodeGen/PowerPC/vec_add_sub_quadword.ll [new file with mode: 0644]
test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
test/MC/PowerPC/ppc64-encoding-vmx.s
utils/TableGen/IntrinsicEmitter.cpp